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13#ifndef __TSEC_H
14#define __TSEC_H
15
16#include <net.h>
17#include <config.h>
18#include <phy.h>
19
20#define TSEC_MDIO_REGS_OFFSET 0x520
21
22#ifndef CONFIG_DM_ETH
23
24#ifdef CONFIG_ARCH_LS1021A
25#define TSEC_SIZE 0x40000
26#define TSEC_MDIO_OFFSET 0x40000
27#else
28#define TSEC_SIZE 0x01000
29#define TSEC_MDIO_OFFSET 0x01000
30#endif
31
32#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
33
34#define TSEC_GET_REGS(num, offset) \
35 (struct tsec __iomem *)\
36 (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
37
38#define TSEC_GET_REGS_BASE(num) \
39 TSEC_GET_REGS((num), TSEC_SIZE)
40
41#define TSEC_GET_MDIO_REGS(num, offset) \
42 (struct tsec_mii_mng __iomem *)\
43 (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
44
45#define TSEC_GET_MDIO_REGS_BASE(num) \
46 TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
47
48#define DEFAULT_MII_NAME "FSL_MDIO"
49
50#define STD_TSEC_INFO(num) \
51{ \
52 .regs = TSEC_GET_REGS_BASE(num), \
53 .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
54 .devname = CONFIG_TSEC##num##_NAME, \
55 .phyaddr = TSEC##num##_PHY_ADDR, \
56 .flags = TSEC##num##_FLAGS, \
57 .mii_devname = DEFAULT_MII_NAME \
58}
59
60#define SET_STD_TSEC_INFO(x, num) \
61{ \
62 x.regs = TSEC_GET_REGS_BASE(num); \
63 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
64 x.devname = CONFIG_TSEC##num##_NAME; \
65 x.phyaddr = TSEC##num##_PHY_ADDR; \
66 x.flags = TSEC##num##_FLAGS;\
67 x.mii_devname = DEFAULT_MII_NAME;\
68}
69
70#endif
71
72#define MAC_ADDR_LEN 6
73
74
75#define TSEC_TIMEOUT 1000
76#define TOUT_LOOP 1000000
77
78
79#define TBI_CR 0x00
80#define TBI_SR 0x01
81#define TBI_ANA 0x04
82#define TBI_ANLPBPA 0x05
83#define TBI_ANEX 0x06
84#define TBI_TBICON 0x11
85
86
87#define TBICON_CLK_SELECT 0x0020
88#define TBIANA_ASYMMETRIC_PAUSE 0x0100
89#define TBIANA_SYMMETRIC_PAUSE 0x0080
90#define TBIANA_HALF_DUPLEX 0x0040
91#define TBIANA_FULL_DUPLEX 0x0020
92#define TBICR_PHY_RESET 0x8000
93#define TBICR_ANEG_ENABLE 0x1000
94#define TBICR_RESTART_ANEG 0x0200
95#define TBICR_FULL_DUPLEX 0x0100
96#define TBICR_SPEED1_SET 0x0040
97
98
99#define MACCFG1_SOFT_RESET 0x80000000
100#define MACCFG1_RESET_RX_MC 0x00080000
101#define MACCFG1_RESET_TX_MC 0x00040000
102#define MACCFG1_RESET_RX_FUN 0x00020000
103#define MACCFG1_RESET_TX_FUN 0x00010000
104#define MACCFG1_LOOPBACK 0x00000100
105#define MACCFG1_RX_FLOW 0x00000020
106#define MACCFG1_TX_FLOW 0x00000010
107#define MACCFG1_SYNCD_RX_EN 0x00000008
108#define MACCFG1_RX_EN 0x00000004
109#define MACCFG1_SYNCD_TX_EN 0x00000002
110#define MACCFG1_TX_EN 0x00000001
111
112#define MACCFG2_INIT_SETTINGS 0x00007205
113#define MACCFG2_FULL_DUPLEX 0x00000001
114#define MACCFG2_IF 0x00000300
115#define MACCFG2_GMII 0x00000200
116#define MACCFG2_MII 0x00000100
117
118#define ECNTRL_INIT_SETTINGS 0x00001000
119#define ECNTRL_TBI_MODE 0x00000020
120#define ECNTRL_REDUCED_MODE 0x00000010
121#define ECNTRL_R100 0x00000008
122#define ECNTRL_REDUCED_MII_MODE 0x00000004
123#define ECNTRL_SGMII_MODE 0x00000002
124
125#ifndef CONFIG_SYS_TBIPA_VALUE
126# define CONFIG_SYS_TBIPA_VALUE 0x1f
127#endif
128
129#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
130
131#define MINFLR_INIT_SETTINGS 0x00000040
132
133#define DMACTRL_INIT_SETTINGS 0x000000c3
134#define DMACTRL_GRS 0x00000010
135#define DMACTRL_GTS 0x00000008
136#define DMACTRL_LE 0x00008000
137
138#define TSTAT_CLEAR_THALT 0x80000000
139#define RSTAT_CLEAR_RHALT 0x00800000
140
141#define IEVENT_INIT_CLEAR 0xffffffff
142#define IEVENT_BABR 0x80000000
143#define IEVENT_RXC 0x40000000
144#define IEVENT_BSY 0x20000000
145#define IEVENT_EBERR 0x10000000
146#define IEVENT_MSRO 0x04000000
147#define IEVENT_GTSC 0x02000000
148#define IEVENT_BABT 0x01000000
149#define IEVENT_TXC 0x00800000
150#define IEVENT_TXE 0x00400000
151#define IEVENT_TXB 0x00200000
152#define IEVENT_TXF 0x00100000
153#define IEVENT_IE 0x00080000
154#define IEVENT_LC 0x00040000
155#define IEVENT_CRL 0x00020000
156#define IEVENT_XFUN 0x00010000
157#define IEVENT_RXB0 0x00008000
158#define IEVENT_GRSC 0x00000100
159#define IEVENT_RXF0 0x00000080
160
161#define IMASK_INIT_CLEAR 0x00000000
162#define IMASK_TXEEN 0x00400000
163#define IMASK_TXBEN 0x00200000
164#define IMASK_TXFEN 0x00100000
165#define IMASK_RXFEN0 0x00000080
166
167
168#define ATTR_INIT_SETTINGS 0x000000c0
169#define ATTRELI_INIT_SETTINGS 0x00000000
170
171
172#define TXBD_READY 0x8000
173#define TXBD_PADCRC 0x4000
174#define TXBD_WRAP 0x2000
175#define TXBD_INTERRUPT 0x1000
176#define TXBD_LAST 0x0800
177#define TXBD_CRC 0x0400
178#define TXBD_DEF 0x0200
179#define TXBD_HUGEFRAME 0x0080
180#define TXBD_LATECOLLISION 0x0080
181#define TXBD_RETRYLIMIT 0x0040
182#define TXBD_RETRYCOUNTMASK 0x003c
183#define TXBD_UNDERRUN 0x0002
184#define TXBD_STATS 0x03ff
185
186
187#define RXBD_EMPTY 0x8000
188#define RXBD_RO1 0x4000
189#define RXBD_WRAP 0x2000
190#define RXBD_INTERRUPT 0x1000
191#define RXBD_LAST 0x0800
192#define RXBD_FIRST 0x0400
193#define RXBD_MISS 0x0100
194#define RXBD_BROADCAST 0x0080
195#define RXBD_MULTICAST 0x0040
196#define RXBD_LARGE 0x0020
197#define RXBD_NONOCTET 0x0010
198#define RXBD_SHORT 0x0008
199#define RXBD_CRCERR 0x0004
200#define RXBD_OVERRUN 0x0002
201#define RXBD_TRUNCATED 0x0001
202#define RXBD_STATS 0x003f
203
204struct txbd8 {
205 uint16_t status;
206 uint16_t length;
207 uint32_t bufptr;
208};
209
210struct rxbd8 {
211 uint16_t status;
212 uint16_t length;
213 uint32_t bufptr;
214};
215
216struct tsec_rmon_mib {
217
218 u32 tr64;
219 u32 tr127;
220 u32 tr255;
221 u32 tr511;
222 u32 tr1k;
223 u32 trmax;
224 u32 trmgv;
225
226 u32 rbyt;
227 u32 rpkt;
228 u32 rfcs;
229 u32 rmca;
230 u32 rbca;
231 u32 rxcf;
232 u32 rxpf;
233 u32 rxuo;
234 u32 raln;
235 u32 rflr;
236 u32 rcde;
237 u32 rcse;
238 u32 rund;
239 u32 rovr;
240 u32 rfrg;
241 u32 rjbr;
242 u32 rdrp;
243
244 u32 tbyt;
245 u32 tpkt;
246 u32 tmca;
247 u32 tbca;
248 u32 txpf;
249 u32 tdfr;
250 u32 tedf;
251 u32 tscl;
252
253 u32 tmcl;
254 u32 tlcl;
255 u32 txcl;
256 u32 tncl;
257
258 u32 res2;
259
260 u32 tdrp;
261 u32 tjbr;
262 u32 tfcs;
263 u32 txcf;
264 u32 tovr;
265 u32 tund;
266 u32 tfrg;
267
268 u32 car1;
269 u32 car2;
270 u32 cam1;
271 u32 cam2;
272};
273
274struct tsec_hash_regs {
275 u32 iaddr0;
276 u32 iaddr1;
277 u32 iaddr2;
278 u32 iaddr3;
279 u32 iaddr4;
280 u32 iaddr5;
281 u32 iaddr6;
282 u32 iaddr7;
283 u32 res1[24];
284 u32 gaddr0;
285 u32 gaddr1;
286 u32 gaddr2;
287 u32 gaddr3;
288 u32 gaddr4;
289 u32 gaddr5;
290 u32 gaddr6;
291 u32 gaddr7;
292 u32 res2[24];
293};
294
295struct tsec {
296
297 u32 res000[4];
298
299 u32 ievent;
300 u32 imask;
301 u32 edis;
302 u32 res01c;
303 u32 ecntrl;
304 u32 minflr;
305 u32 ptv;
306 u32 dmactrl;
307 u32 tbipa;
308
309 u32 res034[3];
310 u32 res040[48];
311
312
313 u32 tctrl;
314 u32 tstat;
315 u32 res108;
316 u32 tbdlen;
317 u32 res110[5];
318 u32 ctbptr;
319 u32 res128[23];
320 u32 tbptr;
321 u32 res188[30];
322
323 u32 res200;
324 u32 tbase;
325 u32 res208[42];
326 u32 ostbd;
327 u32 ostbdp;
328 u32 res2b8[18];
329
330
331 u32 rctrl;
332 u32 rstat;
333 u32 res308;
334 u32 rbdlen;
335 u32 res310[4];
336 u32 res320;
337 u32 crbptr;
338 u32 res328[6];
339 u32 mrblr;
340 u32 res344[16];
341 u32 rbptr;
342 u32 res388[30];
343
344 u32 res400;
345 u32 rbase;
346 u32 res408[62];
347
348
349 u32 maccfg1;
350 u32 maccfg2;
351 u32 ipgifg;
352 u32 hafdup;
353 u32 maxfrm;
354 u32 res514;
355 u32 res518;
356
357 u32 res51c;
358
359 u32 resmdio[6];
360
361 u32 res538;
362
363 u32 ifstat;
364 u32 macstnaddr1;
365 u32 macstnaddr2;
366 u32 res548[46];
367
368
369 u32 res600[32];
370
371
372 struct tsec_rmon_mib rmon;
373 u32 res740[48];
374
375
376 struct tsec_hash_regs hash;
377
378 u32 res900[128];
379
380
381 u32 resb00[62];
382 u32 attr;
383 u32 attreli;
384
385
386 u32 resc00[256];
387};
388
389#define TSEC_GIGABIT (1 << 0)
390
391
392#define TSEC_REDUCED (1 << 1)
393#define TSEC_SGMII (1 << 2)
394
395#define TX_BUF_CNT 2
396
397struct tsec_data {
398 u32 mdio_regs_off;
399};
400
401struct tsec_private {
402 struct txbd8 __iomem txbd[TX_BUF_CNT];
403 struct rxbd8 __iomem rxbd[PKTBUFSRX];
404 struct tsec __iomem *regs;
405 struct tsec_mii_mng __iomem *phyregs_sgmii;
406 struct phy_device *phydev;
407 phy_interface_t interface;
408 struct mii_dev *bus;
409 uint phyaddr;
410 uint tbiaddr;
411 char mii_devname[16];
412 u32 flags;
413 uint rx_idx;
414 uint tx_idx;
415#ifndef CONFIG_DM_ETH
416 struct eth_device *dev;
417#else
418 struct udevice *dev;
419#endif
420};
421
422struct tsec_info_struct {
423 struct tsec __iomem *regs;
424 struct tsec_mii_mng __iomem *miiregs_sgmii;
425 char *devname;
426 char *mii_devname;
427 phy_interface_t interface;
428 unsigned int phyaddr;
429 u32 flags;
430};
431
432#ifndef CONFIG_DM_ETH
433int tsec_standard_init(struct bd_info *bis);
434int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsec_info,
435 int num);
436#endif
437
438#endif
439