LXR uboot/arch/arc/include/asm/io.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
   4 */
   5
   6#ifndef __ASM_ARC_IO_H
   7#define __ASM_ARC_IO_H
   8
   9#include <linux/types.h>
  10#include <asm/byteorder.h>
  11
  12/*
  13 * Compiler barrier. It prevents compiler from reordering instructions before
  14 * and after it. It doesn't prevent HW (CPU) from any reordering though.
  15 */
  16#define __comp_b()              asm volatile("" : : : "memory")
  17
  18#ifdef __ARCHS__
  19
  20/*
  21 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
  22 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
  23 *
  24 * Explicit barrier provided by DMB instruction
  25 *  - Operand supports fine grained load/store/load+store semantics
  26 *  - Ensures that selected memory operation issued before it will complete
  27 *    before any subsequent memory operation of same type
  28 *  - DMB guarantees SMP as well as local barrier semantics
  29 *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
  30 *    UP: barrier(), SMP: smp_*mb == *mb)
  31 *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
  32 *    in the general case. Plus it only provides full barrier.
  33 */
  34
  35#define mb()    asm volatile("dmb 3\n" : : : "memory")
  36#define rmb()   asm volatile("dmb 1\n" : : : "memory")
  37#define wmb()   asm volatile("dmb 2\n" : : : "memory")
  38
  39#else
  40
  41/*
  42 * ARCompact based cores (ARC700) only have SYNC instruction which is super
  43 * heavy weight as it flushes the pipeline as well.
  44 * There are no real SMP implementations of such cores.
  45 */
  46
  47#define mb()    asm volatile("sync\n" : : : "memory")
  48#endif
  49
  50#ifdef __ARCHS__
  51#define __iormb()               rmb()
  52#define __iowmb()               wmb()
  53#else
  54#define __iormb()               __comp_b()
  55#define __iowmb()               __comp_b()
  56#endif
  57
  58static inline void sync(void)
  59{
  60        /* Not yet implemented */
  61}
  62
  63/*
  64 * We must use 'volatile' in C-version read/write IO accessors implementation
  65 * to avoid merging several reads (writes) into one read (write), or optimizing
  66 * them out by compiler.
  67 * We must use compiler barriers before and after operation (read or write) so
  68 * it won't be reordered by compiler.
  69 */
  70#define __arch_getb(a)          ({ u8  __v; __comp_b(); __v = *(volatile u8  *)(a); __comp_b(); __v; })
  71#define __arch_getw(a)          ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
  72#define __arch_getl(a)          ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
  73#define __arch_getq(a)          ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
  74
  75#define __arch_putb(v, a)       ({ __comp_b(); *(volatile u8  *)(a) = (v); __comp_b(); })
  76#define __arch_putw(v, a)       ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
  77#define __arch_putl(v, a)       ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
  78#define __arch_putq(v, a)       ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
  79
  80
  81/*
  82 * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
  83 * it is done for readX and writeX accessors as lots of U-boot driver uses
  84 * __raw_readX / __raw_writeX instead of proper accessor with barrier.
  85 */
  86#define __raw_writeb(v, c)      ({ __iowmb(); __arch_putb(v, c); })
  87#define __raw_writew(v, c)      ({ __iowmb(); __arch_putw(v, c); })
  88#define __raw_writel(v, c)      ({ __iowmb(); __arch_putl(v, c); })
  89#define __raw_writeq(v, c)      ({ __iowmb(); __arch_putq(v, c); })
  90
  91#define __raw_readb(c)          ({ u8  __v = __arch_getb(c); __iormb(); __v; })
  92#define __raw_readw(c)          ({ u16 __v = __arch_getw(c); __iormb(); __v; })
  93#define __raw_readl(c)          ({ u32 __v = __arch_getl(c); __iormb(); __v; })
  94#define __raw_readq(c)          ({ u64 __v = __arch_getq(c); __iormb(); __v; })
  95
  96
  97static inline void __raw_writesb(unsigned long addr, const void *data,
  98                                 int bytelen)
  99{
 100        u8 *buf = (uint8_t *)data;
 101
 102        __iowmb();
 103
 104        while (bytelen--)
 105                __arch_putb(*buf++, addr);
 106}
 107
 108static inline void __raw_writesw(unsigned long addr, const void *data,
 109                                 int wordlen)
 110{
 111        u16 *buf = (uint16_t *)data;
 112
 113        __iowmb();
 114
 115        while (wordlen--)
 116                __arch_putw(*buf++, addr);
 117}
 118
 119static inline void __raw_writesl(unsigned long addr, const void *data,
 120                                 int longlen)
 121{
 122        u32 *buf = (uint32_t *)data;
 123
 124        __iowmb();
 125
 126        while (longlen--)
 127                __arch_putl(*buf++, addr);
 128}
 129
 130static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
 131{
 132        u8 *buf = (uint8_t *)data;
 133
 134        while (bytelen--)
 135                *buf++ = __arch_getb(addr);
 136
 137        __iormb();
 138}
 139
 140static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
 141{
 142        u16 *buf = (uint16_t *)data;
 143
 144        while (wordlen--)
 145                *buf++ = __arch_getw(addr);
 146
 147        __iormb();
 148}
 149
 150static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 151{
 152        u32 *buf = (uint32_t *)data;
 153
 154        while (longlen--)
 155                *buf++ = __arch_getl(addr);
 156
 157        __iormb();
 158}
 159
 160/*
 161 * Relaxed I/O memory access primitives. These follow the Device memory
 162 * ordering rules but do not guarantee any ordering relative to Normal memory
 163 * accesses.
 164 */
 165#define readb_relaxed(c)        ({ u8  __r = __arch_getb(c); __r; })
 166#define readw_relaxed(c)        ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
 167#define readl_relaxed(c)        ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
 168#define readq_relaxed(c)        ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
 169
 170#define writeb_relaxed(v, c)    ((void)__arch_putb((v), (c)))
 171#define writew_relaxed(v, c)    ((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
 172#define writel_relaxed(v, c)    ((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
 173#define writeq_relaxed(v, c)    ((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
 174
 175/*
 176 * MMIO can also get buffered/optimized in micro-arch, so barriers needed
 177 * Based on ARM model for the typical use case
 178 *
 179 *      <ST [DMA buffer]>
 180 *      <writel MMIO "go" reg>
 181 *  or:
 182 *      <readl MMIO "status" reg>
 183 *      <LD [DMA buffer]>
 184 *
 185 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
 186 */
 187#define readb(c)        ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 188#define readw(c)        ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 189#define readl(c)        ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 190#define readq(c)        ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 191
 192#define writeb(v, c)    ({ __iowmb(); writeb_relaxed(v, c); })
 193#define writew(v, c)    ({ __iowmb(); writew_relaxed(v, c); })
 194#define writel(v, c)    ({ __iowmb(); writel_relaxed(v, c); })
 195#define writeq(v, c)    ({ __iowmb(); writeq_relaxed(v, c); })
 196
 197#define out_arch(type, endian, a, v)    __raw_write##type(cpu_to_##endian(v), a)
 198#define in_arch(type, endian, a)        endian##_to_cpu(__raw_read##type(a))
 199
 200#define out_le32(a, v)  out_arch(l, le32, a, v)
 201#define out_le16(a, v)  out_arch(w, le16, a, v)
 202
 203#define in_le32(a)      in_arch(l, le32, a)
 204#define in_le16(a)      in_arch(w, le16, a)
 205
 206#define out_be32(a, v)  out_arch(l, be32, a, v)
 207#define out_be16(a, v)  out_arch(w, be16, a, v)
 208
 209#define in_be32(a)      in_arch(l, be32, a)
 210#define in_be16(a)      in_arch(w, be16, a)
 211
 212#define out_8(a, v)     __raw_writeb(v, a)
 213#define in_8(a)         __raw_readb(a)
 214
 215/*
 216 * Clear and set bits in one shot. These macros can be used to clear and
 217 * set multiple bits in a register using a single call. These macros can
 218 * also be used to set a multiple-bit bit pattern using a mask, by
 219 * specifying the mask in the 'clear' parameter and the new bit pattern
 220 * in the 'set' parameter.
 221 */
 222
 223#define clrbits(type, addr, clear) \
 224        out_##type((addr), in_##type(addr) & ~(clear))
 225
 226#define setbits(type, addr, set) \
 227        out_##type((addr), in_##type(addr) | (set))
 228
 229#define clrsetbits(type, addr, clear, set) \
 230        out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 231
 232#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
 233#define setbits_be32(addr, set) setbits(be32, addr, set)
 234#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 235
 236#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
 237#define setbits_le32(addr, set) setbits(le32, addr, set)
 238#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 239
 240#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
 241#define setbits_be16(addr, set) setbits(be16, addr, set)
 242#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 243
 244#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
 245#define setbits_le16(addr, set) setbits(le16, addr, set)
 246#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 247
 248#define clrbits_8(addr, clear) clrbits(8, addr, clear)
 249#define setbits_8(addr, set) setbits(8, addr, set)
 250#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 251
 252#include <asm-generic/io.h>
 253
 254#endif  /* __ASM_ARC_IO_H */
 255