1config ARCH_LS1021A 2 bool 3 select SYS_FSL_DDR_BE if SYS_FSL_DDR 4 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 5 select SYS_FSL_ERRATUM_A008378 6 select SYS_FSL_ERRATUM_A008407 7 select SYS_FSL_ERRATUM_A008850 8 select SYS_FSL_ERRATUM_A008997 if USB 9 select SYS_FSL_ERRATUM_A009007 if USB 10 select SYS_FSL_ERRATUM_A009008 if USB 11 select SYS_FSL_ERRATUM_A009663 12 select SYS_FSL_ERRATUM_A009798 if USB 13 select SYS_FSL_ERRATUM_A009942 14 select SYS_FSL_ERRATUM_A010315 15 select SYS_FSL_HAS_CCI400 16 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 17 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 18 select SYS_FSL_HAS_SEC 19 select SYS_FSL_SEC_COMPAT_5 20 select SYS_FSL_SEC_LE 21 select SYS_FSL_SRDS_1 22 select SYS_HAS_SERDES 23 select SYS_I2C_MXC 24 imply CMD_PCI 25 imply SCSI 26 imply SCSI_AHCI 27 28menu "LS102xA architecture" 29 depends on ARCH_LS1021A 30 31config LS1_DEEP_SLEEP 32 bool "Deep sleep" 33 34config MAX_CPUS 35 int "Maximum number of CPUs permitted for LS102xA" 36 default 2 37 help 38 Set this number to the maximum number of possible CPUs in the SoC. 39 SoCs may have multiple clusters with each cluster may have multiple 40 ports. If some ports are reserved but higher ports are used for 41 cores, count the reserved ports. This will allocate enough memory 42 in spin table to properly handle all cores. 43 44config NXP_ESBC 45 bool "NXP_ESBC" 46 help 47 Enable Freescale Secure Boot feature. Normally selected 48 by defconfig. If unsure, do not change. 49 50config SYS_CCI400_OFFSET 51 hex "Offset for CCI400 base" 52 depends on SYS_FSL_HAS_CCI400 53 default 0x180000 54 help 55 Offset for CCI400 base. 56 CCI400 base addr = CCSRBAR + CCI400_OFFSET 57 58config SYS_FSL_ERRATUM_A008850 59 bool 60 help 61 Workaround for DDR erratum A008850 62 63config SYS_FSL_ERRATUM_A008997 64 bool 65 help 66 Workaround for USB PHY erratum A008997 67 68config SYS_FSL_ERRATUM_A009007 69 bool 70 help 71 Workaround for USB PHY erratum A009007 72 73config SYS_FSL_ERRATUM_A009008 74 bool 75 help 76 Workaround for USB PHY erratum A009008 77 78config SYS_FSL_ERRATUM_A009798 79 bool 80 help 81 Workaround for USB PHY erratum A009798 82 83config SYS_FSL_ERRATUM_A010315 84 bool "Workaround for PCIe erratum A010315" 85 86config SYS_FSL_HAS_CCI400 87 bool 88 89config SYS_FSL_SRDS_1 90 bool 91 92config SYS_FSL_SRDS_2 93 bool 94 95config SYS_HAS_SERDES 96 bool 97 98config SYS_FSL_IFC_BANK_COUNT 99 int "Maximum banks of Integrated flash controller" 100 default 8 101 102config SYS_FSL_ERRATUM_A008407 103 bool 104 105endmenu 106