1SoC overview 2 3 1. LS1043A 4 2. LS1088A 5 3. LS2080A 6 4. LS1012A 7 5. LS1046A 8 6. LS2088A 9 7. LS2081A 10 8. LX2160A 11 9. LS1028A 12 10. LX2162A 13 14LS1043A 15--------- 16The LS1043A integrated multicore processor combines four ARM Cortex-A53 17processor cores with datapath acceleration optimized for L2/3 packet 18processing, single pass security offload and robust traffic management 19and quality of service. 20 21The LS1043A SoC includes the following function and features: 22 - Four 64-bit ARM Cortex-A53 CPUs 23 - 1 MB unified L2 Cache 24 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving 25 support 26 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 27 the following functions: 28 - Packet parsing, classification, and distribution (FMan) 29 - Queue management for scheduling, packet sequencing, and congestion 30 management (QMan) 31 - Hardware buffer management for buffer allocation and de-allocation (BMan) 32 - Cryptography acceleration (SEC) 33 - Ethernet interfaces by FMan 34 - Up to 1 x 10GBase-R supporting 10G interface 35 - Up to 1 x QSGMII 36 - Up to 4 x SGMII supporting 1000Mbps 37 - Up to 2 x SGMII supporting 2500Mbps 38 - Up to 2 x RGMII supporting 1000Mbps 39 - High-speed peripheral interfaces 40 - Three PCIe 2.0 controllers, one supporting x4 operation 41 - One serial ATA (SATA 3.0) controllers 42 - Additional peripheral interfaces 43 - Three high-speed USB 3.0 controllers with integrated PHY 44 - Enhanced secure digital host controller (eSDXC/eMMC) 45 - Quad Serial Peripheral Interface (QSPI) Controller 46 - Serial peripheral interface (SPI) controller 47 - Four I2C controllers 48 - Two DUARTs 49 - Integrated flash controller supporting NAND and NOR flash 50 - QorIQ platform's trust architecture 2.1 51 52LS1088A 53-------- 54The QorIQ LS1088A processor is built on the Layerscape 55architecture combining eight ARM A53 processor cores 56with advanced, high-performance datapath acceleration 57and networks, peripheral interfaces required for 58networking, wireless infrastructure, and general-purpose 59embedded applications. 60 61LS1088A is compliant with the Layerscape Chassis Generation 3. 62 63Features summary: 64 - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs 65 - Cores are in 2 cluster of 4-cores each 66 - 1MB L2 - Cache per cluster 67 - Cache coherent interconnect (CCI-400) 68 - 1 64-bit DDR4 SDRAM memory controller with ECC 69 - Data path acceleration architecture 2.0 (DPAA2) 70 - 4-Lane 10GHz SerDes comprising of WRIOP 71 - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART) 72 - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs 73 - QSPI, SPI, IFC2.0 supporting NAND, NOR flash 74 - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc 75 - 2 DUARTs 76 - 4 I2C, GPIO 77 - Thermal monitor unit(TMU) 78 - 4 Flextimers and 1 generic timer 79 - Support for hardware virtualization and partitioning enforcement 80 - QorIQ platform's trust architecture 3.0 81 - Service processor (SP) provides pre-boot initialization and secure-boot 82 capabilities 83 84LS2080A 85-------- 86The LS2080A integrated multicore processor combines eight ARM Cortex-A57 87processor cores with high-performance data path acceleration logic and network 88and peripheral bus interfaces required for networking, telecom/datacom, 89wireless infrastructure, and mil/aerospace applications. 90 91The LS2080A SoC includes the following function and features: 92 93 - Eight 64-bit ARM Cortex-A57 CPUs 94 - 1 MB platform cache with ECC 95 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 96 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 97 the AIOP 98 - Data path acceleration architecture (DPAA2) incorporating acceleration for 99 the following functions: 100 - Packet parsing, classification, and distribution (WRIOP) 101 - Queue and Hardware buffer management for scheduling, packet sequencing, and 102 congestion management, buffer allocation and de-allocation (QBMan) 103 - Cryptography acceleration (SEC) at up to 10 Gbps 104 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 105 - Decompression/compression acceleration (DCE) at up to 20 Gbps 106 - Accelerated I/O processing (AIOP) at up to 20 Gbps 107 - QDMA engine 108 - 16 SerDes lanes at up to 10.3125 GHz 109 - Ethernet interfaces 110 - Up to eight 10 Gbps Ethernet MACs 111 - Up to eight 1 / 2.5 Gbps Ethernet MACs 112 - High-speed peripheral interfaces 113 - Four PCIe 3.0 controllers, one supporting SR-IOV 114 - Additional peripheral interfaces 115 - Two serial ATA (SATA 3.0) controllers 116 - Two high-speed USB 3.0 controllers with integrated PHY 117 - Enhanced secure digital host controller (eSDXC/eMMC) 118 - Serial peripheral interface (SPI) controller 119 - Quad Serial Peripheral Interface (QSPI) Controller 120 - Four I2C controllers 121 - Two DUARTs 122 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 123 - Support for hardware virtualization and partitioning enforcement 124 - QorIQ platform's trust architecture 3.0 125 - Service processor (SP) provides pre-boot initialization and secure-boot 126 capabilities 127 128LS1012A 129-------- 130The LS1012A features an advanced 64-bit ARM v8 Cortex- 131A53 processor, with 32 KB of parity protected L1-I cache, 13232 KB of ECC protected L1-D cache, as well as 256 KB of 133ECC protected L2 cache. 134 135The LS1012A SoC includes the following function and features: 136 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: 137 - ARM v8 cryptography extensions 138 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports 139 16-/8-bit operation (no ECC support) 140 - ARM core-link CCI-400 cache coherent interconnect 141 - Packet Forwarding Engine (PFE) 142 - Cryptography acceleration (SEC) 143 - Ethernet interfaces supported by PFE: 144 - One Configurable x3 SerDes: 145 Two Serdes PLLs supported for usage by any SerDes data lane 146 Support for up to 6 GBaud operation 147 - High-speed peripheral interfaces: 148 - One PCI Express Gen2 controller, supporting x1 operation 149 - One serial ATA (SATA Gen 3.0) controller 150 - One USB 3.0/2.0 controller with integrated PHY 151 - One USB 2.0 controller with ULPI interface. . 152 - Additional peripheral interfaces: 153 - One quad serial peripheral interface (QuadSPI) controller 154 - One serial peripheral interface (SPI) controller 155 - Two enhanced secure digital host controllers 156 - Two I2C controllers 157 - One 16550 compliant DUART (two UART interfaces) 158 - Two general purpose IOs (GPIO) 159 - Two FlexTimers 160 - Five synchronous audio interfaces (SAI) 161 - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading 162 - Single-source clocking solution enabling generation of core, platform, 163 DDR, SerDes, and USB clocks from a single external crystal and internal 164 crystaloscillator 165 - Thermal monitor unit (TMU) with +/- 3C accuracy 166 - Two WatchDog timers 167 - ARM generic timer 168 - QorIQ platform's trust architecture 2.1 169 170LS1046A 171-------- 172The LS1046A integrated multicore processor combines four ARM Cortex-A72 173processor cores with datapath acceleration optimized for L2/3 packet 174processing, single pass security offload and robust traffic management 175and quality of service. 176 177The LS1046A SoC includes the following function and features: 178 - Four 64-bit ARM Cortex-A72 CPUs 179 - 2 MB unified L2 Cache 180 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving 181 support 182 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 183 the following functions: 184 - Packet parsing, classification, and distribution (FMan) 185 - Queue management for scheduling, packet sequencing, and congestion 186 management (QMan) 187 - Hardware buffer management for buffer allocation and de-allocation (BMan) 188 - Cryptography acceleration (SEC) 189 - Two Configurable x4 SerDes 190 - Two PLLs per four-lane SerDes 191 - Support for 10G operation 192 - Ethernet interfaces by FMan 193 - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) 194 - Up to 1 x QSGMII (MAC 5, 6, 10, 1) 195 - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) 196 - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) 197 - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) 198 - High-speed peripheral interfaces 199 - Three PCIe 3.0 controllers, one supporting x4 operation 200 - One serial ATA (SATA 3.0) controllers 201 - Additional peripheral interfaces 202 - Three high-speed USB 3.0 controllers with integrated PHY 203 - Enhanced secure digital host controller (eSDXC/eMMC) 204 - Quad Serial Peripheral Interface (QSPI) Controller 205 - Serial peripheral interface (SPI) controller 206 - Four I2C controllers 207 - Two DUARTs 208 - Integrated flash controller (IFC) supporting NAND and NOR flash 209 - QorIQ platform's trust architecture 2.1 210 211LS2088A 212-------- 213The LS2088A integrated multicore processor combines eight ARM Cortex-A72 214processor cores with high-performance data path acceleration logic and network 215and peripheral bus interfaces required for networking, telecom/datacom, 216wireless infrastructure, and mil/aerospace applications. 217 218The LS2088A SoC includes the following function and features: 219 220 - Eight 64-bit ARM Cortex-A72 CPUs 221 - 1 MB platform cache with ECC 222 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 223 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 224 the AIOP 225 - Data path acceleration architecture (DPAA2) incorporating acceleration for 226 the following functions: 227 - Packet parsing, classification, and distribution (WRIOP) 228 - Queue and Hardware buffer management for scheduling, packet sequencing, and 229 congestion management, buffer allocation and de-allocation (QBMan) 230 - Cryptography acceleration (SEC) at up to 10 Gbps 231 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 232 - Decompression/compression acceleration (DCE) at up to 20 Gbps 233 - Accelerated I/O processing (AIOP) at up to 20 Gbps 234 - QDMA engine 235 - 16 SerDes lanes at up to 10.3125 GHz 236 - Ethernet interfaces 237 - Up to eight 10 Gbps Ethernet MACs 238 - Up to eight 1 / 2.5 Gbps Ethernet MACs 239 - High-speed peripheral interfaces 240 - Four PCIe 3.0 controllers, one supporting SR-IOV 241 - Additional peripheral interfaces 242 - Two serial ATA (SATA 3.0) controllers 243 - Two high-speed USB 3.0 controllers with integrated PHY 244 - Enhanced secure digital host controller (eSDXC/eMMC) 245 - Serial peripheral interface (SPI) controller 246 - Quad Serial Peripheral Interface (QSPI) Controller 247 - Four I2C controllers 248 - Two DUARTs 249 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 250 - Support for hardware virtualization and partitioning enforcement 251 - QorIQ platform's trust architecture 3.0 252 - Service processor (SP) provides pre-boot initialization and secure-boot 253 capabilities 254 255LS2088A SoC has 3 more similar SoC personalities 2561)LS2048A, few difference w.r.t. LS2088A: 257 a) Four 64-bit ARM v8 Cortex-A72 CPUs 258 2592)LS2084A, few difference w.r.t. LS2088A: 260 a) No AIOP 261 b) No 32-bit DDR3 SDRAM memory 262 c) 5 * 1/10G + 5 *1G WRIOP 263 d) No L2 switch 264 2653)LS2044A, few difference w.r.t. LS2084A: 266 a) Four 64-bit ARM v8 Cortex-A72 CPUs 267 268LS2081A 269-------- 270LS2081A is 40-pin derivative of LS2084A. 271So feature-wise it is same as LS2084A. 272Refer to LS2084A(LS2088A) section above for details. 273 274It has one more similar SoC personality 2751)LS2041A, few difference w.r.t. LS2081A: 276 a) Four 64-bit ARM v8 Cortex-A72 CPUs 277 278LX2160A 279-------- 280The QorIQ LX2160A processor is built in the 16FFC process on 281the Layerscape architecture combining sixteen ARM A72 processor 282cores with advanced, high-performance datapath acceleration and 283network, peripheral interfaces required for networking, wireless 284infrastructure, storage, and general-purpose embedded applications. 285 286LX2160A is compliant with the Layerscape Chassis Generation 3.2. 287 288The LX2160A SoC includes the following function and features: 289 Sixteen 32-bit / 64-bit ARM v8 A72 CPUs 290 Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) 291 Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. 292 Data path acceleration architecture (DPAA2) 293 24 Serdes lanes at up to 25 GHz 294 Ethernet interfaces 295 Single WRIOP tile supporting 130Gbps using 18 MACs 296 Support for 10G-SXGMII (aka USXGMII). 297 Support for SGMII (and 1000Base-KX) 298 Support for 10GBase-R (and 10GBase-KR) 299 Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). 300 Support for XLAUI (and 40GBase-KR4) for 40G. 301 Support for two RGMII parallel interfaces. 302 Energy efficient Ethernet support (802.3az) 303 IEEE 1588 support. 304 High-speed peripheral interfaces 305 Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, 306 Four PCIe Gen 4.0 4-lane controllers. 307 Four serial ATA (SATA 3.0) controllers. 308 Two USB 3.0 controllers with integrated PHY 309 Two Enhanced secure digital host controllers 310 Two Controller Area Network (CAN) modules 311 Flexible Serial peripheral interface (FlexSPI) controller. 312 Three Serial peripheral interface (SPI) controllers. 313 Eight I2C Controllers. 314 Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. 315 General Purpose IO (GPIO) 316 Support for hardware virtualization and partitioning (ARM MMU-500) 317 Support for GIC (ARM GIC-500) 318 QorIQ platform Trust Architecture 3.0 319 One Secure WatchDog timer and one Non-Secure Watchdog timer. 320 ARM Generic Timer 321 Two Flextimers 322 Debug supporting run control, data acquisition, high-speed trace, 323 performance/event monitoring 324 Thermal Monitor Unit (TMU) with +/- 2C accuracy 325 Support for Voltage ID (VID) for yield improvement 326 327LX2160A SoC has 2 more similar SoC personalities 3281)LX2120A, few difference w.r.t. LX2160A: 329 a) Twelve 64-bit ARM v8 Cortex-A72 CPUs 330 3312)LX2080A, few difference w.r.t. LX2160A: 332 a) Eight 64-bit ARM v8 Cortex-A72 CPUs 333 334 335LS1028A 336-------- 337The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with 338a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and 339a TSNenabled 4-port switch. 340 341The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, 342combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and 343Octal/Quad SPI interfaces provide capabilities for a number of industrial and 344embedded applications. The device provides excellent integration with the 345new Time-Sensitive Networking standard, and enables a number of 346TSN applications. 347 348The LS1028A SoC includes the following function and features: 349 - Two 64-bit ARM v8 A72 CPUs 350 - Cache Coherent interconnect (CCI-400) 351 - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC 352 - eDP/Displayport interface 353 - Graphics processing unit 354 - One Configurable x4 SerDes 355 - Ethernet interfaces 356 - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one 357 ethernet MAC supporting 1G, 100M, 10M. 358 - Switched: TSN IP to support four 2.5/1G interfaces. 359 - None of the MACs support MACSEC 360 - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII 361 - Support for 10G-SXGMII and 10G-QXGMII. 362 - Energy efficient Ethernet support (802.3az) 363 - IEEE 1588 support 364 - High-speed peripheral interfaces 365 - Two PCIe 3.0 controllers, one supporting x4 operation 366 - One serial ATA (SATA 3.0) controller 367 - Additional peripheral interfaces 368 - Two high-speed USB 2.0/3.0 controllers with integrated PHY each 369 supporting host or device modes 370 - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) 371 - Two Serial peripheral interface (SPI) controllers 372 - Eight I2C controllers 373 - Two UART controllers 374 - Additional six Industrual UARTs (LPUART). 375 - One FlexSPI controller 376 - General Purpose IO (GPIO) 377 - Two CAN-FD interfaces 378 - Eight Flextimers with PWM I/O 379 - Support for hardware virtualization and partitioning enforcement 380 - Layerscape Trust Architecture 381 - Service Processor (SP) provides pre-boot initialization and secure-boot 382 capabilities 383 384LX2162A 385-------- 386The QorIQ LX2162A processor is built on the Layerscape architecture 387combining sixteen ARM A72 processor cores with advanced, high-performance 388datapath acceleration and network, peripheral interfaces required for 389networking, wireless infrastructure, storage, and general-purpose embedded 390applications. 391 392LX2162A is compliant with the Layerscape Chassis Generation 3.2. 393 394The LX2162A SoC includes the following function and features: 395 Sixteen 32-bit / 64-bit ARM v8 A72 CPUs 396 Cache Coherent Interconnect Fabric (CCN508) 397 One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC. 398 Data path acceleration architecture (DPAA2) 399 12 Serdes lanes at up to 25 GHz 400 Ethernet interfaces 401 Support for 10G-SXGMII (aka USXGMII). 402 Support for SGMII (and 1000Base-KX) 403 Support for 10GBase-R (and 10GBase-KR) 404 Support for CAUI2 (50G) and 25G-AUI(25G). 405 Support for XLAUI (and 40GBase-KR4) for 40G. 406 Support for two RGMII parallel interfaces. 407 Energy efficient Ethernet support (802.3az) 408 IEEE 1588 support. 409 High-speed peripheral interfaces 410 One PCIe Gen 3.0 8-lane controllers supporting SR-IOV, 411 Two PCIe Gen 3.0 4-lane controllers. 412 Four serial ATA (SATA 3.0) controllers. 413 One USB 3.0 controllers with integrated PHY 414 Two Enhanced secure digital host controllers 415 Two Controller Area Network (CAN) modules 416 Flexible Serial peripheral interface (FlexSPI) controller. 417 Three Serial peripheral interface (SPI) controllers. 418 Eight I2C Controllers. 419 Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. 420 General Purpose IO (GPIO) 421 Support for hardware virtualization and partitioning (ARM MMU-500) 422 Support for GIC (ARM GIC-500) 423 QorIQ platform Trust Architecture 3.0 424 One Secure WatchDog timer and one Non-Secure Watchdog timer. 425 ARM Generic Timer 426 Two Flextimers 427 Debug supporting run control, data acquisition, high-speed trace, 428 performance/event monitoring 429 Thermal Monitor Unit (TMU) with +/- 2C accuracy 430 Support for Voltage ID (VID) for yield improvement 431 432LX2162A SoC has 2 more similar SoC personalities 4331)LX2122A, few difference w.r.t. LX2162A: 434 a) Twelve 64-bit ARM v8 Cortex-A72 CPUs 435 4362)LX2082A, few difference w.r.t. LX2162A: 437 a) Eight 64-bit ARM v8 Cortex-A72 CPUs 438