1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 */ 5 6#include <common.h> 7#include <clock_legacy.h> 8#include <cpu_func.h> 9#include <debug_uart.h> 10#include <env.h> 11#include <hang.h> 12#include <image.h> 13#include <init.h> 14#include <log.h> 15#include <spl.h> 16#include <asm/cache.h> 17#include <asm/global_data.h> 18#include <asm/io.h> 19#include <fsl_ifc.h> 20#include <i2c.h> 21#include <fsl_csu.h> 22#include <asm/arch/fdt.h> 23#include <asm/arch/ppa.h> 24#include <asm/arch/soc.h> 25 26DECLARE_GLOBAL_DATA_PTR; 27 28u32 spl_boot_device(void) 29{ 30#ifdef CONFIG_SPL_MMC 31 return BOOT_DEVICE_MMC1; 32#endif 33#ifdef CONFIG_SPL_NAND_SUPPORT 34 return BOOT_DEVICE_NAND; 35#endif 36#ifdef CONFIG_QSPI_BOOT 37 return BOOT_DEVICE_NOR; 38#endif 39 return 0; 40} 41 42#ifdef CONFIG_SPL_BUILD 43 44void spl_board_init(void) 45{ 46#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) 47 /* 48 * In case of Secure Boot, the IBR configures the SMMU 49 * to allow only Secure transactions. 50 * SMMU must be reset in bypass mode. 51 * Set the ClientPD bit and Clear the USFCFG Bit 52 */ 53 u32 val; 54 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 55 out_le32(SMMU_SCR0, val); 56 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 57 out_le32(SMMU_NSCR0, val); 58#endif 59#ifdef CONFIG_LAYERSCAPE_NS_ACCESS 60 enable_layerscape_ns_access(); 61#endif 62#ifdef CONFIG_SPL_FSL_LS_PPA 63 ppa_init(); 64#endif 65} 66 67void board_init_f(ulong dummy) 68{ 69 int ret; 70 71 icache_enable(); 72 /* Clear global data */ 73 memset((void *)gd, 0, sizeof(gd_t)); 74 if (IS_ENABLED(CONFIG_DEBUG_UART)) 75 debug_uart_init(); 76 board_early_init_f(); 77 ret = spl_early_init(); 78 if (ret) { 79 debug("spl_early_init() failed: %d\n", ret); 80 hang(); 81 } 82 timer_init(); 83#ifdef CONFIG_ARCH_LS2080A 84 env_init(); 85#endif 86 get_clocks(); 87 88 preloader_console_init(); 89 spl_set_bd(); 90 91#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) 92#ifdef CONFIG_SPL_I2C 93 i2c_init_all(); 94#endif 95#endif 96#ifdef CONFIG_VID 97 init_func_vid(); 98#endif 99 dram_init(); 100#ifdef CONFIG_SPL_FSL_LS_PPA 101#ifndef CONFIG_SYS_MEM_RESERVE_SECURE 102#error Need secure RAM for PPA 103#endif 104 /* 105 * Secure memory location is determined in dram_init_banksize(). 106 * gd->ram_size is deducted by the size of secure ram. 107 */ 108 dram_init_banksize(); 109 110 /* 111 * After dram_init_bank_size(), we know U-Boot only uses the first 112 * memory bank regardless how big the memory is. 113 */ 114 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 115 116 /* 117 * If PPA is loaded, U-Boot will resume running at EL2. 118 * Cache and MMU will be enabled. Need a place for TLB. 119 * U-Boot will be relocated to the end of available memory 120 * in first bank. At this point, we cannot know how much 121 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK 122 * to avoid overlapping. As soon as the RAM version U-Boot sets 123 * up new MMU, this space is no longer needed. 124 */ 125 gd->ram_top -= SPL_TLB_SETBACK; 126 gd->arch.tlb_size = PGTABLE_SIZE; 127 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1); 128 gd->arch.tlb_allocated = gd->arch.tlb_addr; 129#endif /* CONFIG_SPL_FSL_LS_PPA */ 130#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT) 131 qspi_ahb_init(); 132#endif 133} 134 135#ifdef CONFIG_SPL_OS_BOOT 136/* 137 * Return 138 * 0 if booting into OS is selected 139 * 1 if booting into U-Boot is selected 140 */ 141int spl_start_uboot(void) 142{ 143 env_init(); 144 if (env_get_yesno("boot_os") != 0) 145 return 0; 146 147 return 1; 148} 149#endif /* CONFIG_SPL_OS_BOOT */ 150#endif /* CONFIG_SPL_BUILD */ 151