LXR uboot/arch/arm/include/asm/arch-sunxi/display2.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Sunxi platform display controller register and constant defines
   4 *
   5 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6 *
   7 * Based on out of tree Linux DRM driver defines:
   8 * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
   9 * Copyright (c) 2016 Allwinnertech Co., Ltd.
  10 */
  11
  12#ifndef _SUNXI_DISPLAY2_H
  13#define _SUNXI_DISPLAY2_H
  14
  15/* internal clock settings */
  16struct de_clk {
  17        u32 gate_cfg;
  18        u32 bus_cfg;
  19        u32 rst_cfg;
  20        u32 div_cfg;
  21        u32 sel_cfg;
  22};
  23
  24/* global control */
  25struct de_glb {
  26        u32 ctl;
  27        u32 status;
  28        u32 dbuff;
  29        u32 size;
  30};
  31
  32/* alpha blending */
  33struct de_bld {
  34        u32 fcolor_ctl;
  35        struct {
  36                u32 fcolor;
  37                u32 insize;
  38                u32 offset;
  39                u32 dum;
  40        } attr[4];
  41        u32 dum0[15];
  42        u32 route;
  43        u32 premultiply;
  44        u32 bkcolor;
  45        u32 output_size;
  46        u32 bld_mode[4];
  47        u32 dum1[4];
  48        u32 ck_ctl;
  49        u32 ck_cfg;
  50        u32 dum2[2];
  51        u32 ck_max[4];
  52        u32 dum3[4];
  53        u32 ck_min[4];
  54        u32 dum4[3];
  55        u32 out_ctl;
  56};
  57
  58/* VI channel */
  59struct de_vi {
  60        struct {
  61                u32 attr;
  62                u32 size;
  63                u32 coord;
  64                u32 pitch[3];
  65                u32 top_laddr[3];
  66                u32 bot_laddr[3];
  67        } cfg[4];
  68        u32 fcolor[4];
  69        u32 top_haddr[3];
  70        u32 bot_haddr[3];
  71        u32 ovl_size[2];
  72        u32 hori[2];
  73        u32 vert[2];
  74};
  75
  76struct de_ui {
  77        struct {
  78                u32 attr;
  79                u32 size;
  80                u32 coord;
  81                u32 pitch;
  82                u32 top_laddr;
  83                u32 bot_laddr;
  84                u32 fcolor;
  85                u32 dum;
  86        } cfg[4];
  87        u32 top_haddr;
  88        u32 bot_haddr;
  89        u32 ovl_size;
  90};
  91
  92struct de_csc {
  93        u32 csc_ctl;
  94        u8 res[0xc];
  95        u32 coef11;
  96        u32 coef12;
  97        u32 coef13;
  98        u32 coef14;
  99        u32 coef21;
 100        u32 coef22;
 101        u32 coef23;
 102        u32 coef24;
 103        u32 coef31;
 104        u32 coef32;
 105        u32 coef33;
 106        u32 coef34;
 107};
 108
 109/*
 110 * DE register constants.
 111 */
 112#define SUNXI_DE2_MUX0_BASE                     (SUNXI_DE2_BASE + 0x100000)
 113#define SUNXI_DE2_MUX1_BASE                     (SUNXI_DE2_BASE + 0x200000)
 114
 115#define SUNXI_DE2_MUX_GLB_REGS                  0x00000
 116#define SUNXI_DE2_MUX_BLD_REGS                  0x01000
 117#define SUNXI_DE2_MUX_CHAN_REGS                 0x02000
 118#define SUNXI_DE2_MUX_CHAN_SZ                   0x1000
 119#define SUNXI_DE2_MUX_VSU_REGS                  0x20000
 120#define SUNXI_DE2_MUX_GSU1_REGS                 0x30000
 121#define SUNXI_DE2_MUX_GSU2_REGS                 0x40000
 122#define SUNXI_DE2_MUX_GSU3_REGS                 0x50000
 123#define SUNXI_DE2_MUX_FCE_REGS                  0xa0000
 124#define SUNXI_DE2_MUX_BWS_REGS                  0xa2000
 125#define SUNXI_DE2_MUX_LTI_REGS                  0xa4000
 126#define SUNXI_DE2_MUX_PEAK_REGS                 0xa6000
 127#define SUNXI_DE2_MUX_ASE_REGS                  0xa8000
 128#define SUNXI_DE2_MUX_FCC_REGS                  0xaa000
 129#define SUNXI_DE2_MUX_DCSC_REGS                 0xb0000
 130
 131#define SUNXI_DE2_FORMAT_XRGB_8888              4
 132#define SUNXI_DE2_FORMAT_RGB_565                10
 133
 134#define SUNXI_DE2_MUX_GLB_CTL_EN                (1 << 0)
 135#define SUNXI_DE2_UI_CFG_ATTR_EN                (1 << 0)
 136#define SUNXI_DE2_UI_CFG_ATTR_FMT(f)            ((f & 0xf) << 8)
 137
 138#define SUNXI_DE2_WH(w, h)                      (((h - 1) << 16) | (w - 1))
 139
 140#endif /* _SUNXI_DISPLAY2_H */
 141