LXR uboot/arch/arm/include/asm/arch-tegra/pinmux.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2010-2014
   4 * NVIDIA Corporation <www.nvidia.com>
   5 */
   6
   7#ifndef _TEGRA_PINMUX_H_
   8#define _TEGRA_PINMUX_H_
   9
  10#include <linux/types.h>
  11
  12#include <asm/arch/tegra.h>
  13
  14/* The pullup/pulldown state of a pin group */
  15enum pmux_pull {
  16        PMUX_PULL_NORMAL = 0,
  17        PMUX_PULL_DOWN,
  18        PMUX_PULL_UP,
  19};
  20
  21/* Defines whether a pin group is tristated or in normal operation */
  22enum pmux_tristate {
  23        PMUX_TRI_NORMAL = 0,
  24        PMUX_TRI_TRISTATE = 1,
  25};
  26
  27#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
  28enum pmux_pin_io {
  29        PMUX_PIN_OUTPUT = 0,
  30        PMUX_PIN_INPUT = 1,
  31        PMUX_PIN_NONE,
  32};
  33#endif
  34
  35#ifdef TEGRA_PMX_PINS_HAVE_LOCK
  36enum pmux_pin_lock {
  37        PMUX_PIN_LOCK_DEFAULT = 0,
  38        PMUX_PIN_LOCK_DISABLE,
  39        PMUX_PIN_LOCK_ENABLE,
  40};
  41#endif
  42
  43#ifdef TEGRA_PMX_PINS_HAVE_OD
  44enum pmux_pin_od {
  45        PMUX_PIN_OD_DEFAULT = 0,
  46        PMUX_PIN_OD_DISABLE,
  47        PMUX_PIN_OD_ENABLE,
  48};
  49#endif
  50
  51#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
  52enum pmux_pin_ioreset {
  53        PMUX_PIN_IO_RESET_DEFAULT = 0,
  54        PMUX_PIN_IO_RESET_DISABLE,
  55        PMUX_PIN_IO_RESET_ENABLE,
  56};
  57#endif
  58
  59#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
  60enum pmux_pin_rcv_sel {
  61        PMUX_PIN_RCV_SEL_DEFAULT = 0,
  62        PMUX_PIN_RCV_SEL_NORMAL,
  63        PMUX_PIN_RCV_SEL_HIGH,
  64};
  65#endif
  66
  67#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  68enum pmux_pin_e_io_hv {
  69        PMUX_PIN_E_IO_HV_DEFAULT = 0,
  70        PMUX_PIN_E_IO_HV_NORMAL,
  71        PMUX_PIN_E_IO_HV_HIGH,
  72};
  73#endif
  74
  75#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
  76/* Defines a pin group cfg's low-power mode select */
  77enum pmux_lpmd {
  78        PMUX_LPMD_X8 = 0,
  79        PMUX_LPMD_X4,
  80        PMUX_LPMD_X2,
  81        PMUX_LPMD_X,
  82        PMUX_LPMD_NONE = -1,
  83};
  84#endif
  85
  86#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
  87/* Defines whether a pin group cfg's schmidt is enabled or not */
  88enum pmux_schmt {
  89        PMUX_SCHMT_DISABLE = 0,
  90        PMUX_SCHMT_ENABLE = 1,
  91        PMUX_SCHMT_NONE = -1,
  92};
  93#endif
  94
  95#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
  96/* Defines whether a pin group cfg's high-speed mode is enabled or not */
  97enum pmux_hsm {
  98        PMUX_HSM_DISABLE = 0,
  99        PMUX_HSM_ENABLE = 1,
 100        PMUX_HSM_NONE = -1,
 101};
 102#endif
 103
 104/*
 105 * This defines the configuration for a pin, including the function assigned,
 106 * pull up/down settings and tristate settings. Having set up one of these
 107 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
 108 * available is pinmux_config_table() to configure a list of pins.
 109 */
 110struct pmux_pingrp_config {
 111        u32 pingrp:16;          /* pin group PMUX_PINGRP_...        */
 112        u32 func:8;             /* function to assign PMUX_FUNC_... */
 113        u32 pull:2;             /* pull up/down/normal PMUX_PULL_...*/
 114        u32 tristate:2;         /* tristate or normal PMUX_TRI_...  */
 115#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 116        u32 io:2;               /* input or output PMUX_PIN_...     */
 117#endif
 118#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 119        u32 lock:2;             /* lock enable/disable PMUX_PIN...  */
 120#endif
 121#ifdef TEGRA_PMX_PINS_HAVE_OD
 122        u32 od:2;               /* open-drain or push-pull driver   */
 123#endif
 124#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 125        u32 ioreset:2;          /* input/output reset PMUX_PIN...   */
 126#endif
 127#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 128        u32 rcv_sel:2;          /* select between High and Normal  */
 129                                /* VIL/VIH receivers */
 130#endif
 131#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
 132        u32 e_io_hv:2;          /* select 3.3v tolerant receivers */
 133#endif
 134#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
 135        u32 schmt:2;            /* schmitt enable            */
 136#endif
 137#ifdef TEGRA_PMX_PINS_HAVE_HSM
 138        u32 hsm:2;              /* high-speed mode enable    */
 139#endif
 140};
 141
 142#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 143/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
 144void pinmux_set_tristate_input_clamping(void);
 145void pinmux_clear_tristate_input_clamping(void);
 146#endif
 147
 148/* Set the mux function for a pin group */
 149void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 150
 151/* Set the pull up/down feature for a pin group */
 152void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
 153
 154/* Set a pin group to tristate */
 155void pinmux_tristate_enable(enum pmux_pingrp pin);
 156
 157/* Set a pin group to normal (non tristate) */
 158void pinmux_tristate_disable(enum pmux_pingrp pin);
 159
 160#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 161/* Set a pin group as input or output */
 162void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 163#endif
 164
 165/**
 166 * Configure a list of pin groups
 167 *
 168 * @param config        List of config items
 169 * @param len           Number of config items in list
 170 */
 171void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 172                                int len);
 173
 174struct pmux_pingrp_desc {
 175        u8 funcs[4];
 176#if defined(CONFIG_TEGRA20)
 177        u8 ctl_id;
 178        u8 pull_id;
 179#endif /* CONFIG_TEGRA20 */
 180};
 181
 182extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
 183
 184#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 185
 186#define PMUX_SLWF_MIN   0
 187#define PMUX_SLWF_MAX   3
 188#define PMUX_SLWF_NONE  -1
 189
 190#define PMUX_SLWR_MIN   0
 191#define PMUX_SLWR_MAX   3
 192#define PMUX_SLWR_NONE  -1
 193
 194#define PMUX_DRVUP_MIN  0
 195#define PMUX_DRVUP_MAX  127
 196#define PMUX_DRVUP_NONE -1
 197
 198#define PMUX_DRVDN_MIN  0
 199#define PMUX_DRVDN_MAX  127
 200#define PMUX_DRVDN_NONE -1
 201
 202/*
 203 * This defines the configuration for a pin group's pad control config
 204 */
 205struct pmux_drvgrp_config {
 206        u32 drvgrp:16;  /* pin group PMUX_DRVGRP_x   */
 207        u32 slwf:3;             /* falling edge slew         */
 208        u32 slwr:3;             /* rising edge slew          */
 209        u32 drvup:8;            /* pull-up drive strength    */
 210        u32 drvdn:8;            /* pull-down drive strength  */
 211#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 212        u32 lpmd:3;             /* low-power mode selection  */
 213#endif
 214#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 215        u32 schmt:2;            /* schmidt enable            */
 216#endif
 217#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 218        u32 hsm:2;              /* high-speed mode enable    */
 219#endif
 220};
 221
 222/**
 223 * Set the GP pad configs
 224 *
 225 * @param config        List of config items
 226 * @param len           Number of config items in list
 227 */
 228void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 229                                int len);
 230
 231#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 232
 233#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
 234struct pmux_mipipadctrlgrp_config {
 235        u32 grp:16;     /* pin group PMUX_MIPIPADCTRLGRP_x   */
 236        u32 func:8;     /* function to assign PMUX_FUNC_... */
 237};
 238
 239void pinmux_config_mipipadctrlgrp_table(
 240        const struct pmux_mipipadctrlgrp_config *config, int len);
 241
 242struct pmux_mipipadctrlgrp_desc {
 243        u8 funcs[2];
 244};
 245
 246extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
 247#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
 248
 249#endif /* _TEGRA_PINMUX_H_ */
 250