1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2009 SAMSUNG Electronics 4 * Minkyu Kang <mk7.kang@samsung.com> 5 * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation 6 */ 7 8#ifndef __TEGRA_MMC_H_ 9#define __TEGRA_MMC_H_ 10 11#include <clk.h> 12#include <reset.h> 13#include <fdtdec.h> 14#include <asm/gpio.h> 15 16/* for mmc_config definition */ 17#include <mmc.h> 18 19#ifndef __ASSEMBLY__ 20struct tegra_mmc { 21 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ 22 unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ 23 unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ 24 unsigned int argument; /* _ARGUMENT_0 */ 25 unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ 26 unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ 27 unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ 28 unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ 29 unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ 30 unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ 31 unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ 32 unsigned int prnsts; /* _PRESENT_STATE_0 */ 33 unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ 34 unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ 35 unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ 36 unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ 37 unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ 38 unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ 39 unsigned char swrst; /* _SW_RESET_ 31:24 */ 40 unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ 41 unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ 42 unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ 43 unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ 44 unsigned char res1[2]; /* _RESERVED 31:16 */ 45 unsigned int capareg; /* _CAPABILITIES_0 */ 46 unsigned char res2[4]; /* RESERVED, offset 44h-47h */ 47 unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ 48 unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ 49 unsigned short setacmd12err; /* offset 50h */ 50 unsigned short setinterr; /* offset 52h */ 51 unsigned char admaerr; /* offset 54h */ 52 unsigned char res4[3]; /* RESERVED, offset 55h-57h */ 53 unsigned long admaaddr; /* offset 58h-5Fh */ 54 unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ 55 unsigned short slotintstatus; /* offset FCh */ 56 unsigned short hcver; /* HOST Version */ 57 unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ 58 unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ 59 unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ 60 unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ 61 unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ 62 unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ 63 unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ 64 unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ 65 unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ 66 unsigned int res6[47]; /* 0x124 ~ 0x1DC */ 67 unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ 68 unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ 69 unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ 70 unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ 71}; 72 73#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) 74#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) 75#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) 76#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) 77 78#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) 79#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) 80#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) 81#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) 82 83#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) 84#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) 85#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) 86#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) 87#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) 88 89#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) 90#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) 91#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) 92#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) 93#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) 94 95#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) 96#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) 97#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) 98 99#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) 100#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) 101 102#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) 103#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) 104#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) 105 106#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 107#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) 108 109#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) 110 111#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) 112#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) 113#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) 114 115#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) 116#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) 117#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) 118#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) 119#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) 120 121#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) 122#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) 123#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) 124#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) 125#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) 126 127#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) 128 129/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ 130#define MEMCOMP_PADCTRL_VREF 7 131#define AUTO_CAL_ENABLE (1 << 29) 132#define AUTO_CAL_ACTIVE (1 << 31) 133#define AUTO_CAL_START (1 << 31) 134#if defined(CONFIG_TEGRA210) 135#define AUTO_CAL_PD_OFFSET (0x7D << 8) 136#define AUTO_CAL_PU_OFFSET (0 << 0) 137#define IO_TRIM_BYPASS_MASK (1 << 2) 138#define TRIM_VAL_SHIFT 24 139#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) 140#define TAP_VAL_SHIFT 16 141#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) 142#else 143#define AUTO_CAL_PD_OFFSET (0x70 << 8) 144#define AUTO_CAL_PU_OFFSET (0x62 << 0) 145#endif 146 147#endif /* __ASSEMBLY__ */ 148#endif /* __TEGRA_MMC_H_ */ 149