1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * Copyright (c) 2013 NVIDIA Corporation 5 */ 6 7#ifndef _TEGRA_USB_H_ 8#define _TEGRA_USB_H_ 9 10/* USB Controller (USBx_CONTROLLER_) regs */ 11struct usb_ctlr { 12 /* 0x000 */ 13 uint id; 14 uint reserved0; 15 uint host; 16 uint device; 17 18 /* 0x010 */ 19 uint txbuf; 20 uint rxbuf; 21 uint reserved1[2]; 22 23 /* 0x020 */ 24 uint reserved2[56]; 25 26 /* 0x100 */ 27 u16 cap_length; 28 u16 hci_version; 29 uint hcs_params; 30 uint hcc_params; 31 uint reserved3[5]; 32 33 /* 0x120 */ 34 uint dci_version; 35 uint dcc_params; 36 uint reserved4[2]; 37 38#ifdef CONFIG_TEGRA20 39 /* 0x130 */ 40 uint reserved4_2[4]; 41 42 /* 0x140 */ 43 uint usb_cmd; 44 uint usb_sts; 45 uint usb_intr; 46 uint frindex; 47 48 /* 0x150 */ 49 uint reserved5; 50 uint periodic_list_base; 51 uint async_list_addr; 52 uint async_tt_sts; 53 54 /* 0x160 */ 55 uint burst_size; 56 uint tx_fill_tuning; 57 uint reserved6; /* is this port_sc1 on some controllers? */ 58 uint icusb_ctrl; 59 60 /* 0x170 */ 61 uint ulpi_viewport; 62 uint reserved7; 63 uint endpt_nak; 64 uint endpt_nak_enable; 65 66 /* 0x180 */ 67 uint reserved; 68 uint port_sc1; 69 uint reserved8[6]; 70 71 /* 0x1a0 */ 72 uint reserved9; 73 uint otgsc; 74 uint usb_mode; 75 uint endpt_setup_stat; 76 77 /* 0x1b0 */ 78 uint reserved10[20]; 79 80 /* 0x200 */ 81 uint reserved11[0x80]; 82#else 83 /* 0x130 */ 84 uint usb_cmd; 85 uint usb_sts; 86 uint usb_intr; 87 uint frindex; 88 89 /* 0x140 */ 90 uint reserved5; 91 uint periodic_list_base; 92 uint async_list_addr; 93 uint reserved5_1; 94 95 /* 0x150 */ 96 uint burst_size; 97 uint tx_fill_tuning; 98 uint reserved6; 99 uint icusb_ctrl; 100 101 /* 0x160 */ 102 uint ulpi_viewport; 103 uint reserved7[3]; 104 105 /* 0x170 */ 106 uint reserved; 107 uint port_sc1; 108 uint reserved8[6]; 109 110 /* 0x190 */ 111 uint reserved9[8]; 112 113 /* 0x1b0 */ 114 uint reserved10; 115 uint hostpc1_devlc; 116 uint reserved10_1[2]; 117 118 /* 0x1c0 */ 119 uint reserved10_2[4]; 120 121 /* 0x1d0 */ 122 uint reserved10_3[4]; 123 124 /* 0x1e0 */ 125 uint reserved10_4[4]; 126 127 /* 0x1f0 */ 128 uint reserved10_5; 129 uint otgsc; 130 uint usb_mode; 131 uint reserved10_6; 132 133 /* 0x200 */ 134 uint endpt_nak; 135 uint endpt_nak_enable; 136 uint endpt_setup_stat; 137 uint reserved11_1[0x7D]; 138#endif 139 140 /* 0x400 */ 141 uint susp_ctrl; 142 uint phy_vbus_sensors; 143 uint phy_vbus_wakeup_id; 144 uint phy_alt_vbus_sys; 145 146#ifdef CONFIG_TEGRA20 147 /* 0x410 */ 148 uint usb1_legacy_ctrl; 149 uint reserved12[4]; 150 151 /* 0x424 */ 152 uint ulpi_timing_ctrl_0; 153 uint ulpi_timing_ctrl_1; 154 uint reserved13[53]; 155#else 156 157 /* 0x410 */ 158 uint usb1_legacy_ctrl; 159 uint reserved12[3]; 160 161 /* 0x420 */ 162 uint reserved13[56]; 163#endif 164 165 /* 0x500 */ 166 uint reserved14[64 * 3]; 167 168 /* 0x800 */ 169 uint utmip_pll_cfg0; 170 uint utmip_pll_cfg1; 171 uint utmip_xcvr_cfg0; 172 uint utmip_bias_cfg0; 173 174 /* 0x810 */ 175 uint utmip_hsrx_cfg0; 176 uint utmip_hsrx_cfg1; 177 uint utmip_fslsrx_cfg0; 178 uint utmip_fslsrx_cfg1; 179 180 /* 0x820 */ 181 uint utmip_tx_cfg0; 182 uint utmip_misc_cfg0; 183 uint utmip_misc_cfg1; 184 uint utmip_debounce_cfg0; 185 186 /* 0x830 */ 187 uint utmip_bat_chrg_cfg0; 188 uint utmip_spare_cfg0; 189 uint utmip_xcvr_cfg1; 190 uint utmip_bias_cfg1; 191}; 192 193/* USB1_LEGACY_CTRL */ 194#define USB1_NO_LEGACY_MODE 1 195 196#define VBUS_SENSE_CTL_SHIFT 1 197#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) 198#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 199#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 200#define VBUS_SENSE_CTL_AB_SESS_VLD 2 201#define VBUS_SENSE_CTL_A_SESS_VLD 3 202 203/* USBx_IF_USB_SUSP_CTRL_0 */ 204#define UTMIP_PHY_ENB (1 << 12) 205#define UTMIP_RESET (1 << 11) 206#define USB_PHY_CLK_VALID (1 << 7) 207#define USB_SUSP_CLR (1 << 5) 208 209#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) 210/* USB2_IF_USB_SUSP_CTRL_0 */ 211#define ULPI_PHY_ENB (1 << 13) 212 213/* USB2_IF_ULPI_TIMING_CTRL_0 */ 214#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 215#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 216 217/* USB2_IF_ULPI_TIMING_CTRL_1 */ 218#define ULPI_DATA_TRIMMER_LOAD (1 << 0) 219#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 220#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 221#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 222#define ULPI_DIR_TRIMMER_LOAD (1 << 24) 223#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 224#endif 225 226/* USBx_UTMIP_MISC_CFG0 */ 227#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 228 229/* USBx_UTMIP_MISC_CFG1 */ 230#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) 231 232/* 233 * Tegra 3 and later: Moved to Clock and Reset register space, see 234 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 235 */ 236#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 237#define UTMIP_PLLU_STABLE_COUNT_MASK \ 238 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) 239/* 240 * Tegra 3 and later: Moved to Clock and Reset register space, see 241 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 242 */ 243#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 244#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ 245 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) 246 247/* USBx_UTMIP_PLL_CFG1_0 */ 248/* Tegra 3 and later: Moved to Clock and Reset register space */ 249#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 250#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ 251 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) 252#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 253#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff 254 255/* USBx_UTMIP_BIAS_CFG0_0 */ 256#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) 257#define UTMIP_OTGPD (1 << 11) 258#define UTMIP_BIASPD (1 << 10) 259#define UTMIP_HSDISCON_LEVEL_SHIFT 2 260#define UTMIP_HSDISCON_LEVEL_MASK \ 261 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) 262#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 263#define UTMIP_HSSQUELCH_LEVEL_MASK \ 264 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) 265 266/* USBx_UTMIP_BIAS_CFG1_0 */ 267#define UTMIP_FORCE_PDTRK_POWERDOWN 1 268#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8 269#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \ 270 (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT) 271#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 272#define UTMIP_BIAS_PDTRK_COUNT_MASK \ 273 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) 274 275/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ 276#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 277#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff 278 279/* USBx_UTMIP_TX_CFG0_0 */ 280#define UTMIP_FS_PREAMBLE_J (1 << 19) 281 282/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ 283#define UTMIP_PD_CHRG 1 284 285/* USBx_UTMIP_SPARE_CFG0_0 */ 286#define FUSE_SETUP_SEL (1 << 3) 287 288/* USBx_UTMIP_HSRX_CFG0_0 */ 289#define UTMIP_IDLE_WAIT_SHIFT 15 290#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) 291#define UTMIP_ELASTIC_LIMIT_SHIFT 10 292#define UTMIP_ELASTIC_LIMIT_MASK \ 293 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) 294 295/* USBx_UTMIP_HSRX_CFG1_0 */ 296#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 297#define UTMIP_HS_SYNC_START_DLY_MASK \ 298 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) 299 300/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ 301#define IC_ENB1 (1 << 3) 302 303#ifdef CONFIG_TEGRA20 304/* PORTSC1, USB1 */ 305#define PTS1_SHIFT 31 306#define PTS1_MASK (1 << PTS1_SHIFT) 307#define STS1 (1 << 30) 308 309/* PORTSC, USB2, USB3 */ 310#define PTS_SHIFT 30 311#define PTS_MASK (3U << PTS_SHIFT) 312#define STS (1 << 29) 313#else 314/* USB2D_HOSTPC1_DEVLC_0 */ 315#define PTS_SHIFT 29 316#define PTS_MASK (0x7U << PTS_SHIFT) 317#define STS (1 << 28) 318#endif 319 320#define PTS_UTMI 0 321#define PTS_RESERVED 1 322#define PTS_ULPI 2 323#define PTS_ICUSB_SER 3 324#define PTS_HSIC 4 325 326/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ 327#define WKOC (1 << 22) 328#define WKDS (1 << 21) 329#define WKCN (1 << 20) 330 331/* USBx_UTMIP_XCVR_CFG0_0 */ 332#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 333#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 334#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 335#define UTMIP_XCVR_LSBIAS_SE (1 << 21) 336#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 337#define UTMIP_XCVR_HSSLEW_MSB_MASK \ 338 (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) 339#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 340#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) 341#define UTMIP_XCVR_SETUP_SHIFT 0 342#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) 343 344/* USBx_UTMIP_XCVR_CFG1_0 */ 345#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 346#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ 347 (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) 348#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 349#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 350#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 351 352/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ 353#define VBUS_VLD_STS (1 << 26) 354#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) 355#define VBUS_B_SESS_VLD_SW_EN (1 << 11) 356 357/* Setup USB on the board */ 358int usb_process_devicetree(const void *blob); 359 360#endif /* _TEGRA_USB_H_ */ 361