LXR uboot/arch/arm/include/asm/pl310.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2010
   4 * Texas Instruments, <www.ti.com>
   5 * Aneesh V <aneesh@ti.com>
   6 */
   7#ifndef _PL310_H_
   8#define _PL310_H_
   9
  10#include <linux/types.h>
  11
  12/* Register bit fields */
  13#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK       (1 << 16)
  14#define L2X0_DYNAMIC_CLK_GATING_EN              (1 << 1)
  15#define L2X0_STNDBY_MODE_EN                     (1 << 0)
  16#define L2X0_CTRL_EN                            1
  17
  18#define L310_SHARED_ATT_OVERRIDE_ENABLE         (1 << 22)
  19#define L310_AUX_CTRL_DATA_PREFETCH_MASK        (1 << 28)
  20#define L310_AUX_CTRL_INST_PREFETCH_MASK        (1 << 29)
  21#define L310_LATENCY_CTRL_SETUP(n)              ((n) << 0)
  22#define L310_LATENCY_CTRL_RD(n)                 ((n) << 4)
  23#define L310_LATENCY_CTRL_WR(n)                 ((n) << 8)
  24
  25#define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
  26#define L2X0_CACHE_ID_PART_L310     (3 << 6)
  27#define L2X0_CACHE_ID_RTL_MASK          0x3f
  28#define L2X0_CACHE_ID_RTL_R3P2          0x8
  29
  30struct pl310_regs {
  31        u32 pl310_cache_id;
  32        u32 pl310_cache_type;
  33        u32 pad1[62];
  34        u32 pl310_ctrl;
  35        u32 pl310_aux_ctrl;
  36        u32 pl310_tag_latency_ctrl;
  37        u32 pl310_data_latency_ctrl;
  38        u32 pad2[60];
  39        u32 pl310_event_cnt_ctrl;
  40        u32 pl310_event_cnt1_cfg;
  41        u32 pl310_event_cnt0_cfg;
  42        u32 pl310_event_cnt1_val;
  43        u32 pl310_event_cnt0_val;
  44        u32 pl310_intr_mask;
  45        u32 pl310_masked_intr_stat;
  46        u32 pl310_raw_intr_stat;
  47        u32 pl310_intr_clear;
  48        u32 pad3[323];
  49        u32 pl310_cache_sync;
  50        u32 pad4[15];
  51        u32 pl310_inv_line_pa;
  52        u32 pad5[2];
  53        u32 pl310_inv_way;
  54        u32 pad6[12];
  55        u32 pl310_clean_line_pa;
  56        u32 pad7[1];
  57        u32 pl310_clean_line_idx;
  58        u32 pl310_clean_way;
  59        u32 pad8[12];
  60        u32 pl310_clean_inv_line_pa;
  61        u32 pad9[1];
  62        u32 pl310_clean_inv_line_idx;
  63        u32 pl310_clean_inv_way;
  64        u32 pad10[64];
  65        u32 pl310_lockdown_dbase;
  66        u32 pl310_lockdown_ibase;
  67        u32 pad11[190];
  68        u32 pl310_addr_filter_start;
  69        u32 pl310_addr_filter_end;
  70        u32 pad12[190];
  71        u32 pl310_test_operation;
  72        u32 pad13[3];
  73        u32 pl310_line_data;
  74        u32 pad14[7];
  75        u32 pl310_line_tag;
  76        u32 pad15[3];
  77        u32 pl310_debug_ctrl;
  78        u32 pad16[7];
  79        u32 pl310_prefetch_ctrl;
  80        u32 pad17[7];
  81        u32 pl310_power_ctrl;
  82};
  83
  84void pl310_inval_all(void);
  85void pl310_clean_inval_all(void);
  86void pl310_inval_range(u32 start, u32 end);
  87void pl310_clean_inval_range(u32 start, u32 end);
  88
  89#endif
  90