LXR uboot/arch/arm/mach-at91/arm926ejs/timer.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 */
   7
   8#include <common.h>
   9#include <init.h>
  10#include <time.h>
  11#include <asm/global_data.h>
  12#include <asm/io.h>
  13#include <asm/arch/hardware.h>
  14#include <asm/arch/at91_pit.h>
  15#include <asm/arch/clk.h>
  16#include <div64.h>
  17
  18#if !defined(CONFIG_AT91FAMILY)
  19# error You need to define CONFIG_AT91FAMILY in your board config!
  20#endif
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24/*
  25 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  26 * setting the 20 bit counter period to its maximum (0xfffff).
  27 * (See the relevant data sheets to understand that this really works)
  28 *
  29 * We do also mimic the typical powerpc way of incrementing
  30 * two 32 bit registers called tbl and tbu.
  31 *
  32 * Those registers increment at 1/16 the main clock rate.
  33 */
  34
  35#define TIMER_LOAD_VAL  0xfffff
  36
  37/*
  38 * Use the PITC in full 32 bit incrementing mode
  39 */
  40int timer_init(void)
  41{
  42        at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  43
  44        at91_periph_clk_enable(ATMEL_ID_SYS);
  45
  46        /* Enable PITC */
  47        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  48
  49        gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  50
  51        return 0;
  52}
  53
  54/*
  55 * Return the number of timer ticks per second.
  56 */
  57ulong get_tbclk(void)
  58{
  59        return gd->arch.timer_rate_hz;
  60}
  61