LXR uboot/arch/arm/mach-at91/armv7/timer.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 *
   7 * (C) Copyright 2013
   8 * Bo Shen <voice.shen@atmel.com>
   9 */
  10
  11#include <common.h>
  12#include <init.h>
  13#include <time.h>
  14#include <asm/global_data.h>
  15#include <asm/io.h>
  16#include <asm/arch/hardware.h>
  17#include <asm/arch/at91_pit.h>
  18#include <asm/arch/clk.h>
  19#include <div64.h>
  20
  21#if !defined(CONFIG_AT91FAMILY)
  22# error You need to define CONFIG_AT91FAMILY in your board config!
  23#endif
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27/*
  28 * We're using the SAMA5D3x PITC in 32 bit mode, by
  29 * setting the 20 bit counter period to its maximum (0xfffff).
  30 * (See the relevant data sheets to understand that this really works)
  31 *
  32 * We do also mimic the typical powerpc way of incrementing
  33 * two 32 bit registers called tbl and tbu.
  34 *
  35 * Those registers increment at 1/16 the main clock rate.
  36 */
  37
  38#define TIMER_LOAD_VAL  0xfffff
  39
  40/*
  41 * Use the PITC in full 32 bit incrementing mode
  42 */
  43int timer_init(void)
  44{
  45        at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
  46
  47        /* Enable PITC Clock */
  48        at91_periph_clk_enable(ATMEL_ID_PIT);
  49
  50        /* Enable PITC */
  51        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  52
  53        gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
  54
  55        return 0;
  56}
  57
  58/*
  59 * Return the number of timer ticks per second.
  60 */
  61ulong get_tbclk(void)
  62{
  63        return gd->arch.timer_rate_hz;
  64}
  65