1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] 4 * 5 * (C) 2006 Andrew Victor 6 * (C) Copyright 2010 7 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 8 * 9 * Definitions for the SoCs: 10 * AT91SAM9260, AT91SAM9G20, AT91SAM9XE 11 * 12 * Note that those SoCs are mostly software and pin compatible, 13 * therefore this file applies to all of them. Differences between 14 * those SoCs are concentrated at the end of this file. 15 */ 16 17#ifndef AT91SAM9260_H 18#define AT91SAM9260_H 19 20/* 21 * Peripheral identifiers/interrupts. 22 */ 23#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 24#define ATMEL_ID_SYS 1 /* System Peripherals */ 25#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 26#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 27#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ 28#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */ 29#define ATMEL_ID_USART0 6 /* USART 0 */ 30#define ATMEL_ID_USART1 7 /* USART 1 */ 31#define ATMEL_ID_USART2 8 /* USART 2 */ 32#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ 33#define ATMEL_ID_UDP 10 /* USB Device Port */ 34#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ 35#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 36#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 37#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 38/* Reserved: 15 */ 39/* Reserved: 16 */ 40#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ 41#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ 42#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ 43#define ATMEL_ID_UHP 20 /* USB Host port */ 44#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */ 45#define ATMEL_ID_ISI 22 /* Image Sensor Interface */ 46#define ATMEL_ID_USART3 23 /* USART 3 */ 47#define ATMEL_ID_USART4 24 /* USART 4 */ 48/* USART5 or TWI1: 25 */ 49#define ATMEL_ID_TC3 26 /* Timer Counter 3 */ 50#define ATMEL_ID_TC4 27 /* Timer Counter 4 */ 51#define ATMEL_ID_TC5 28 /* Timer Counter 5 */ 52#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 53#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 54#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 55 56/* 57 * User Peripherals physical base addresses. 58 */ 59#define ATMEL_BASE_TCB0 0xfffa0000 60#define ATMEL_BASE_TC0 0xfffa0000 61#define ATMEL_BASE_TC1 0xfffa0040 62#define ATMEL_BASE_TC2 0xfffa0080 63#define ATMEL_BASE_UDP0 0xfffa4000 64#define ATMEL_BASE_MCI 0xfffa8000 65#define ATMEL_BASE_TWI0 0xfffac000 66#define ATMEL_BASE_USART0 0xfffb0000 67#define ATMEL_BASE_USART1 0xfffb4000 68#define ATMEL_BASE_USART2 0xfffb8000 69#define ATMEL_BASE_SSC0 0xfffbc000 70#define ATMEL_BASE_ISI0 0xfffc0000 71#define ATMEL_BASE_EMAC0 0xfffc4000 72#define ATMEL_BASE_SPI0 0xfffc8000 73#define ATMEL_BASE_SPI1 0xfffcc000 74#define ATMEL_BASE_USART3 0xfffd0000 75#define ATMEL_BASE_USART4 0xfffd4000 76/* USART5 or TWI1: 0xfffd8000 */ 77#define ATMEL_BASE_TCB1 0xfffdc000 78#define ATMEL_BASE_TC3 0xfffdc000 79#define ATMEL_BASE_TC4 0xfffdc040 80#define ATMEL_BASE_TC5 0xfffdc080 81#define ATMEL_BASE_ADC 0xfffe0000 82/* Reserved: 0xfffe4000 - 0xffffe7ff */ 83 84/* 85 * System Peripherals physical base addresses. 86 */ 87#define ATMEL_BASE_SYS 0xffffe800 88#define ATMEL_BASE_SDRAMC 0xffffea00 89#define ATMEL_BASE_SMC 0xffffec00 90#define ATMEL_BASE_MATRIX 0xffffee00 91#define ATMEL_BASE_CCFG 0xffffef14 92#define ATMEL_BASE_AIC 0xfffff000 93#define ATMEL_BASE_DBGU 0xfffff200 94#define ATMEL_BASE_PIOA 0xfffff400 95#define ATMEL_BASE_PIOB 0xfffff600 96#define ATMEL_BASE_PIOC 0xfffff800 97/* EEFC: 0xfffffa00 */ 98#define ATMEL_BASE_PMC 0xfffffc00 99#define ATMEL_BASE_RSTC 0xfffffd00 100#define ATMEL_BASE_SHDWN 0xfffffd10 101#define ATMEL_BASE_RTT 0xfffffd20 102#define ATMEL_BASE_PIT 0xfffffd30 103#define ATMEL_BASE_WDT 0xfffffd40 104/* GPBR(non-XE SoCs): 0xfffffd50 */ 105/* GPBR(XE SoCs): 0xfffffd60 */ 106/* Reserved: 0xfffffd70 - 0xffffffff */ 107 108/* 109 * Internal Memory common on all these SoCs 110 */ 111#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */ 112#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ 113/* SRAM or FLASH: 0x00200000 */ 114/* SRAM: 0x00300000 */ 115/* Reserved: 0x00400000 */ 116#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */ 117 118/* 119 * External memory 120 */ 121#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ 122#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 123#define ATMEL_BASE_CS2 0x30000000 124#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ 125#define ATMEL_BASE_CS4 0x50000000 126#define ATMEL_BASE_CS5 0x60000000 127#define ATMEL_BASE_CS6 0x70000000 128#define ATMEL_BASE_CS7 0x80000000 129 130/* Timer */ 131#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c 132 133/* 134 * Other misc defines 135 */ 136#if !CONFIG_IS_ENABLED(DM_GPIO) 137#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ 138#define ATMEL_BASE_PIO ATMEL_BASE_PIOA 139#endif 140#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 141 142/* 143 * SoC specific defines 144 */ 145#if defined(CONFIG_AT91SAM9XE) 146# define ATMEL_CPU_NAME "AT91SAM9XE" 147# define ATMEL_ID_TWI1 25 /* TWI 1 */ 148# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ 149# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ 150# define ATMEL_BASE_TWI1 0xfffd8000 151# define ATMEL_BASE_EEFC 0xfffffa00 152# define ATMEL_BASE_GPBR 0xfffffd60 153#elif defined(CONFIG_AT91SAM9260) 154# define ATMEL_CPU_NAME "AT91SAM9260" 155# define ATMEL_ID_USART5 25 /* USART 5 */ 156# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ 157# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ 158# define ATMEL_BASE_USART5 0xfffd8000 159# define ATMEL_BASE_GPBR 0xfffffd50 160#elif defined(CONFIG_AT91SAM9G20) 161# define ATMEL_CPU_NAME "AT91SAM9G20" 162# define ATMEL_ID_USART5 25 /* USART 5 */ 163# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ 164# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ 165# define ATMEL_BASE_USART5 0xfffd8000 166# define ATMEL_BASE_GPBR 0xfffffd50 167#endif 168 169#endif 170