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5
6#ifndef _DV_PSC_DEFS_H_
7#define _DV_PSC_DEFS_H_
8
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11
12
13struct dv_psc_regs {
14 unsigned int pid;
15 unsigned char rsvd0[16];
16 unsigned char rsvd1[4];
17 unsigned int inteval;
18 unsigned char rsvd2[36];
19 unsigned int merrpr0;
20 unsigned int merrpr1;
21 unsigned char rsvd3[8];
22 unsigned int merrcr0;
23 unsigned int merrcr1;
24 unsigned char rsvd4[8];
25 unsigned int perrpr;
26 unsigned char rsvd5[4];
27 unsigned int perrcr;
28 unsigned char rsvd6[4];
29 unsigned int epcpr;
30 unsigned char rsvd7[4];
31 unsigned int epccr;
32 unsigned char rsvd8[144];
33 unsigned char rsvd9[20];
34 unsigned int ptcmd;
35 unsigned char rsvd10[4];
36 unsigned int ptstat;
37 unsigned char rsvd11[212];
38 unsigned int pdstat0;
39 unsigned int pdstat1;
40 unsigned char rsvd12[248];
41 unsigned int pdctl0;
42 unsigned int pdctl1;
43 unsigned char rsvd13[536];
44 unsigned int mckout0;
45 unsigned int mckout1;
46 unsigned char rsvd14[728];
47 unsigned int mdstat[52];
48 unsigned char rsvd15[304];
49 unsigned int mdctl[52];
50};
51
52
53#define EMURSTIE_MASK (0x00000200)
54
55#define PD0 (0)
56
57#define PSC_ENABLE (0x3)
58#define PSC_DISABLE (0x2)
59#define PSC_SYNCRESET (0x1)
60#define PSC_SWRSTDISABLE (0x0)
61
62#define PSC_GOSTAT (1 << 0)
63#define PSC_MD_STATE_MSK (0x1f)
64
65#define PSC_CMD_GO (1 << 0)
66
67#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
68
69#endif
70