LXR uboot/arch/arm/mach-keystone/include/mach/ddr3.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * DDR3
   4 *
   5 * (C) Copyright 2014
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 */
   8
   9#ifndef _DDR3_H_
  10#define _DDR3_H_
  11
  12#include <asm/arch/hardware.h>
  13
  14struct ddr3_phy_config {
  15        unsigned int pllcr;
  16        unsigned int pgcr1_mask;
  17        unsigned int pgcr1_val;
  18        unsigned int ptr0;
  19        unsigned int ptr1;
  20        unsigned int ptr2;
  21        unsigned int ptr3;
  22        unsigned int ptr4;
  23        unsigned int dcr_mask;
  24        unsigned int dcr_val;
  25        unsigned int dtpr0;
  26        unsigned int dtpr1;
  27        unsigned int dtpr2;
  28        unsigned int mr0;
  29        unsigned int mr1;
  30        unsigned int mr2;
  31        unsigned int dtcr;
  32        unsigned int pgcr2;
  33        unsigned int zq0cr1;
  34        unsigned int zq1cr1;
  35        unsigned int zq2cr1;
  36        unsigned int pir_v1;
  37        unsigned int datx8_2_mask;
  38        unsigned int datx8_2_val;
  39        unsigned int datx8_3_mask;
  40        unsigned int datx8_3_val;
  41        unsigned int datx8_4_mask;
  42        unsigned int datx8_4_val;
  43        unsigned int datx8_5_mask;
  44        unsigned int datx8_5_val;
  45        unsigned int datx8_6_mask;
  46        unsigned int datx8_6_val;
  47        unsigned int datx8_7_mask;
  48        unsigned int datx8_7_val;
  49        unsigned int datx8_8_mask;
  50        unsigned int datx8_8_val;
  51        unsigned int pir_v2;
  52};
  53
  54struct ddr3_emif_config {
  55        unsigned int sdcfg;
  56        unsigned int sdtim1;
  57        unsigned int sdtim2;
  58        unsigned int sdtim3;
  59        unsigned int sdtim4;
  60        unsigned int zqcfg;
  61        unsigned int sdrfc;
  62};
  63
  64struct ddr3_spd_cb {
  65        char   dimm_name[32];
  66        struct ddr3_phy_config phy_cfg;
  67        struct ddr3_emif_config emif_cfg;
  68        unsigned int ddrspdclock;
  69        int    ddr_size_gbyte;
  70};
  71
  72u32 ddr3_init(void);
  73void ddr3_reset_ddrphy(void);
  74void ddr3_init_ecc(u32 base, u32 ddr3_size);
  75void ddr3_disable_ecc(u32 base);
  76void ddr3_check_ecc_int(u32 base);
  77int ddr3_ecc_support_rmw(u32 base);
  78void ddr3_err_reset_workaround(void);
  79void ddr3_enable_ecc(u32 base, int test);
  80void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
  81void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
  82int ddr3_get_size(void);
  83
  84#endif
  85