LXR uboot/arch/arm/mach-lpc32xx/devices.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
   4 */
   5
   6#include <common.h>
   7#include <dm.h>
   8#include <ns16550.h>
   9#include <dm/platform_data/lpc32xx_hsuart.h>
  10
  11#include <asm/arch/clk.h>
  12#include <asm/arch/uart.h>
  13#include <asm/arch/mux.h>
  14#include <asm/io.h>
  15
  16static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
  17static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
  18static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
  19
  20void lpc32xx_uart_init(unsigned int uart_id)
  21{
  22        if (uart_id < 1 || uart_id > 7)
  23                return;
  24
  25        /* Disable loopback mode, if it is set by S1L bootloader */
  26        clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
  27
  28        if (uart_id < 3 || uart_id > 6)
  29                return;
  30
  31        /* Enable UART system clock */
  32        setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
  33
  34        /* Set UART into autoclock mode */
  35        clrsetbits_le32(&ctrl->clkmode,
  36                        UART_CLKMODE_MASK(uart_id),
  37                        UART_CLKMODE_AUTO(uart_id));
  38
  39        /* Bypass pre-divider of UART clock */
  40        writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
  41               &clk->u3clk + (uart_id - 3));
  42}
  43
  44#if !CONFIG_IS_ENABLED(OF_CONTROL)
  45static const struct ns16550_plat lpc32xx_uart[] = {
  46        { .base = UART3_BASE, .reg_shift = 2,
  47          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  48        { .base = UART4_BASE, .reg_shift = 2,
  49          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  50        { .base = UART5_BASE, .reg_shift = 2,
  51          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  52        { .base = UART6_BASE, .reg_shift = 2,
  53          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  54};
  55
  56#if defined(CONFIG_LPC32XX_HSUART)
  57static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
  58        { HS_UART1_BASE, },
  59        { HS_UART2_BASE, },
  60        { HS_UART7_BASE, },
  61};
  62#endif
  63
  64U_BOOT_DRVINFOS(lpc32xx_uarts) = {
  65#if defined(CONFIG_LPC32XX_HSUART)
  66        { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
  67        { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
  68#endif
  69        { "ns16550_serial", &lpc32xx_uart[0], },
  70        { "ns16550_serial", &lpc32xx_uart[1], },
  71        { "ns16550_serial", &lpc32xx_uart[2], },
  72        { "ns16550_serial", &lpc32xx_uart[3], },
  73#if defined(CONFIG_LPC32XX_HSUART)
  74        { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
  75#endif
  76};
  77#endif
  78
  79void lpc32xx_dma_init(void)
  80{
  81        /* Enable DMA interface */
  82        writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
  83}
  84
  85void lpc32xx_mac_init(void)
  86{
  87        /* Enable MAC interface */
  88        writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
  89#if defined(CONFIG_RMII)
  90                | CLK_MAC_RMII,
  91#else
  92                | CLK_MAC_MII,
  93#endif
  94                &clk->macclk_ctrl);
  95}
  96
  97void lpc32xx_mlc_nand_init(void)
  98{
  99        /* Enable NAND interface */
 100        writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 101}
 102
 103void lpc32xx_slc_nand_init(void)
 104{
 105        /* Enable SLC NAND interface */
 106        writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
 107}
 108
 109void lpc32xx_usb_init(void)
 110{
 111        /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
 112        clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
 113}
 114
 115void lpc32xx_i2c_init(unsigned int devnum)
 116{
 117        /* Enable I2C interface */
 118        uint32_t ctrl = readl(&clk->i2cclk_ctrl);
 119        if (devnum == 1)
 120                ctrl |= CLK_I2C1_ENABLE;
 121        if (devnum == 2)
 122                ctrl |= CLK_I2C2_ENABLE;
 123        writel(ctrl, &clk->i2cclk_ctrl);
 124}
 125
 126U_BOOT_DRVINFO(lpc32xx_gpios) = {
 127        .name = "gpio_lpc32xx"
 128};
 129
 130/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
 131
 132#define P_MUX_SET_SSP0 0x1600
 133
 134void lpc32xx_ssp_init(void)
 135{
 136        /* Enable SSP0 interface */
 137        writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
 138        /* Mux SSP0 pins */
 139        writel(P_MUX_SET_SSP0, &mux->p_mux_set);
 140}
 141