1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef __BOARD_ENV_SPEC 7#define __BOARD_ENV_SPEC 8 9/* Board specific configuration */ 10 11/* KW40 */ 12#define MV_6710_DEV_ID 0x6710 13 14#define MV_6710_Z1_REV 0x0 15#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV) 16#define MV_6710_Z1_NAME "MV6710 Z1" 17 18/* Armada XP Family */ 19#define MV_78130_DEV_ID 0x7813 20#define MV_78160_DEV_ID 0x7816 21#define MV_78230_DEV_ID 0x7823 22#define MV_78260_DEV_ID 0x7826 23#define MV_78460_DEV_ID 0x7846 24#define MV_78000_DEV_ID 0x7888 25 26#define MV_FPGA_DEV_ID 0x2107 27 28#define MV_78XX0_Z1_REV 0x0 29 30/* boards ID numbers */ 31#define BOARD_ID_BASE 0x0 32 33/* New board ID numbers */ 34#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1) 35#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) 36#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) 37#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) 38#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1) 39#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1) 40#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1) 41#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1) 42#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1) 43#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) 44#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) 45#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) 46#define INVALID_BOARD_ID 0xFFFFFFFF 47 48/* Sample at Reset */ 49#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) 50 51/* BIOS Modes related defines */ 52 53#define SAR0_BOOTWIDTH_OFFSET 3 54#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET) 55#define SAR0_BOOTSRC_OFFSET 5 56#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET) 57 58#define SAR0_L2_SIZE_OFFSET 19 59#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET) 60#define SAR0_CPU_FREQ_OFFSET 21 61#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET) 62#define SAR0_FABRIC_FREQ_OFFSET 24 63#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET) 64#define SAR0_CPU0CORE_OFFSET 31 65#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET) 66#define SAR1_CPU0CORE_OFFSET 0 67#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET) 68 69#define PEX_CLK_100MHZ_OFFSET 2 70#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET) 71 72#define SAR1_FABRIC_MODE_OFFSET 19 73#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET) 74#define SAR1_CPU_MODE_OFFSET 20 75#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET) 76 77#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) 78 79 80#define CORE_AVS_CONTROL_0REG 0x18300 81#define CORE_AVS_CONTROL_2REG 0x18308 82#define CPU_AVS_CONTROL2_REG 0x20868 83#define CPU_AVS_CONTROL0_REG 0x20860 84#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0 85 86#define MSAR_TCLK_OFFS 28 87#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) 88 89 90/* Controler environment registers offsets */ 91#define GEN_PURP_RES_1_REG 0x182F4 92#define GEN_PURP_RES_2_REG 0x182F8 93 94/* registers offsets */ 95#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40)) 96#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 97#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) 98#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0) 99 100#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 101#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */ 102#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 103#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08) 104#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C) 105#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 106#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14) 107#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18) 108#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C) 109#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40)) 110#define GPP_64_66_DATA_OUT_SET_REG 0x181A4 111#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40)) 112#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0 113#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40) 114 115#define MV_GPP66 (1 << 2) 116 117/* Relevant for MV78XX0 */ 118#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20) 119#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24) 120 121/* This define describes the maximum number of supported PEX Interfaces */ 122#define MV_PEX_MAX_IF 10 123#define MV_PEX_MAX_UNIT 4 124 125#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12))) 126 127#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \ 128 ((unit)/2 * 0x2000) + 0x1B00) 129 130#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000) 131 132#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804) 133#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C) 134#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918) 135#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920) 136#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058) 137#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C) 138#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810) 139#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834) 140#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838) 141#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C) 142#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840) 143 144#define MV_ETH_BASE_ADDR (0x72000) 145#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \ 146 0x40000 + ((port) % 2) * 0x4000) 147#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port) 148 149 150#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04) 151#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C) 152#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18) 153#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0) 154#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4) 155#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20) 156#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38) 157#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0) 158 159#define SERDES_LINE_MUX_REG_0_7 0x18270 160#define SERDES_LINE_MUX_REG_8_15 0x18274 161#define QSGMII_CONTROL_1_REG 0x18404 162 163/* SOC_CTRL_REG fields */ 164#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) 165#define SCR_PEX_ENA_MASK(pex) (1 << pex) 166 167#define PCIE0_QUADX1_EN (1<<7) 168#define PCIE1_QUADX1_EN (1<<8) 169 170#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) 171#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) 172 173#define PCIE1_CLK_OUT_EN_OFF 5 174#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF) 175 176#define PCIE0_CLK_OUT_EN_OFF 4 177#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF) 178 179#define SCR_PEX0_4BY1_OFFS 7 180#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS) 181 182#define SCR_PEX1_4BY1_OFFS 8 183#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) 184 185 186#define MV_MISC_REGS_OFFSET (0x18200) 187#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) 188#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) 189 190/* 191 * PCI Express Control and Status Registers 192 */ 193#define MAX_PEX_DEVICES 32 194#define MAX_PEX_FUNCS 8 195#define MAX_PEX_BUSSES 256 196 197#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ 198#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) 199 200#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ 201#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) 202 203#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */ 204#define PXCAR_CONFIG_EN (1 << 31) 205#define PEX_STATUS_AND_COMMAND 0x004 206#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */ 207 208/* PCI Express Configuration Address Register */ 209 210/* PEX_CFG_ADDR_REG (PXCAR) */ 211#define PXCAR_REG_NUM_OFFS 2 212#define PXCAR_REG_NUM_MAX 0x3F 213#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) 214#define PXCAR_FUNC_NUM_OFFS 8 215#define PXCAR_FUNC_NUM_MAX 0x7 216#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) 217#define PXCAR_DEVICE_NUM_OFFS 11 218#define PXCAR_DEVICE_NUM_MAX 0x1F 219#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) 220#define PXCAR_BUS_NUM_OFFS 16 221#define PXCAR_BUS_NUM_MAX 0xFF 222#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) 223#define PXCAR_EXT_REG_NUM_OFFS 24 224#define PXCAR_EXT_REG_NUM_MAX 0xF 225 226#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 227#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) 228 229 230#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60) 231#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C) 232#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70) 233#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90) 234#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00) 235#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04) 236#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10) 237#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18) 238#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20) 239#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30) 240#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C) 241#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50) 242#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60) 243#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64) 244 245#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */ 246#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS) 247#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS) 248#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS) 249 250#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8) 251#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC) 252#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900) 253 254#define PEX_CAPABILITY_REG 0x60 255#define PEX_DEV_CAPABILITY_REG 0x64 256#define PEX_DEV_CTRL_STAT_REG 0x68 257#define PEX_LINK_CAPABILITY_REG 0x6C 258#define PEX_LINK_CTRL_STAT_REG 0x70 259#define PEX_LINK_CTRL_STAT_2_REG 0x90 260 261#endif /* __BOARD_ENV_SPEC */ 262