LXR uboot/arch/arm/mach-mvebu/serdes/axp/high_speed_env

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) Marvell International Ltd. and its affiliates
   4 */
   5
   6#ifndef __HIGHSPEED_ENV_SPEC_H
   7#define __HIGHSPEED_ENV_SPEC_H
   8
   9#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  10
  11typedef enum {
  12        SERDES_UNIT_UNCONNECTED = 0x0,
  13        SERDES_UNIT_PEX         = 0x1,
  14        SERDES_UNIT_SATA        = 0x2,
  15        SERDES_UNIT_SGMII0      = 0x3,
  16        SERDES_UNIT_SGMII1      = 0x4,
  17        SERDES_UNIT_SGMII2      = 0x5,
  18        SERDES_UNIT_SGMII3      = 0x6,
  19        SERDES_UNIT_QSGMII      = 0x7,
  20        SERDES_UNIT_SETM        = 0x8,
  21        SERDES_LAST_UNIT
  22} MV_BIN_SERDES_UNIT_INDX;
  23
  24
  25typedef enum {
  26        PEX_BUS_DISABLED        = 0,
  27        PEX_BUS_MODE_X1         = 1,
  28        PEX_BUS_MODE_X4         = 2,
  29        PEX_BUS_MODE_X8         = 3
  30} MV_PEX_UNIT_CFG;
  31
  32typedef enum pex_type {
  33        MV_PEX_ROOT_COMPLEX,    /* root complex device */
  34        MV_PEX_END_POINT        /* end point device */
  35} MV_PEX_TYPE;
  36
  37typedef struct serdes_change_m_phy {
  38        MV_BIN_SERDES_UNIT_INDX type;
  39        u32 reg_low_speed;
  40        u32 val_low_speed;
  41        u32 reg_hi_speed;
  42        u32 val_hi_speed;
  43} MV_SERDES_CHANGE_M_PHY;
  44
  45/*
  46 * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
  47 */
  48typedef struct board_serdes_conf {
  49        MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
  50        u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
  51        u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
  52        MV_PEX_UNIT_CFG pex_mode[4];
  53
  54        /*
  55         * Bus speed - one bit per SERDES line:
  56         *              Low speed (0)           High speed (1)
  57         * PEX          2.5 G (10 bit)          5 G (20 bit)
  58         * SATA         1.5 G                   3 G
  59         * SGMII        1.25 Gbps               3.125 Gbps
  60         */
  61        u32     bus_speed;
  62
  63        MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
  64} MV_BIN_SERDES_CFG;
  65
  66
  67#define BIN_SERDES_CFG {        \
  68        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */       \
  69        {0, 1, -1 , -1, -1, -1, -1, -1,  2}, /* Lane 1 */       \
  70        {0, 1, -1 ,  2, -1, -1, -1, -1,  3}, /* Lane 2 */       \
  71        {0, 1, -1 , -1,  2, -1, -1,  3, -1}, /* Lane 3 */       \
  72        {0, 1,  2 , -1, -1,  3, -1, -1,  4}, /* Lane 4 */       \
  73        {0, 1,  2 , -1,  3, -1, -1,  4, -1}, /* Lane 5 */       \
  74        {0, 1,  2 ,  4, -1,  3, -1, -1, -1}, /* Lane 6 */       \
  75        {0, 1, -1 ,  2, -1, -1,  3, -1,  4}, /* Lane 7*/        \
  76        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */       \
  77        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */       \
  78        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */      \
  79        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */      \
  80        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */      \
  81        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */      \
  82        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */      \
  83        {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */      \
  84}
  85
  86#endif /* __HIGHSPEED_ENV_SPEC_H */
  87