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14#include <common.h>
15#include <init.h>
16#include <asm/io.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/cpu.h>
19#include <asm/arch/clock.h>
20#include <power/tps65910.h>
21#include <linux/compiler.h>
22
23struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
24
25
26
27
28u32 get_cpu_rev(void)
29{
30 u32 id;
31 u32 rev;
32
33 id = readl(DEVICE_ID);
34 rev = (id >> 28) & 0xff;
35
36 return rev;
37}
38
39
40
41
42u32 get_cpu_type(void)
43{
44 u32 id = 0;
45 u32 partnum;
46
47 id = readl(DEVICE_ID);
48 partnum = (id >> 12) & 0xffff;
49
50 return partnum;
51}
52
53
54
55
56u32 get_sysboot_value(void)
57{
58 return readl(&cstat->statusreg) & SYSBOOT_MASK;
59}
60
61u32 get_sys_clk_index(void)
62{
63 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
64 u32 ind = readl(&ctrl->statusreg);
65
66#ifdef CONFIG_AM43XX
67 u32 src;
68 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
69 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE)
70 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
71 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
72 else
73#endif
74 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
75 CTRL_SYSBOOT_15_14_SHIFT);
76}
77
78
79#ifdef CONFIG_DISPLAY_CPUINFO
80static char *cpu_revs[] = {
81 "1.0",
82 "2.0",
83 "2.1"};
84
85static char *cpu_revs_am43xx[] = {
86 "1.0",
87 "1.1",
88 "1.2"};
89
90static char *dev_types[] = {
91 "TST",
92 "EMU",
93 "HS",
94 "GP"};
95
96
97
98
99int print_cpuinfo(void)
100{
101 char *cpu_s, *sec_s, *rev_s;
102 char **cpu_rev_arr = cpu_revs;
103
104 switch (get_cpu_type()) {
105 case AM335X:
106 cpu_s = "AM335X";
107 break;
108 case TI81XX:
109 cpu_s = "TI81XX";
110 break;
111 case AM437X:
112 cpu_s = "AM437X";
113 cpu_rev_arr = cpu_revs_am43xx;
114 break;
115 default:
116 cpu_s = "Unknown CPU type";
117 break;
118 }
119
120 if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
121 rev_s = cpu_rev_arr[get_cpu_rev()];
122 else
123 rev_s = "?";
124
125 if (get_device_type() < ARRAY_SIZE(dev_types))
126 sec_s = dev_types[get_device_type()];
127 else
128 sec_s = "?";
129
130 printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
131
132 return 0;
133}
134#endif
135
136#ifdef CONFIG_AM33XX
137int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
138{
139 int sil_rev;
140
141 sil_rev = readl(&cdev->deviceid) >> 28;
142
143 if (sil_rev == 0) {
144
145 return MPUPLL_M_720;
146 } else if (sil_rev >= 1) {
147
148 int efuse_arm_mpu_max_freq, package_type;
149 efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
150 package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
151 PACKAGE_TYPE_SHIFT;
152
153
154 if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
155 PACKAGE_TYPE_RESERVED)
156 return MPUPLL_M_800;
157
158 switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
159 case AM335X_ZCZ_1000:
160 return MPUPLL_M_1000;
161 case AM335X_ZCZ_800:
162 return MPUPLL_M_800;
163 case AM335X_ZCZ_720:
164 return MPUPLL_M_720;
165 case AM335X_ZCZ_600:
166 case AM335X_ZCE_600:
167 return MPUPLL_M_600;
168 case AM335X_ZCZ_300:
169 case AM335X_ZCE_300:
170 return MPUPLL_M_300;
171 }
172 }
173
174
175 return MPUPLL_M_720;
176}
177
178int am335x_get_mpu_vdd(int sil_rev, int frequency)
179{
180 int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
181
182 switch (sel_mask) {
183 case TPS65910_OP_REG_SEL_1_3_2_5:
184 return 1325000;
185 case TPS65910_OP_REG_SEL_1_2_0:
186 return 1200000;
187 case TPS65910_OP_REG_SEL_1_1_0:
188 return 1100000;
189 default:
190 return 1262500;
191 }
192}
193
194int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
195{
196
197 if (sil_rev >= 1) {
198 switch (frequency) {
199 case MPUPLL_M_1000:
200 return TPS65910_OP_REG_SEL_1_3_2_5;
201 case MPUPLL_M_800:
202 return TPS65910_OP_REG_SEL_1_2_6;
203 case MPUPLL_M_720:
204 return TPS65910_OP_REG_SEL_1_2_0;
205 case MPUPLL_M_600:
206 case MPUPLL_M_500:
207 case MPUPLL_M_300:
208 return TPS65910_OP_REG_SEL_1_1_0;
209 }
210 }
211
212
213 return TPS65910_OP_REG_SEL_1_2_6;
214}
215#endif
216