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11#ifndef _ORION5X_CPU_H
12#define _ORION5X_CPU_H
13
14#include <asm/system.h>
15
16#ifndef __ASSEMBLY__
17
18#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
19 | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
20
21#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
22 ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
23
24enum memory_bank {
25 BANK0,
26 BANK1,
27 BANK2,
28 BANK3
29};
30
31enum orion5x_cpu_winen {
32 ORION5X_WIN_DISABLE,
33 ORION5X_WIN_ENABLE
34};
35
36enum orion5x_cpu_target {
37 ORION5X_TARGET_DRAM = 0,
38 ORION5X_TARGET_DEVICE = 1,
39 ORION5X_TARGET_PCI = 3,
40 ORION5X_TARGET_PCIE = 4,
41 ORION5X_TARGET_SASRAM = 9
42};
43
44enum orion5x_cpu_attrib {
45 ORION5X_ATTR_DRAM_CS0 = 0x0e,
46 ORION5X_ATTR_DRAM_CS1 = 0x0d,
47 ORION5X_ATTR_DRAM_CS2 = 0x0b,
48 ORION5X_ATTR_DRAM_CS3 = 0x07,
49 ORION5X_ATTR_PCI_MEM = 0x59,
50 ORION5X_ATTR_PCI_IO = 0x51,
51 ORION5X_ATTR_PCIE_MEM = 0x59,
52 ORION5X_ATTR_PCIE_IO = 0x51,
53 ORION5X_ATTR_SASRAM = 0x00,
54 ORION5X_ATTR_DEV_CS0 = 0x1e,
55 ORION5X_ATTR_DEV_CS1 = 0x1d,
56 ORION5X_ATTR_DEV_CS2 = 0x1b,
57 ORION5X_ATTR_BOOTROM = 0x0f
58};
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66
67#if !defined (ORION5X_ADR_PCIE_MEM)
68#define ORION5X_ADR_PCIE_MEM 0x90000000
69#endif
70
71#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
72#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000
73#endif
74
75#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
76#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0
77#endif
78
79#if !defined (ORION5X_SZ_PCIE_MEM)
80#define ORION5X_SZ_PCIE_MEM (128*1024*1024)
81#endif
82
83#if !defined (ORION5X_ADR_PCIE_IO)
84#define ORION5X_ADR_PCIE_IO 0xf0000000
85#endif
86
87#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
88#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000
89#endif
90
91#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
92#define ORION5X_ADR_PCIE_IO_REMAP_HI 0
93#endif
94
95#if !defined (ORION5X_SZ_PCIE_IO)
96#define ORION5X_SZ_PCIE_IO (64*1024)
97#endif
98
99#if !defined (ORION5X_ADR_PCI_MEM)
100#define ORION5X_ADR_PCI_MEM 0x98000000
101#endif
102
103#if !defined (ORION5X_SZ_PCI_MEM)
104#define ORION5X_SZ_PCI_MEM (128*1024*1024)
105#endif
106
107#if !defined (ORION5X_ADR_PCI_IO)
108#define ORION5X_ADR_PCI_IO 0xf0100000
109#endif
110
111#if !defined (ORION5X_SZ_PCI_IO)
112#define ORION5X_SZ_PCI_IO (64*1024)
113#endif
114
115#if !defined (ORION5X_ADR_DEV_CS0)
116#define ORION5X_ADR_DEV_CS0 0xfa000000
117#endif
118
119#if !defined (ORION5X_SZ_DEV_CS0)
120#define ORION5X_SZ_DEV_CS0 (2*1024*1024)
121#endif
122
123#if !defined (ORION5X_ADR_DEV_CS1)
124#define ORION5X_ADR_DEV_CS1 0xf8000000
125#endif
126
127#if !defined (ORION5X_SZ_DEV_CS1)
128#define ORION5X_SZ_DEV_CS1 (32*1024*1024)
129#endif
130
131#if !defined (ORION5X_ADR_DEV_CS2)
132#define ORION5X_ADR_DEV_CS2 0xfa800000
133#endif
134
135#if !defined (ORION5X_SZ_DEV_CS2)
136#define ORION5X_SZ_DEV_CS2 (1*1024*1024)
137#endif
138
139#if !defined (ORION5X_ADR_BOOTROM)
140#define ORION5X_ADR_BOOTROM 0xFFF80000
141#endif
142
143#if !defined (ORION5X_SZ_BOOTROM)
144#define ORION5X_SZ_BOOTROM (512*1024)
145#endif
146
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149
150#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
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160
161#define MV88F5181_DEV_ID 0x5181
162#define MV88F5181_REV_B1 3
163#define MV88F5181L_REV_A0 8
164#define MV88F5181L_REV_A1 9
165
166#define MV88F5182_DEV_ID 0x5182
167#define MV88F5182_REV_A2 2
168
169#define MV88F5281_DEV_ID 0x5281
170#define MV88F5281_REV_D0 4
171#define MV88F5281_REV_D1 5
172#define MV88F5281_REV_D2 6
173
174#define MV88F6183_DEV_ID 0x6183
175#define MV88F6183_REV_B0 3
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180
181static inline unsigned int readfr_extra_feature_reg(void)
182{
183 unsigned int val;
184 asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
185 (val) : : "cc");
186 return val;
187}
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192
193static inline void writefr_extra_feature_reg(unsigned int val)
194{
195 asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
196 (val) : "cc");
197 isb();
198}
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205struct orion5x_win_registers {
206 u32 ctrl;
207 u32 base;
208 u32 remap_lo;
209 u32 remap_hi;
210};
211
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215
216struct orion5x_cpu_registers {
217 u32 config;
218 u32 ctrl_stat;
219 u32 rstoutn_mask;
220 u32 sys_soft_rst;
221 u32 ahb_mbus_cause_irq;
222 u32 ahb_mbus_mask_irq;
223};
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228
229struct orion5x_ddr_addr_decode_registers {
230 u32 base;
231 u32 size;
232};
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237u32 orion5x_device_id(void);
238u32 orion5x_device_rev(void);
239unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
240void timer_init_r(void);
241#endif
242#endif
243