1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6#ifndef _CLOCK_MANAGER_GEN5_H_ 7#define _CLOCK_MANAGER_GEN5_H_ 8 9#ifndef __ASSEMBLY__ 10 11#include <linux/bitops.h> 12 13struct cm_config { 14 /* main group */ 15 u32 main_vco_base; 16 u32 mpuclk; 17 u32 mainclk; 18 u32 dbgatclk; 19 u32 mainqspiclk; 20 u32 mainnandsdmmcclk; 21 u32 cfg2fuser0clk; 22 u32 maindiv; 23 u32 dbgdiv; 24 u32 tracediv; 25 u32 l4src; 26 27 /* peripheral group */ 28 u32 peri_vco_base; 29 u32 emac0clk; 30 u32 emac1clk; 31 u32 perqspiclk; 32 u32 pernandsdmmcclk; 33 u32 perbaseclk; 34 u32 s2fuser1clk; 35 u32 perdiv; 36 u32 gpiodiv; 37 u32 persrc; 38 39 /* sdram pll group */ 40 u32 sdram_vco_base; 41 u32 ddrdqsclk; 42 u32 ddr2xdqsclk; 43 u32 ddrdqclk; 44 u32 s2fuser2clk; 45 46 /* altera group */ 47 u32 altera_grp_mpuclk; 48}; 49 50/* Clock manager group */ 51#define CLKMGR_GEN5_CTRL 0x00 52#define CLKMGR_GEN5_BYPASS 0x04 53#define CLKMGR_GEN5_INTER 0x08 54#define CLKMGR_GEN5_STAT 0x14 55/* MainPLL group */ 56#define CLKMGR_GEN5_MAINPLL_VCO 0x40 57#define CLKMGR_GEN5_MAINPLL_MISC 0x44 58#define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48 59#define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c 60#define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50 61#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54 62#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58 63#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c 64#define CLKMGR_GEN5_MAINPLL_EN 0x60 65#define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64 66#define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68 67#define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c 68#define CLKMGR_GEN5_MAINPLL_L4SRC 0x70 69/* Peripheral PLL group */ 70#define CLKMGR_GEN5_PERPLL_VCO 0x80 71#define CLKMGR_GEN5_PERPLL_MISC 0x84 72#define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88 73#define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c 74#define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90 75#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94 76#define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98 77#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c 78#define CLKMGR_GEN5_PERPLL_EN 0xa0 79#define CLKMGR_GEN5_PERPLL_DIV 0xa4 80#define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8 81#define CLKMGR_GEN5_PERPLL_SRC 0xac 82/* SDRAM PLL group */ 83#define CLKMGR_GEN5_SDRPLL_VCO 0xc0 84#define CLKMGR_GEN5_SDRPLL_CTRL 0xc4 85#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8 86#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc 87#define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0 88#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4 89#define CLKMGR_GEN5_SDRPLL_EN 0xd8 90/* Altera group */ 91#define CLKMGR_GEN5_ALTR_MPUCLK 0xe0 92#define CLKMGR_GEN5_ALTR_MAINCLK 0xe4 93 94#define CLKMGR_STAT CLKMGR_GEN5_STAT 95#define CLKMGR_INTER CLKMGR_GEN5_INTER 96#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN 97 98/* Clock speed accessors */ 99unsigned long cm_get_sdram_clk_hz(void); 100unsigned int cm_get_l4_sp_clk_hz(void); 101unsigned int cm_get_mmc_controller_clk_hz(void); 102unsigned int cm_get_spi_controller_clk_hz(void); 103const unsigned int cm_get_osc_clk_hz(const int osc); 104const unsigned int cm_get_f2s_per_ref_clk_hz(void); 105const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); 106 107/* Clock configuration accessors */ 108int cm_basic_init(const struct cm_config * const cfg); 109const struct cm_config * const cm_get_default_config(void); 110#endif /* __ASSEMBLY__ */ 111 112#include <linux/bitops.h> 113#define LOCKED_MASK \ 114 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ 115 CLKMGR_INTER_PERPLLLOCKED_MASK | \ 116 CLKMGR_INTER_MAINPLLLOCKED_MASK) 117 118#define CLKMGR_CTRL_SAFEMODE BIT(0) 119#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 120 121#define CLKMGR_BYPASS_PERPLLSRC BIT(4) 122#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 123#define CLKMGR_BYPASS_PERPLL BIT(3) 124#define CLKMGR_BYPASS_PERPLL_OFFSET 3 125#define CLKMGR_BYPASS_SDRPLLSRC BIT(2) 126#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 127#define CLKMGR_BYPASS_SDRPLL BIT(1) 128#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 129#define CLKMGR_BYPASS_MAINPLL BIT(0) 130#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 131 132#define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3) 133#define CLKMGR_INTER_PERPLLLOST_MASK BIT(4) 134#define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5) 135#define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6) 136#define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7) 137#define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8) 138 139#define CLKMGR_STAT_BUSY BIT(0) 140 141/* Main PLL */ 142#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) 143#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 144#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 145#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 146#define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) 147#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 148#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 149#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 150#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 151#define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) 152#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 153#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 154#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 155 156#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 157#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 158 159#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 160#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 161 162#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 163#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 164 165#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 166#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 167 168#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 169#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 170 171#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 172#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 173 174#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) 175#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4) 176#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5) 177#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6) 178#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7) 179#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9) 180 181#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 182#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 183#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 184#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 185#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 186#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 187#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 188#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 189 190#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 191#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 192#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 193#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 194 195#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 196#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 197 198#define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) 199#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 200#define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) 201#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 202#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 203#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 204#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 205 206/* Per PLL */ 207#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 208#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 209#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 210#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 211#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 212#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 213#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 214#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 215#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 216#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 217#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 218 219#define CLKMGR_VCO_SSRC_EOSC1 0x0 220#define CLKMGR_VCO_SSRC_EOSC2 0x1 221#define CLKMGR_VCO_SSRC_F2S 0x2 222 223#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 224#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 225 226#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 227#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 228 229#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 230#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 231 232#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 233#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 234 235#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 236#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 237 238#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 239#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 240 241#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 242#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 243 244#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 245#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 246#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 247#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 248#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 249#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 250#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 251#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 252 253#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 254#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 255 256#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 257#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 258#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 259#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 260#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 261#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 262#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 263#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 264#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 265#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 266#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 267#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 268#define CLKMGR_QSPI_CLK_SRC_PER 0x2 269 270/* SDR PLL */ 271#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 272#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 273#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 274#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 275#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) 276#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 277#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 278#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 279#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31) 280#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 281#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 282#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 283 284#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 285#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 286#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 287#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 288 289#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 290#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 291#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 292#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 293 294#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 295#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 296#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 297#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 298 299#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 300#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 301#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 302#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 303 304#endif /* _CLOCK_MANAGER_GEN5_H_ */ 305