LXR uboot/arch/arm/mach-socfpga/spl

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4 *
   5 */
   6
   7#include <hang.h>
   8#include <init.h>
   9#include <log.h>
  10#include <asm/global_data.h>
  11#include <asm/io.h>
  12#include <asm/u-boot.h>
  13#include <asm/utils.h>
  14#include <common.h>
  15#include <debug_uart.h>
  16#include <image.h>
  17#include <spl.h>
  18#include <asm/arch/clock_manager.h>
  19#include <asm/arch/firewall.h>
  20#include <asm/arch/mailbox_s10.h>
  21#include <asm/arch/misc.h>
  22#include <asm/arch/reset_manager.h>
  23#include <asm/arch/system_manager.h>
  24#include <watchdog.h>
  25#include <dm/uclass.h>
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29void board_init_f(ulong dummy)
  30{
  31        const struct cm_config *cm_default_cfg = cm_get_default_config();
  32        int ret;
  33
  34        ret = spl_early_init();
  35        if (ret)
  36                hang();
  37
  38        socfpga_get_managers_addr();
  39
  40        /* Ensure watchdog is paused when debugging is happening */
  41        writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  42               socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  43
  44#ifdef CONFIG_HW_WATCHDOG
  45        /* Enable watchdog before initializing the HW */
  46        socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  47        socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  48        hw_watchdog_init();
  49#endif
  50
  51        /* ensure all processors are not released prior Linux boot */
  52        writeq(0, CPU_RELEASE_ADDR);
  53
  54        socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  55        timer_init();
  56
  57        sysmgr_pinmux_init();
  58
  59        /* configuring the HPS clocks */
  60        cm_basic_init(cm_default_cfg);
  61
  62#ifdef CONFIG_DEBUG_UART
  63        socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  64        debug_uart_init();
  65#endif
  66
  67        preloader_console_init();
  68        print_reset_info();
  69        cm_print_clock_quick_summary();
  70
  71        firewall_setup();
  72
  73        /* disable ocram security at CCU for non secure access */
  74        clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  75                     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  76        clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  77                     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  78
  79#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  80                struct udevice *dev;
  81
  82                ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  83                if (ret) {
  84                        debug("DRAM init failed: %d\n", ret);
  85                        hang();
  86                }
  87#endif
  88
  89        mbox_init();
  90
  91#ifdef CONFIG_CADENCE_QSPI
  92        mbox_qspi_open();
  93#endif
  94}
  95