LXR uboot/arch/arm/mach-stm32mp/include/mach/stm32.h

   1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2/*
   3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4 */
   5
   6#ifndef _MACH_STM32_H_
   7#define _MACH_STM32_H_
   8
   9#ifndef __ASSEMBLY__
  10#include <linux/bitops.h>
  11#endif
  12
  13/*
  14 * Peripheral memory map
  15 * only address used before device tree parsing
  16 */
  17#define STM32_RCC_BASE                  0x50000000
  18#define STM32_PWR_BASE                  0x50001000
  19#define STM32_DBGMCU_BASE               0x50081000
  20#define STM32_FMC2_BASE                 0x58002000
  21#define STM32_TZC_BASE                  0x5C006000
  22#define STM32_ETZPC_BASE                0x5C007000
  23#define STM32_STGEN_BASE                0x5C008000
  24#define STM32_TAMP_BASE                 0x5C00A000
  25
  26#define STM32_USART1_BASE               0x5C000000
  27#define STM32_USART2_BASE               0x4000E000
  28#define STM32_USART3_BASE               0x4000F000
  29#define STM32_UART4_BASE                0x40010000
  30#define STM32_UART5_BASE                0x40011000
  31#define STM32_USART6_BASE               0x44003000
  32#define STM32_UART7_BASE                0x40018000
  33#define STM32_UART8_BASE                0x40019000
  34
  35#define STM32_SDMMC1_BASE               0x58005000
  36#define STM32_SDMMC2_BASE               0x58007000
  37#define STM32_SDMMC3_BASE               0x48004000
  38
  39#define STM32_SYSRAM_BASE               0x2FFC0000
  40#define STM32_SYSRAM_SIZE               SZ_256K
  41
  42#define STM32_DDR_BASE                  0xC0000000
  43#define STM32_DDR_SIZE                  SZ_1G
  44
  45#ifndef __ASSEMBLY__
  46/* enumerated used to identify the SYSCON driver instance */
  47enum {
  48        STM32MP_SYSCON_UNKNOWN,
  49        STM32MP_SYSCON_SYSCFG,
  50};
  51
  52/*
  53 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
  54 * - boot device = bit 8:4
  55 * - boot instance = bit 3:0
  56 */
  57#define BOOT_TYPE_MASK          0xF0
  58#define BOOT_TYPE_SHIFT         4
  59#define BOOT_INSTANCE_MASK      0x0F
  60#define BOOT_INSTANCE_SHIFT     0
  61
  62enum boot_device {
  63        BOOT_FLASH_SD = 0x10,
  64        BOOT_FLASH_SD_1 = 0x11,
  65        BOOT_FLASH_SD_2 = 0x12,
  66        BOOT_FLASH_SD_3 = 0x13,
  67
  68        BOOT_FLASH_EMMC = 0x20,
  69        BOOT_FLASH_EMMC_1 = 0x21,
  70        BOOT_FLASH_EMMC_2 = 0x22,
  71        BOOT_FLASH_EMMC_3 = 0x23,
  72
  73        BOOT_FLASH_NAND = 0x30,
  74        BOOT_FLASH_NAND_FMC = 0x31,
  75
  76        BOOT_FLASH_NOR = 0x40,
  77        BOOT_FLASH_NOR_QSPI = 0x41,
  78
  79        BOOT_SERIAL_UART = 0x50,
  80        BOOT_SERIAL_UART_1 = 0x51,
  81        BOOT_SERIAL_UART_2 = 0x52,
  82        BOOT_SERIAL_UART_3 = 0x53,
  83        BOOT_SERIAL_UART_4 = 0x54,
  84        BOOT_SERIAL_UART_5 = 0x55,
  85        BOOT_SERIAL_UART_6 = 0x56,
  86        BOOT_SERIAL_UART_7 = 0x57,
  87        BOOT_SERIAL_UART_8 = 0x58,
  88
  89        BOOT_SERIAL_USB = 0x60,
  90        BOOT_SERIAL_USB_OTG = 0x62,
  91
  92        BOOT_FLASH_SPINAND = 0x70,
  93        BOOT_FLASH_SPINAND_1 = 0x71,
  94};
  95
  96/* TAMP registers */
  97#define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
  98#define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
  99#define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
 100#define TAMP_COPRO_RSC_TBL_ADDRESS      TAMP_BACKUP_REGISTER(17)
 101#define TAMP_COPRO_STATE                TAMP_BACKUP_REGISTER(18)
 102#define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
 103#define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
 104
 105#define TAMP_COPRO_STATE_OFF            0
 106#define TAMP_COPRO_STATE_INIT           1
 107#define TAMP_COPRO_STATE_CRUN           2
 108#define TAMP_COPRO_STATE_CSTOP          3
 109#define TAMP_COPRO_STATE_STANDBY        4
 110#define TAMP_COPRO_STATE_CRASH          5
 111
 112#define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
 113#define TAMP_BOOT_MODE_SHIFT            8
 114#define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
 115#define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
 116#define TAMP_BOOT_FORCED_MASK           GENMASK(7, 0)
 117#define TAMP_BOOT_DEBUG_ON              BIT(16)
 118
 119enum forced_boot_mode {
 120        BOOT_NORMAL = 0x00,
 121        BOOT_FASTBOOT = 0x01,
 122        BOOT_RECOVERY = 0x02,
 123        BOOT_STM32PROG = 0x03,
 124        BOOT_UMS_MMC0 = 0x10,
 125        BOOT_UMS_MMC1 = 0x11,
 126        BOOT_UMS_MMC2 = 0x12,
 127};
 128
 129/* offset used for BSEC driver: misc_read and misc_write */
 130#define STM32_BSEC_SHADOW_OFFSET        0x0
 131#define STM32_BSEC_SHADOW(id)           (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
 132#define STM32_BSEC_OTP_OFFSET           0x80000000
 133#define STM32_BSEC_OTP(id)              (STM32_BSEC_OTP_OFFSET + (id) * 4)
 134#define STM32_BSEC_LOCK_OFFSET          0xC0000000
 135#define STM32_BSEC_LOCK(id)             (STM32_BSEC_LOCK_OFFSET + (id) * 4)
 136
 137/* BSEC OTP index */
 138#define BSEC_OTP_RPN    1
 139#define BSEC_OTP_SERIAL 13
 140#define BSEC_OTP_PKG    16
 141#define BSEC_OTP_MAC    57
 142#define BSEC_OTP_BOARD  59
 143
 144#endif /* __ASSEMBLY__ */
 145#endif /* _MACH_STM32_H_ */
 146