LXR uboot/arch/arm/mach-sunxi/board.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   4 *
   5 * (C) Copyright 2007-2011
   6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7 * Tom Cubie <tangliang@allwinnertech.com>
   8 *
   9 * Some init for sunxi platform.
  10 */
  11
  12#include <common.h>
  13#include <cpu_func.h>
  14#include <init.h>
  15#include <log.h>
  16#include <mmc.h>
  17#include <i2c.h>
  18#include <serial.h>
  19#include <spl.h>
  20#include <asm/cache.h>
  21#include <asm/gpio.h>
  22#include <asm/io.h>
  23#include <asm/arch/clock.h>
  24#include <asm/arch/spl.h>
  25#include <asm/arch/sys_proto.h>
  26#include <asm/arch/timer.h>
  27#include <asm/arch/tzpc.h>
  28#include <asm/arch/mmc.h>
  29
  30#include <linux/compiler.h>
  31
  32struct fel_stash {
  33        uint32_t sp;
  34        uint32_t lr;
  35        uint32_t cpsr;
  36        uint32_t sctlr;
  37        uint32_t vbar;
  38        uint32_t cr;
  39};
  40
  41struct fel_stash fel_stash __section(".data");
  42
  43#ifdef CONFIG_ARM64
  44#include <asm/armv8/mmu.h>
  45
  46static struct mm_region sunxi_mem_map[] = {
  47        {
  48                /* SRAM, MMIO regions */
  49                .virt = 0x0UL,
  50                .phys = 0x0UL,
  51                .size = 0x40000000UL,
  52                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  53                         PTE_BLOCK_NON_SHARE
  54        }, {
  55                /* RAM */
  56                .virt = 0x40000000UL,
  57                .phys = 0x40000000UL,
  58                .size = CONFIG_SUNXI_DRAM_MAX_SIZE,
  59                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  60                         PTE_BLOCK_INNER_SHARE
  61        }, {
  62                /* List terminator */
  63                0,
  64        }
  65};
  66struct mm_region *mem_map = sunxi_mem_map;
  67
  68ulong board_get_usable_ram_top(ulong total_size)
  69{
  70        /* Some devices (like the EMAC) have a 32-bit DMA limit. */
  71        if (gd->ram_top > (1ULL << 32))
  72                return 1ULL << 32;
  73
  74        return gd->ram_top;
  75}
  76#endif
  77
  78static int gpio_init(void)
  79{
  80        __maybe_unused uint val;
  81#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  82#if defined(CONFIG_MACH_SUN4I) || \
  83    defined(CONFIG_MACH_SUN7I) || \
  84    defined(CONFIG_MACH_SUN8I_R40)
  85        /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  86        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  87        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  88#endif
  89#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
  90        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  91        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  92#else
  93        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  94        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  95#endif
  96        sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  97#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
  98                                 defined(CONFIG_MACH_SUN7I) || \
  99                                 defined(CONFIG_MACH_SUN8I_R40))
 100        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
 101        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 102        sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 103#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
 104        sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
 105        sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
 106        sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 107#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
 108        sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 109        sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 110        sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 111#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
 112        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
 113        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
 114        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 115#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
 116        sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 117        sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 118        sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
 119#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
 120        sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
 121        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
 122        sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 123#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
 124        sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
 125        sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
 126        sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
 127#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
 128        sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
 129        sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
 130        sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
 131#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
 132        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
 133        sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
 134        sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 135#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
 136        sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
 137        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
 138        sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 139#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 140        sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 141        sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 142        sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 143#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 144        sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 145        sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 146        sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 147#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
 148        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
 149        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
 150        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 151#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
 152        sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
 153        sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 154        sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 155#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
 156                                !defined(CONFIG_MACH_SUN8I_R40)
 157        sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
 158        sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
 159        sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
 160#else
 161#error Unsupported console port number. Please fix pin mux settings in board.c
 162#endif
 163
 164#ifdef CONFIG_SUN50I_GEN_H6
 165        /* Update PIO power bias configuration by copy hardware detected value */
 166        val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 167        writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
 168        val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 169        writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
 170#endif
 171
 172        return 0;
 173}
 174
 175#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
 176static int spl_board_load_image(struct spl_image_info *spl_image,
 177                                struct spl_boot_device *bootdev)
 178{
 179        debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
 180        return_to_fel(fel_stash.sp, fel_stash.lr);
 181
 182        return 0;
 183}
 184SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
 185#endif
 186
 187void s_init(void)
 188{
 189        /*
 190         * Undocumented magic taken from boot0, without this DRAM
 191         * access gets messed up (seems cache related).
 192         * The boot0 sources describe this as: "config ema for cache sram"
 193         */
 194#if defined CONFIG_MACH_SUN6I
 195        setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 196#elif defined CONFIG_MACH_SUN8I
 197        __maybe_unused uint version;
 198
 199        /* Unlock sram version info reg, read it, relock */
 200        setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
 201        version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
 202        clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
 203
 204        /*
 205         * Ideally this would be a switch case, but we do not know exactly
 206         * which versions there are and which version needs which settings,
 207         * so reproduce the per SoC code from the BSP.
 208         */
 209#if defined CONFIG_MACH_SUN8I_A23
 210        if (version == 0x1650)
 211                setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 212        else /* 0x1661 ? */
 213                setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 214#elif defined CONFIG_MACH_SUN8I_A33
 215        if (version != 0x1667)
 216                setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 217#endif
 218        /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
 219        /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 220#endif
 221
 222#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
 223        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 224        asm volatile(
 225                "mrc p15, 0, r0, c1, c0, 1\n"
 226                "orr r0, r0, #1 << 6\n"
 227                "mcr p15, 0, r0, c1, c0, 1\n"
 228                ::: "r0");
 229#endif
 230#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 231        /* Enable non-secure access to some peripherals */
 232        tzpc_init();
 233#endif
 234
 235        clock_init();
 236        timer_init();
 237        gpio_init();
 238#if !CONFIG_IS_ENABLED(DM_I2C)
 239        i2c_init_board();
 240#endif
 241        eth_init_board();
 242}
 243
 244#define SUNXI_INVALID_BOOT_SOURCE       -1
 245
 246static int sunxi_get_boot_source(void)
 247{
 248        if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 249                return SUNXI_INVALID_BOOT_SOURCE;
 250
 251        return readb(SPL_ADDR + 0x28);
 252}
 253
 254/* The sunxi internal brom will try to loader external bootloader
 255 * from mmc0, nand flash, mmc2.
 256 */
 257uint32_t sunxi_get_boot_device(void)
 258{
 259        int boot_source = sunxi_get_boot_source();
 260
 261        /*
 262         * When booting from the SD card or NAND memory, the "eGON.BT0"
 263         * signature is expected to be found in memory at the address 0x0004
 264         * (see the "mksunxiboot" tool, which generates this header).
 265         *
 266         * When booting in the FEL mode over USB, this signature is patched in
 267         * memory and replaced with something else by the 'fel' tool. This other
 268         * signature is selected in such a way, that it can't be present in a
 269         * valid bootable SD card image (because the BROM would refuse to
 270         * execute the SPL in this case).
 271         *
 272         * This checks for the signature and if it is not found returns to
 273         * the FEL code in the BROM to wait and receive the main u-boot
 274         * binary over USB. If it is found, it determines where SPL was
 275         * read from.
 276         */
 277        switch (boot_source) {
 278        case SUNXI_INVALID_BOOT_SOURCE:
 279                return BOOT_DEVICE_BOARD;
 280        case SUNXI_BOOTED_FROM_MMC0:
 281        case SUNXI_BOOTED_FROM_MMC0_HIGH:
 282                return BOOT_DEVICE_MMC1;
 283        case SUNXI_BOOTED_FROM_NAND:
 284                return BOOT_DEVICE_NAND;
 285        case SUNXI_BOOTED_FROM_MMC2:
 286        case SUNXI_BOOTED_FROM_MMC2_HIGH:
 287                return BOOT_DEVICE_MMC2;
 288        case SUNXI_BOOTED_FROM_SPI:
 289                return BOOT_DEVICE_SPI;
 290        }
 291
 292        panic("Unknown boot source %d\n", boot_source);
 293        return -1;              /* Never reached */
 294}
 295
 296#ifdef CONFIG_SPL_BUILD
 297static u32 sunxi_get_spl_size(void)
 298{
 299        if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 300                return 0;
 301
 302        return readl(SPL_ADDR + 0x10);
 303}
 304
 305/*
 306 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
 307 * an eMMC device. The boot source has bit 4 set in the latter case.
 308 * By adding 120KB to the normal offset when booting from a "high" location
 309 * we can support both cases.
 310 * Also U-Boot proper is located at least 32KB after the SPL, but will
 311 * immediately follow the SPL if that is bigger than that.
 312 */
 313unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
 314                                           unsigned long raw_sect)
 315{
 316        unsigned long spl_size = sunxi_get_spl_size();
 317        unsigned long sector;
 318
 319        sector = max(raw_sect, spl_size / 512);
 320
 321        switch (sunxi_get_boot_source()) {
 322        case SUNXI_BOOTED_FROM_MMC0_HIGH:
 323        case SUNXI_BOOTED_FROM_MMC2_HIGH:
 324                sector += (128 - 8) * 2;
 325                break;
 326        }
 327
 328        return sector;
 329}
 330
 331u32 spl_boot_device(void)
 332{
 333        return sunxi_get_boot_device();
 334}
 335
 336void board_init_f(ulong dummy)
 337{
 338        spl_init();
 339        preloader_console_init();
 340
 341#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 342        /* Needed early by sunxi_board_init if PMU is enabled */
 343        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 344#endif
 345        sunxi_board_init();
 346}
 347#endif
 348
 349#if !CONFIG_IS_ENABLED(SYSRESET)
 350void reset_cpu(void)
 351{
 352#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
 353        static const struct sunxi_wdog *wdog =
 354                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 355
 356        /* Set the watchdog for its shortest interval (.5s) and wait */
 357        writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 358        writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 359
 360        while (1) {
 361                /* sun5i sometimes gets stuck without this */
 362                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 363        }
 364#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
 365#if defined(CONFIG_MACH_SUN50I_H6)
 366        /* WDOG is broken for some H6 rev. use the R_WDOG instead */
 367        static const struct sunxi_wdog *wdog =
 368                (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
 369#else
 370        static const struct sunxi_wdog *wdog =
 371                ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 372#endif
 373        /* Set the watchdog for its shortest interval (.5s) and wait */
 374        writel(WDT_CFG_RESET, &wdog->cfg);
 375        writel(WDT_MODE_EN, &wdog->mode);
 376        writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 377        while (1) { }
 378#endif
 379}
 380#endif
 381
 382#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 383void enable_caches(void)
 384{
 385        /* Enable D-cache. I-cache is already enabled in start.S */
 386        dcache_enable();
 387}
 388#endif
 389