LXR uboot/arch/arm/mach-tegra/xusb-padctl-common.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
   7#define _TEGRA_XUSB_PADCTL_COMMON_H_
   8
   9#include <common.h>
  10#include <fdtdec.h>
  11#include <dm/ofnode.h>
  12
  13#include <asm/io.h>
  14#include <asm/arch-tegra/xusb-padctl.h>
  15#include <linux/ioport.h>
  16
  17struct tegra_xusb_padctl_lane {
  18        const char *name;
  19
  20        unsigned int offset;
  21        unsigned int shift;
  22        unsigned int mask;
  23        unsigned int iddq;
  24
  25        const unsigned int *funcs;
  26        unsigned int num_funcs;
  27};
  28
  29struct tegra_xusb_phy_ops {
  30        int (*prepare)(struct tegra_xusb_phy *phy);
  31        int (*enable)(struct tegra_xusb_phy *phy);
  32        int (*disable)(struct tegra_xusb_phy *phy);
  33        int (*unprepare)(struct tegra_xusb_phy *phy);
  34};
  35
  36struct tegra_xusb_phy {
  37        unsigned int type;
  38        const struct tegra_xusb_phy_ops *ops;
  39        struct tegra_xusb_padctl *padctl;
  40};
  41
  42struct tegra_xusb_padctl_pin {
  43        const struct tegra_xusb_padctl_lane *lane;
  44
  45        unsigned int func;
  46        int iddq;
  47};
  48
  49#define MAX_GROUPS 5
  50#define MAX_PINS 7
  51
  52struct tegra_xusb_padctl_group {
  53        const char *name;
  54
  55        const char *pins[MAX_PINS];
  56        unsigned int num_pins;
  57
  58        const char *func;
  59        int iddq;
  60};
  61
  62struct tegra_xusb_padctl_soc {
  63        const struct tegra_xusb_padctl_lane *lanes;
  64        unsigned int num_lanes;
  65        const char *const *functions;
  66        unsigned int num_functions;
  67        struct tegra_xusb_phy *phys;
  68        unsigned int num_phys;
  69};
  70
  71struct tegra_xusb_padctl_config {
  72        const char *name;
  73
  74        struct tegra_xusb_padctl_group groups[MAX_GROUPS];
  75        unsigned int num_groups;
  76};
  77
  78struct tegra_xusb_padctl {
  79        const struct tegra_xusb_padctl_soc *socdata;
  80        struct tegra_xusb_padctl_config config;
  81        struct resource regs;
  82        unsigned int enable;
  83
  84};
  85extern struct tegra_xusb_padctl padctl;
  86
  87static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
  88                               unsigned long offset)
  89{
  90        return readl(padctl->regs.start + offset);
  91}
  92
  93static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
  94                                 u32 value, unsigned long offset)
  95{
  96        writel(value, padctl->regs.start + offset);
  97}
  98
  99int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
 100                             const struct tegra_xusb_padctl_soc *socdata);
 101
 102#endif
 103