LXR uboot/arch/arm/mach-zynq/clk.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   4 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   5 */
   6#include <clk.h>
   7#include <common.h>
   8#include <dm.h>
   9#include <init.h>
  10#include <malloc.h>
  11#include <asm/arch/clk.h>
  12#include <asm/global_data.h>
  13
  14DECLARE_GLOBAL_DATA_PTR;
  15
  16static const char * const clk_names[clk_max] = {
  17        "armpll", "ddrpll", "iopll",
  18        "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  19        "ddr2x", "ddr3x", "dci",
  20        "lqspi", "smc", "pcap", "gem0", "gem1",
  21        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  22        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  23        "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  24        "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  25        "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  26        "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  27        "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  28};
  29
  30/**
  31 * set_cpu_clk_info() - Setup clock information
  32 *
  33 * This function is called from common code after relocation and sets up the
  34 * clock information.
  35 */
  36int set_cpu_clk_info(void)
  37{
  38        struct clk clk;
  39        struct udevice *dev;
  40        ulong rate;
  41        int i, ret;
  42
  43        ret = uclass_get_device_by_driver(UCLASS_CLK,
  44                DM_DRIVER_GET(zynq_clk), &dev);
  45        if (ret)
  46                return ret;
  47
  48        for (i = 0; i < 2; i++) {
  49                clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  50                ret = clk_request(dev, &clk);
  51                if (ret < 0)
  52                        return ret;
  53
  54                rate = clk_get_rate(&clk) / 1000000;
  55                if (i)
  56                        gd->bd->bi_ddr_freq = rate;
  57                else
  58                        gd->bd->bi_arm_freq = rate;
  59
  60                clk_free(&clk);
  61        }
  62        gd->bd->bi_dsp_freq = 0;
  63
  64        return 0;
  65}
  66
  67/**
  68 * soc_clk_dump() - Print clock frequencies
  69 * Returns zero on success
  70 *
  71 * Implementation for the clk dump command.
  72 */
  73int soc_clk_dump(void)
  74{
  75        struct udevice *dev;
  76        int i, ret;
  77
  78        ret = uclass_get_device_by_driver(UCLASS_CLK,
  79                DM_DRIVER_GET(zynq_clk), &dev);
  80        if (ret)
  81                return ret;
  82
  83        printf("clk\t\tfrequency\n");
  84        for (i = 0; i < clk_max; i++) {
  85                const char *name = clk_names[i];
  86                if (name) {
  87                        struct clk clk;
  88                        unsigned long rate;
  89
  90                        clk.id = i;
  91                        ret = clk_request(dev, &clk);
  92                        if (ret < 0)
  93                                return ret;
  94
  95                        rate = clk_get_rate(&clk);
  96
  97                        clk_free(&clk);
  98
  99                        if ((rate == (unsigned long)-ENOSYS) ||
 100                            (rate == (unsigned long)-ENXIO))
 101                                printf("%10s%20s\n", name, "unknown");
 102                        else
 103                                printf("%10s%20lu\n", name, rate);
 104                }
 105        }
 106
 107        return 0;
 108}
 109