1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. 5 */ 6 7#include <common.h> 8#include <asm/io.h> 9#include <asm/arch/sys_proto.h> 10#include <asm/arch/hardware.h> 11 12#ifndef CONFIG_ZYNQ_DDRC_INIT 13void zynq_ddrc_init(void) {} 14#else 15/* Control regsiter bitfield definitions */ 16#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC 17#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 18#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1 19 20/* ECC scrub regsiter definitions */ 21#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7 22#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4 23 24void zynq_ddrc_init(void) 25{ 26 u32 width, ecctype; 27 28 width = readl(&ddrc_base->ddrc_ctrl); 29 width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >> 30 ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT; 31 ecctype = (readl(&ddrc_base->ecc_scrub) & 32 ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK); 33 34 /* ECC is enabled when memory is in 16bit mode and it is enabled */ 35 if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && 36 (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { 37 puts("ECC enabled "); 38 /* 39 * Clear the first 1MB because it is not initialized from 40 * first stage bootloader. To get ECC to work all memory has 41 * been initialized by writing any value. 42 */ 43 /* cppcheck-suppress nullPointer */ 44 memset((void *)0, 0, 1 * 1024 * 1024); 45 } else { 46 puts("ECC disabled "); 47 } 48} 49#endif 50