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6#include <common.h>
7#include <clock_legacy.h>
8#include <log.h>
9#include <asm/global_data.h>
10#include <asm/io.h>
11#include <asm/addrspace.h>
12#include <asm/types.h>
13#include <mach/ar71xx_regs.h>
14#include <mach/ath79.h>
15#include <wait_bit.h>
16
17#define PLL_SRIF_DPLL2_KI_LSB 29
18#define PLL_SRIF_DPLL2_KI_MASK 0x60000000
19#define PLL_SRIF_DPLL2_KI_SET(x) \
20 (((x) << PLL_SRIF_DPLL2_KI_LSB) & PLL_SRIF_DPLL2_KI_MASK)
21#define PLL_SRIF_DPLL2_KD_LSB 25
22#define PLL_SRIF_DPLL2_KD_MASK 0x1e000000
23#define PLL_SRIF_DPLL2_KD_SET(x) \
24 (((x) << PLL_SRIF_DPLL2_KD_LSB) & PLL_SRIF_DPLL2_KD_MASK)
25#define PLL_SRIF_DPLL2_PLL_PWD_LSB 22
26#define PLL_SRIF_DPLL2_PLL_PWD_MASK 0x00400000
27#define PLL_SRIF_DPLL2_PLL_PWD_SET(x) \
28 (((x) << PLL_SRIF_DPLL2_PLL_PWD_LSB) & PLL_SRIF_DPLL2_PLL_PWD_MASK)
29#define PLL_SRIF_DPLL2_OUTDIV_LSB 19
30#define PLL_SRIF_DPLL2_OUTDIV_MASK 0x00380000
31#define PLL_SRIF_DPLL2_OUTDIV_SET(x) \
32 (((x) << PLL_SRIF_DPLL2_OUTDIV_LSB) & PLL_SRIF_DPLL2_OUTDIV_MASK)
33#define PLL_SRIF_DPLL2_PHASE_SHIFT_LSB 12
34#define PLL_SRIF_DPLL2_PHASE_SHIFT_MASK 0x0007f000
35#define PLL_SRIF_DPLL2_PHASE_SHIFT_SET(x) \
36 (((x) << PLL_SRIF_DPLL2_PHASE_SHIFT_LSB) & PLL_SRIF_DPLL2_PHASE_SHIFT_MASK)
37#define CPU_PLL_CONFIG_PLLPWD_LSB 30
38#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
39#define CPU_PLL_CONFIG_PLLPWD_SET(x) \
40 (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
41#define CPU_PLL_CONFIG_OUTDIV_LSB 19
42#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
43#define CPU_PLL_CONFIG_OUTDIV_SET(x) \
44 (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
45#define CPU_PLL_CONFIG_RANGE_LSB 17
46#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
47#define CPU_PLL_CONFIG_RANGE_SET(x) \
48 (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
49#define CPU_PLL_CONFIG_REFDIV_LSB 12
50#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
51#define CPU_PLL_CONFIG_REFDIV_SET(x) \
52 (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
53#define CPU_PLL_CONFIG1_NINT_LSB 18
54#define CPU_PLL_CONFIG1_NINT_MASK 0x07fc0000
55#define CPU_PLL_CONFIG1_NINT_SET(x) \
56 (((x) << CPU_PLL_CONFIG1_NINT_LSB) & CPU_PLL_CONFIG1_NINT_MASK)
57#define CPU_PLL_DITHER1_DITHER_EN_LSB 31
58#define CPU_PLL_DITHER1_DITHER_EN_MASK 0x80000000
59#define CPU_PLL_DITHER1_DITHER_EN_SET(x) \
60 (((x) << CPU_PLL_DITHER1_DITHER_EN_LSB) & CPU_PLL_DITHER1_DITHER_EN_MASK)
61#define CPU_PLL_DITHER1_UPDATE_COUNT_LSB 24
62#define CPU_PLL_DITHER1_UPDATE_COUNT_MASK 0x3f000000
63#define CPU_PLL_DITHER1_UPDATE_COUNT_SET(x) \
64 (((x) << CPU_PLL_DITHER1_UPDATE_COUNT_LSB) & CPU_PLL_DITHER1_UPDATE_COUNT_MASK)
65#define CPU_PLL_DITHER1_NFRAC_STEP_LSB 18
66#define CPU_PLL_DITHER1_NFRAC_STEP_MASK 0x00fc0000
67#define CPU_PLL_DITHER1_NFRAC_STEP_SET(x) \
68 (((x) << CPU_PLL_DITHER1_NFRAC_STEP_LSB) & CPU_PLL_DITHER1_NFRAC_STEP_MASK)
69#define CPU_PLL_DITHER1_NFRAC_MIN_LSB 0
70#define CPU_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
71#define CPU_PLL_DITHER1_NFRAC_MIN_SET(x) \
72 (((x) << CPU_PLL_DITHER1_NFRAC_MIN_LSB) & CPU_PLL_DITHER1_NFRAC_MIN_MASK)
73#define CPU_PLL_DITHER2_NFRAC_MAX_LSB 0
74#define CPU_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
75#define CPU_PLL_DITHER2_NFRAC_MAX_SET(x) \
76 (((x) << CPU_PLL_DITHER2_NFRAC_MAX_LSB) & CPU_PLL_DITHER2_NFRAC_MAX_MASK)
77#define DDR_PLL_CONFIG_PLLPWD_LSB 30
78#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
79#define DDR_PLL_CONFIG_PLLPWD_SET(x) \
80 (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
81#define DDR_PLL_CONFIG_OUTDIV_LSB 23
82#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
83#define DDR_PLL_CONFIG_OUTDIV_SET(x) \
84 (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
85#define DDR_PLL_CONFIG_RANGE_LSB 21
86#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
87#define DDR_PLL_CONFIG_RANGE_SET(x) \
88 (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
89#define DDR_PLL_CONFIG_REFDIV_LSB 16
90#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
91#define DDR_PLL_CONFIG_REFDIV_SET(x) \
92 (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
93#define DDR_PLL_CONFIG1_NINT_LSB 18
94#define DDR_PLL_CONFIG1_NINT_MASK 0x07fc0000
95#define DDR_PLL_CONFIG1_NINT_SET(x) \
96 (((x) << DDR_PLL_CONFIG1_NINT_LSB) & DDR_PLL_CONFIG1_NINT_MASK)
97#define DDR_PLL_DITHER1_DITHER_EN_LSB 31
98#define DDR_PLL_DITHER1_DITHER_EN_MASK 0x80000000
99#define DDR_PLL_DITHER1_DITHER_EN_SET(x) \
100 (((x) << DDR_PLL_DITHER1_DITHER_EN_LSB) & DDR_PLL_DITHER1_DITHER_EN_MASK)
101#define DDR_PLL_DITHER1_UPDATE_COUNT_LSB 27
102#define DDR_PLL_DITHER1_UPDATE_COUNT_MASK 0x78000000
103#define DDR_PLL_DITHER1_UPDATE_COUNT_SET(x) \
104 (((x) << DDR_PLL_DITHER1_UPDATE_COUNT_LSB) & DDR_PLL_DITHER1_UPDATE_COUNT_MASK)
105#define DDR_PLL_DITHER1_NFRAC_STEP_LSB 20
106#define DDR_PLL_DITHER1_NFRAC_STEP_MASK 0x07f00000
107#define DDR_PLL_DITHER1_NFRAC_STEP_SET(x) \
108 (((x) << DDR_PLL_DITHER1_NFRAC_STEP_LSB) & DDR_PLL_DITHER1_NFRAC_STEP_MASK)
109#define DDR_PLL_DITHER1_NFRAC_MIN_LSB 0
110#define DDR_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
111#define DDR_PLL_DITHER1_NFRAC_MIN_SET(x) \
112 (((x) << DDR_PLL_DITHER1_NFRAC_MIN_LSB) & DDR_PLL_DITHER1_NFRAC_MIN_MASK)
113#define DDR_PLL_DITHER2_NFRAC_MAX_LSB 0
114#define DDR_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
115#define DDR_PLL_DITHER2_NFRAC_MAX_SET(x) \
116 (((x) << DDR_PLL_DITHER2_NFRAC_MAX_LSB) & DDR_PLL_DITHER2_NFRAC_MAX_MASK)
117#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
118#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
119#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) \
120 (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
121#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21
122#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000
123#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) \
124 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)
125#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20
126#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000
127#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) \
128 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)
129#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
130#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
131#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) \
132 (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
133#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
134#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
135#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) \
136 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
137#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
138#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
139#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) \
140 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
141#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
142#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
143#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \
144 (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
145#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
146#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
147#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \
148 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
149#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
150#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
151#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) \
152 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
153
154#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1f)
155#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)
156#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)
157#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)
158#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)
159#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \
160 CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \
161 CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \
162 CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
163#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)
164#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)
165#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)
166#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)
167#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)
168#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)
169#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \
170 DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \
171 DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \
172 DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
173#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)
174#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
175#define CPU_AND_DDR_CLK_FROM_DDR \
176 CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)
177#define CPU_AND_DDR_CLK_FROM_CPU \
178 CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)
179#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL \
180 CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)
181#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV \
182 CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
183#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV \
184 CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
185
186static inline void set_val(u32 _reg, u32 _mask, u32 _val)
187{
188 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
189 AR71XX_PLL_SIZE, MAP_NOCACHE);
190 writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg);
191}
192
193#define cpu_pll_set(_mask, _val) \
194 set_val(QCA956X_PLL_CPU_CONFIG_REG, _mask, _val)
195
196#define ddr_pll_set(_mask, _val) \
197 set_val(QCA956X_PLL_DDR_CONFIG_REG, _mask, _val)
198
199#define cpu_ddr_control_set(_mask, _val) \
200 set_val(QCA956X_PLL_CLK_CTRL_REG, _mask, _val)
201
202DECLARE_GLOBAL_DATA_PTR;
203
204static u32 qca956x_get_xtal(void)
205{
206 u32 val;
207
208 val = ath79_get_bootstrap();
209 if (val & QCA956X_BOOTSTRAP_REF_CLK_40)
210 return 40000000;
211 else
212 return 25000000;
213}
214
215int get_serial_clock(void)
216{
217 return qca956x_get_xtal();
218}
219
220void qca956x_pll_init(void)
221{
222 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE,
223 QCA956X_SRIF_SIZE, MAP_NOCACHE);
224 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
225 AR71XX_PLL_SIZE, MAP_NOCACHE);
226
227
228 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
229 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(1) |
230 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG);
231
232
233 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
234 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(3) |
235 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_PCIE_DPLL2_REG);
236
237
238 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
239 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
240 srif_regs + QCA956X_SRIF_DDR_DPLL2_REG);
241
242
243 writel(PLL_SRIF_DPLL2_KI_SET(1) | PLL_SRIF_DPLL2_KD_SET(7) |
244 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
245 srif_regs + QCA956X_SRIF_CPU_DPLL2_REG);
246
247
248 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
249 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
250 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
251 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
252 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
253 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
254
255
256 cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(1));
257 cpu_pll_set(CPU_PLL_CONFIG_REFDIV_MASK, CPU_PLL_CONFIG_REF_DIV_VAL);
258 cpu_pll_set(CPU_PLL_CONFIG_RANGE_MASK, CPU_PLL_CONFIG_RANGE_VAL);
259 cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL1);
260 set_val(QCA956X_PLL_CPU_CONFIG1_REG, CPU_PLL_CONFIG1_NINT_MASK, \
261 CPU_PLL_CONFIG1_NINT_VAL);
262
263
264 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(1));
265 ddr_pll_set(DDR_PLL_CONFIG_REFDIV_MASK, DDR_PLL_CONFIG_REF_DIV_VAL);
266 ddr_pll_set(DDR_PLL_CONFIG_RANGE_MASK, DDR_PLL_CONFIG_RANGE_VAL);
267 ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL1);
268 set_val(QCA956X_PLL_DDR_CONFIG1_REG, DDR_PLL_CONFIG1_NINT_MASK,
269 DDR_PLL_CONFIG1_NINT_VAL);
270
271
272 writel(CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | AHB_CLK_FROM_DDR |
273 CPU_AND_DDR_CLK_FROM_DDR | CPU_AND_DDR_CLK_FROM_CPU |
274 CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV |
275 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) |
276 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) |
277 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG);
278
279
280 writel(DDR_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_DDR_DIT_FRAC_REG);
281 writel(DDR_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_DDR_DIT2_FRAC_REG);
282
283
284 writel(CPU_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_CPU_DIT_FRAC_REG);
285 writel(CPU_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_CPU_DIT2_FRAC_REG);
286
287
288 cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0));
289 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0));
290
291
292 cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2);
293 ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2);
294
295
296 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
297 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
298 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
299 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
300 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
301 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
302
303 while (readl(pll_regs + QCA956X_PLL_CPU_CONFIG_REG) & 0x8000000)
304 ;
305
306 while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000)
307 ;
308}
309
310int get_clocks(void)
311{
312 void __iomem *regs;
313 u32 ref_rate, cpu_rate, ddr_rate, ahb_rate;
314 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl;
315 u32 pll, cpu_pll, ddr_pll, misc;
316
317
318
319
320
321 regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
322 MAP_NOCACHE);
323 misc = readl(regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
324 misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
325 writel(misc, regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
326
327 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
328 MAP_NOCACHE);
329 pll = readl(regs + QCA956X_PLL_CPU_CONFIG_REG);
330 out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
331 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
332 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
333 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
334
335 pll = readl(regs + QCA956X_PLL_CPU_CONFIG1_REG);
336 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
337 QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
338 hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
339 QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
340 lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
341 QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
342
343 ref_rate = qca956x_get_xtal();
344
345 cpu_pll = nint * ref_rate / ref_div;
346 cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
347 cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
348 cpu_pll /= (1 << out_div);
349
350 pll = readl(regs + QCA956X_PLL_DDR_CONFIG_REG);
351 out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
352 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
353 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
354 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
355 pll = readl(regs + QCA956X_PLL_DDR_CONFIG1_REG);
356 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
357 QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
358 hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
359 QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
360 lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
361 QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
362
363 ddr_pll = nint * ref_rate / ref_div;
364 ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
365 ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
366 ddr_pll /= (1 << out_div);
367
368 clk_ctrl = readl(regs + QCA956X_PLL_CLK_CTRL_REG);
369
370 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
371 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
372
373 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
374 cpu_rate = ref_rate;
375 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
376 cpu_rate = ddr_pll / (postdiv + 1);
377 else
378 cpu_rate = cpu_pll / (postdiv + 1);
379
380 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
381 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
382
383 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
384 ddr_rate = ref_rate;
385 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
386 ddr_rate = cpu_pll / (postdiv + 1);
387 else
388 ddr_rate = ddr_pll / (postdiv + 1);
389
390 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
391 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
392
393 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
394 ahb_rate = ref_rate;
395 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
396 ahb_rate = ddr_pll / (postdiv + 1);
397 else
398 ahb_rate = cpu_pll / (postdiv + 1);
399
400 gd->cpu_clk = cpu_rate;
401 gd->mem_clk = ddr_rate;
402 gd->bus_clk = ahb_rate;
403
404 debug("cpu_clk=%u, ddr_clk=%u, bus_clk=%u\n",
405 cpu_rate, ddr_rate, ahb_rate);
406
407 return 0;
408}
409
410ulong get_bus_freq(ulong dummy)
411{
412 if (!gd->bus_clk)
413 get_clocks();
414 return gd->bus_clk;
415}
416
417ulong get_ddr_freq(ulong dummy)
418{
419 if (!gd->mem_clk)
420 get_clocks();
421 return gd->mem_clk;
422}
423
