1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * JZ4780 timer 4 * 5 * Copyright (c) 2013 Imagination Technologies 6 * Author: Paul Burton <paul.burton@imgtec.com> 7 */ 8 9#include <config.h> 10#include <common.h> 11#include <div64.h> 12#include <init.h> 13#include <irq_func.h> 14#include <time.h> 15#include <asm/io.h> 16#include <asm/mipsregs.h> 17#include <linux/bitops.h> 18#include <linux/delay.h> 19#include <mach/jz4780.h> 20 21#define TCU_TSR 0x1C /* Timer Stop Register */ 22#define TCU_TSSR 0x2C /* Timer Stop Set Register */ 23#define TCU_TSCR 0x3C /* Timer Stop Clear Register */ 24#define TCU_TER 0x10 /* Timer Counter Enable Register */ 25#define TCU_TESR 0x14 /* Timer Counter Enable Set Register */ 26#define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */ 27#define TCU_TFR 0x20 /* Timer Flag Register */ 28#define TCU_TFSR 0x24 /* Timer Flag Set Register */ 29#define TCU_TFCR 0x28 /* Timer Flag Clear Register */ 30#define TCU_TMR 0x30 /* Timer Mask Register */ 31#define TCU_TMSR 0x34 /* Timer Mask Set Register */ 32#define TCU_TMCR 0x38 /* Timer Mask Clear Register */ 33/* n = 0,1,2,3,4,5 */ 34#define TCU_TDFR(n) (0x40 + (n) * 0x10) /* Timer Data Full Reg */ 35#define TCU_TDHR(n) (0x44 + (n) * 0x10) /* Timer Data Half Reg */ 36#define TCU_TCNT(n) (0x48 + (n) * 0x10) /* Timer Counter Reg */ 37#define TCU_TCSR(n) (0x4C + (n) * 0x10) /* Timer Control Reg */ 38 39#define TCU_OSTCNTL 0xe4 40#define TCU_OSTCNTH 0xe8 41#define TCU_OSTCSR 0xec 42#define TCU_OSTCNTHBUF 0xfc 43 44/* Register definitions */ 45#define TCU_TCSR_PWM_SD BIT(9) 46#define TCU_TCSR_PWM_INITL_HIGH BIT(8) 47#define TCU_TCSR_PWM_EN BIT(7) 48#define TCU_TCSR_PRESCALE_BIT 3 49#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 50#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 51#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 52#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 53#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 54#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 55#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 56#define TCU_TCSR_EXT_EN BIT(2) 57#define TCU_TCSR_RTC_EN BIT(1) 58#define TCU_TCSR_PCK_EN BIT(0) 59 60#define TCU_TER_TCEN5 BIT(5) 61#define TCU_TER_TCEN4 BIT(4) 62#define TCU_TER_TCEN3 BIT(3) 63#define TCU_TER_TCEN2 BIT(2) 64#define TCU_TER_TCEN1 BIT(1) 65#define TCU_TER_TCEN0 BIT(0) 66 67#define TCU_TESR_TCST5 BIT(5) 68#define TCU_TESR_TCST4 BIT(4) 69#define TCU_TESR_TCST3 BIT(3) 70#define TCU_TESR_TCST2 BIT(2) 71#define TCU_TESR_TCST1 BIT(1) 72#define TCU_TESR_TCST0 BIT(0) 73 74#define TCU_TECR_TCCL5 BIT(5) 75#define TCU_TECR_TCCL4 BIT(4) 76#define TCU_TECR_TCCL3 BIT(3) 77#define TCU_TECR_TCCL2 BIT(2) 78#define TCU_TECR_TCCL1 BIT(1) 79#define TCU_TECR_TCCL0 BIT(0) 80 81#define TCU_TFR_HFLAG5 BIT(21) 82#define TCU_TFR_HFLAG4 BIT(20) 83#define TCU_TFR_HFLAG3 BIT(19) 84#define TCU_TFR_HFLAG2 BIT(18) 85#define TCU_TFR_HFLAG1 BIT(17) 86#define TCU_TFR_HFLAG0 BIT(16) 87#define TCU_TFR_FFLAG5 BIT(5) 88#define TCU_TFR_FFLAG4 BIT(4) 89#define TCU_TFR_FFLAG3 BIT(3) 90#define TCU_TFR_FFLAG2 BIT(2) 91#define TCU_TFR_FFLAG1 BIT(1) 92#define TCU_TFR_FFLAG0 BIT(0) 93 94#define TCU_TFSR_HFLAG5 BIT(21) 95#define TCU_TFSR_HFLAG4 BIT(20) 96#define TCU_TFSR_HFLAG3 BIT(19) 97#define TCU_TFSR_HFLAG2 BIT(18) 98#define TCU_TFSR_HFLAG1 BIT(17) 99#define TCU_TFSR_HFLAG0 BIT(16) 100#define TCU_TFSR_FFLAG5 BIT(5) 101#define TCU_TFSR_FFLAG4 BIT(4) 102#define TCU_TFSR_FFLAG3 BIT(3) 103#define TCU_TFSR_FFLAG2 BIT(2) 104#define TCU_TFSR_FFLAG1 BIT(1) 105#define TCU_TFSR_FFLAG0 BIT(0) 106 107#define TCU_TFCR_HFLAG5 BIT(21) 108#define TCU_TFCR_HFLAG4 BIT(20) 109#define TCU_TFCR_HFLAG3 BIT(19) 110#define TCU_TFCR_HFLAG2 BIT(18) 111#define TCU_TFCR_HFLAG1 BIT(17) 112#define TCU_TFCR_HFLAG0 BIT(16) 113#define TCU_TFCR_FFLAG5 BIT(5) 114#define TCU_TFCR_FFLAG4 BIT(4) 115#define TCU_TFCR_FFLAG3 BIT(3) 116#define TCU_TFCR_FFLAG2 BIT(2) 117#define TCU_TFCR_FFLAG1 BIT(1) 118#define TCU_TFCR_FFLAG0 BIT(0) 119 120#define TCU_TMR_HMASK5 BIT(21) 121#define TCU_TMR_HMASK4 BIT(20) 122#define TCU_TMR_HMASK3 BIT(19) 123#define TCU_TMR_HMASK2 BIT(18) 124#define TCU_TMR_HMASK1 BIT(17) 125#define TCU_TMR_HMASK0 BIT(16) 126#define TCU_TMR_FMASK5 BIT(5) 127#define TCU_TMR_FMASK4 BIT(4) 128#define TCU_TMR_FMASK3 BIT(3) 129#define TCU_TMR_FMASK2 BIT(2) 130#define TCU_TMR_FMASK1 BIT(1) 131#define TCU_TMR_FMASK0 BIT(0) 132 133#define TCU_TMSR_HMST5 BIT(21) 134#define TCU_TMSR_HMST4 BIT(20) 135#define TCU_TMSR_HMST3 BIT(19) 136#define TCU_TMSR_HMST2 BIT(18) 137#define TCU_TMSR_HMST1 BIT(17) 138#define TCU_TMSR_HMST0 BIT(16) 139#define TCU_TMSR_FMST5 BIT(5) 140#define TCU_TMSR_FMST4 BIT(4) 141#define TCU_TMSR_FMST3 BIT(3) 142#define TCU_TMSR_FMST2 BIT(2) 143#define TCU_TMSR_FMST1 BIT(1) 144#define TCU_TMSR_FMST0 BIT(0) 145 146#define TCU_TMCR_HMCL5 BIT(21) 147#define TCU_TMCR_HMCL4 BIT(20) 148#define TCU_TMCR_HMCL3 BIT(19) 149#define TCU_TMCR_HMCL2 BIT(18) 150#define TCU_TMCR_HMCL1 BIT(17) 151#define TCU_TMCR_HMCL0 BIT(16) 152#define TCU_TMCR_FMCL5 BIT(5) 153#define TCU_TMCR_FMCL4 BIT(4) 154#define TCU_TMCR_FMCL3 BIT(3) 155#define TCU_TMCR_FMCL2 BIT(2) 156#define TCU_TMCR_FMCL1 BIT(1) 157#define TCU_TMCR_FMCL0 BIT(0) 158 159#define TCU_TSR_WDTS BIT(16) 160#define TCU_TSR_STOP5 BIT(5) 161#define TCU_TSR_STOP4 BIT(4) 162#define TCU_TSR_STOP3 BIT(3) 163#define TCU_TSR_STOP2 BIT(2) 164#define TCU_TSR_STOP1 BIT(1) 165#define TCU_TSR_STOP0 BIT(0) 166 167#define TCU_TSSR_WDTSS BIT(16) 168#define TCU_TSSR_STPS5 BIT(5) 169#define TCU_TSSR_STPS4 BIT(4) 170#define TCU_TSSR_STPS3 BIT(3) 171#define TCU_TSSR_STPS2 BIT(2) 172#define TCU_TSSR_STPS1 BIT(1) 173#define TCU_TSSR_STPS0 BIT(0) 174 175#define TCU_TSSR_WDTSC BIT(16) 176#define TCU_TSSR_STPC5 BIT(5) 177#define TCU_TSSR_STPC4 BIT(4) 178#define TCU_TSSR_STPC3 BIT(3) 179#define TCU_TSSR_STPC2 BIT(2) 180#define TCU_TSSR_STPC1 BIT(1) 181#define TCU_TSSR_STPC0 BIT(0) 182 183#define TER_OSTEN BIT(15) 184 185#define OSTCSR_CNT_MD BIT(15) 186#define OSTCSR_SD BIT(9) 187#define OSTCSR_PRESCALE_16 (0x2 << 3) 188#define OSTCSR_EXT_EN BIT(2) 189 190int timer_init(void) 191{ 192 void __iomem *regs = (void __iomem *)TCU_BASE; 193 194 writel(OSTCSR_SD, regs + TCU_OSTCSR); 195 reset_timer(); 196 writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16, 197 regs + TCU_OSTCSR); 198 writew(TER_OSTEN, regs + TCU_TESR); 199 return 0; 200} 201 202void reset_timer(void) 203{ 204 void __iomem *regs = (void __iomem *)TCU_BASE; 205 206 writel(0, regs + TCU_OSTCNTH); 207 writel(0, regs + TCU_OSTCNTL); 208} 209 210static u64 get_timer64(void) 211{ 212 void __iomem *regs = (void __iomem *)TCU_BASE; 213 u32 low = readl(regs + TCU_OSTCNTL); 214 u32 high = readl(regs + TCU_OSTCNTHBUF); 215 216 return ((u64)high << 32) | low; 217} 218 219ulong get_timer(ulong base) 220{ 221 return lldiv(get_timer64(), 3000) - base; 222} 223 224void __udelay(unsigned long usec) 225{ 226 /* OST count increments at 3MHz */ 227 u64 end = get_timer64() + ((u64)usec * 3); 228 229 while (get_timer64() < end) 230 ; 231} 232 233unsigned long long get_ticks(void) 234{ 235 return get_timer64(); 236} 237 238void jz4780_tcu_wdt_start(void) 239{ 240 void __iomem *tcu_regs = (void __iomem *)TCU_BASE; 241 242 /* Enable WDT clock */ 243 writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR); 244} 245