LXR uboot/arch/mips/mach-mscc/include/mach/tlb.h

   1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#ifndef __ASM_MACH_TLB_H
   7#define __ASM_MACH_TLB_H
   8
   9#include <asm/mipsregs.h>
  10#include <linux/bitops.h>
  11#include <mach/common.h>
  12#include <linux/sizes.h>
  13
  14#define TLB_HI_MASK      0xffffe000
  15#define TLB_LO_MASK      0x3fffffff     /* Masks off Fill bits */
  16#define TLB_LO_SHIFT     6      /* PFN Start bit */
  17
  18#define PAGEMASK_SHIFT   13
  19
  20#define MMU_PAGE_CACHED   (3 << 3)      /* C(5:3) Cache Coherency Attributes */
  21#define MMU_PAGE_UNCACHED (2 << 3)      /* C(5:3) Cache Coherency Attributes */
  22#define MMU_PAGE_DIRTY    BIT(2)        /* = Writeable */
  23#define MMU_PAGE_VALID    BIT(1)
  24#define MMU_PAGE_GLOBAL   BIT(0)
  25#define MMU_REGIO_RO_C    (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
  26#define MMU_REGIO_RO      (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
  27#define MMU_REGIO_RW      (MMU_PAGE_DIRTY | MMU_REGIO_RO)
  28#define MMU_REGIO_INVAL   (MMU_PAGE_GLOBAL)
  29
  30#define TLB_COUNT_MASK    GENMASK(5, 0)
  31#define TLB_COUNT_OFF     25
  32
  33static inline u32 get_tlb_count(void)
  34{
  35        register u32 config1;
  36
  37        config1 = read_c0_config1();
  38        config1 >>= TLB_COUNT_OFF;
  39        config1 &= TLB_COUNT_MASK;
  40
  41        return 1 + config1;
  42}
  43
  44static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1,
  45                              u32 tlb_attrib2)
  46{
  47        register u32 tlb_mask, tlb_lo0, tlb_lo1;
  48
  49        tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT;
  50        tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT);
  51        tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT);
  52
  53        write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK,
  54                      tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK);
  55}
  56#endif                          /* __ASM_MACH_TLB_H */
  57