1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) address and type definitions for 6 * Octoen. 7 */ 8 9#ifndef __CVMX_CSR_H__ 10#define __CVMX_CSR_H__ 11 12#include "cvmx-csr-enums.h" 13#include "cvmx-pip-defs.h" 14 15typedef cvmx_pip_prt_cfgx_t cvmx_pip_port_cfg_t; 16 17/* The CSRs for bootbus region zero used to be independent of the 18 other 1-7. As of SDK 1.7.0 these were combined. These macros 19 are for backwards compactability */ 20#define CVMX_MIO_BOOT_REG_CFG0 CVMX_MIO_BOOT_REG_CFGX(0) 21#define CVMX_MIO_BOOT_REG_TIM0 CVMX_MIO_BOOT_REG_TIMX(0) 22 23/* The CN3XXX and CN58XX chips used to not have a LMC number 24 passed to the address macros. These are here to supply backwards 25 compatibility with old code. Code should really use the new addresses 26 with bus arguments for support on other chips */ 27#define CVMX_LMC_BIST_CTL CVMX_LMCX_BIST_CTL(0) 28#define CVMX_LMC_BIST_RESULT CVMX_LMCX_BIST_RESULT(0) 29#define CVMX_LMC_COMP_CTL CVMX_LMCX_COMP_CTL(0) 30#define CVMX_LMC_CTL CVMX_LMCX_CTL(0) 31#define CVMX_LMC_CTL1 CVMX_LMCX_CTL1(0) 32#define CVMX_LMC_DCLK_CNT_HI CVMX_LMCX_DCLK_CNT_HI(0) 33#define CVMX_LMC_DCLK_CNT_LO CVMX_LMCX_DCLK_CNT_LO(0) 34#define CVMX_LMC_DCLK_CTL CVMX_LMCX_DCLK_CTL(0) 35#define CVMX_LMC_DDR2_CTL CVMX_LMCX_DDR2_CTL(0) 36#define CVMX_LMC_DELAY_CFG CVMX_LMCX_DELAY_CFG(0) 37#define CVMX_LMC_DLL_CTL CVMX_LMCX_DLL_CTL(0) 38#define CVMX_LMC_DUAL_MEMCFG CVMX_LMCX_DUAL_MEMCFG(0) 39#define CVMX_LMC_ECC_SYND CVMX_LMCX_ECC_SYND(0) 40#define CVMX_LMC_FADR CVMX_LMCX_FADR(0) 41#define CVMX_LMC_IFB_CNT_HI CVMX_LMCX_IFB_CNT_HI(0) 42#define CVMX_LMC_IFB_CNT_LO CVMX_LMCX_IFB_CNT_LO(0) 43#define CVMX_LMC_MEM_CFG0 CVMX_LMCX_MEM_CFG0(0) 44#define CVMX_LMC_MEM_CFG1 CVMX_LMCX_MEM_CFG1(0) 45#define CVMX_LMC_OPS_CNT_HI CVMX_LMCX_OPS_CNT_HI(0) 46#define CVMX_LMC_OPS_CNT_LO CVMX_LMCX_OPS_CNT_LO(0) 47#define CVMX_LMC_PLL_BWCTL CVMX_LMCX_PLL_BWCTL(0) 48#define CVMX_LMC_PLL_CTL CVMX_LMCX_PLL_CTL(0) 49#define CVMX_LMC_PLL_STATUS CVMX_LMCX_PLL_STATUS(0) 50#define CVMX_LMC_READ_LEVEL_CTL CVMX_LMCX_READ_LEVEL_CTL(0) 51#define CVMX_LMC_READ_LEVEL_DBG CVMX_LMCX_READ_LEVEL_DBG(0) 52#define CVMX_LMC_READ_LEVEL_RANKX CVMX_LMCX_READ_LEVEL_RANKX(0) 53#define CVMX_LMC_RODT_COMP_CTL CVMX_LMCX_RODT_COMP_CTL(0) 54#define CVMX_LMC_RODT_CTL CVMX_LMCX_RODT_CTL(0) 55#define CVMX_LMC_WODT_CTL CVMX_LMCX_WODT_CTL0(0) 56#define CVMX_LMC_WODT_CTL0 CVMX_LMCX_WODT_CTL0(0) 57#define CVMX_LMC_WODT_CTL1 CVMX_LMCX_WODT_CTL1(0) 58 59/* The CN3XXX and CN58XX chips used to not have a TWSI bus number 60 passed to the address macros. These are here to supply backwards 61 compatibility with old code. Code should really use the new addresses 62 with bus arguments for support on other chips */ 63#define CVMX_MIO_TWS_INT CVMX_MIO_TWSX_INT(0) 64#define CVMX_MIO_TWS_SW_TWSI CVMX_MIO_TWSX_SW_TWSI(0) 65#define CVMX_MIO_TWS_SW_TWSI_EXT CVMX_MIO_TWSX_SW_TWSI_EXT(0) 66#define CVMX_MIO_TWS_TWSI_SW CVMX_MIO_TWSX_TWSI_SW(0) 67 68/* The CN3XXX and CN58XX chips used to not have a SMI/MDIO bus number 69 passed to the address macros. These are here to supply backwards 70 compatibility with old code. Code should really use the new addresses 71 with bus arguments for support on other chips */ 72#define CVMX_SMI_CLK CVMX_SMIX_CLK(0) 73#define CVMX_SMI_CMD CVMX_SMIX_CMD(0) 74#define CVMX_SMI_EN CVMX_SMIX_EN(0) 75#define CVMX_SMI_RD_DAT CVMX_SMIX_RD_DAT(0) 76#define CVMX_SMI_WR_DAT CVMX_SMIX_WR_DAT(0) 77 78#endif /* __CVMX_CSR_H__ */ 79