1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Helper functions to abstract board specific data about 6 * network ports from the rest of the cvmx-helper files. 7 */ 8 9#ifndef __CVMX_HELPER_BOARD_H__ 10#define __CVMX_HELPER_BOARD_H__ 11 12#define CVMX_VSC7224_NAME_LEN 16 13 14typedef enum { 15 USB_CLOCK_TYPE_REF_12, 16 USB_CLOCK_TYPE_REF_24, 17 USB_CLOCK_TYPE_REF_48, 18 USB_CLOCK_TYPE_CRYSTAL_12, 19} cvmx_helper_board_usb_clock_types_t; 20 21typedef enum cvmx_phy_type { 22 BROADCOM_GENERIC_PHY, 23 MARVELL_GENERIC_PHY, 24 CORTINA_PHY, /** Now Inphi */ 25 AQUANTIA_PHY, 26 GENERIC_8023_C22_PHY, 27 GENERIC_8023_C45_PHY, 28 INBAND_PHY, 29 QUALCOMM_S17, /** Qualcomm QCA833X switch */ 30 VITESSE_VSC8490_PHY, /** Vitesse VSC8490 is non-standard for SGMII */ 31 FAKE_PHY, /** Unsupported or no PHY, use GPIOs for LEDs */ 32} cvmx_phy_type_t; 33 34/** Used to record the host mode used by the Cortina CS4321 PHY */ 35typedef enum { 36 CVMX_PHY_HOST_MODE_UNKNOWN, 37 CVMX_PHY_HOST_MODE_SGMII, 38 CVMX_PHY_HOST_MODE_QSGMII, 39 CVMX_PHY_HOST_MODE_XAUI, 40 CVMX_PHY_HOST_MODE_RXAUI, 41} cvmx_phy_host_mode_t; 42 43typedef enum { 44 set_phy_link_flags_autoneg = 0x1, 45 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, 46 set_phy_link_flags_flow_control_enable = 0x1 << 1, 47 set_phy_link_flags_flow_control_disable = 0x2 << 1, 48 set_phy_link_flags_flow_control_mask = 0x3 << 1, 49} cvmx_helper_board_set_phy_link_flags_types_t; 50 51/** 52 * The EBB6600 board uses a MDIO mux device to select between the two QLM 53 * modules since both QLM modules share the same PHY addresses. The 54 * MDIO mux is controlled via GPIO by a GPIO device that is also on 55 * the TWSI bus rather than native OCTEON GPIO libes. 56 * 57 * To further complicate matters, the TWSI GPIO device sits behind 58 * a TWSI mux device as well, making accessing the MDIO devices on 59 * this board a very complex operation involving writing to the TWSI mux, 60 * followed by the MDIO mux device. 61 */ 62/** Maximum number of GPIO devices used to control the MDIO mux */ 63#define CVMX_PHY_MUX_MAX_GPIO 2 64 65/** Type of MDIO mux device, currently OTHER isn't supported */ 66typedef enum { 67 SN74CBTLV3253, /** SN74CBTLV3253 I2C device */ 68 OTHER /** Unknown/other */ 69} cvmx_phy_mux_type_t; 70 71/** Type of GPIO line controlling MDIO mux */ 72typedef enum { 73 GPIO_OCTEON, /** Native OCTEON */ 74 GPIO_PCA8574 /** TWSI mux device */ 75} cvmx_phy_gpio_type_t; 76 77/* Forward declarations */ 78struct cvmx_fdt_sfp_info; /** Defined in cvmx-helper-fdt.h */ 79struct cvmx_vsc7224; 80struct cvmx_fdt_gpio_info; /** Defined in cvmx-helper-fdt.h */ 81struct cvmx_fdt_i2c_bus_info; /** Defined in cvmx-helper-fdt.h */ 82struct cvmx_phy_info; 83struct cvmx_fdt_i2c_bus_info; 84struct cvmx_fdt_gpio_info; 85struct cvmx_fdt_gpio_led; 86 87/** 88 * @INTERNAL 89 * This data structure is used when the port LEDs are wired up to Octeon's GPIO 90 * lines instead of to a traditional PHY. 91 */ 92struct cvmx_phy_gpio_leds { 93 struct cvmx_phy_gpio_leds *next; /** For when ports are grouped together */ 94 u64 last_rx_count; /** Counters used to check for activity */ 95 u64 last_tx_count; /** Counters used to check for activity */ 96 u64 last_activity_poll_time; /** Last time activity was polled */ 97 u64 last_link_poll_time; /** Last time link was polled */ 98 int of_offset; 99 int link_poll_interval_ms; /** Link polling interval in ms */ 100 int activity_poll_interval_ms; /** Activity polling interval in ms */ 101 struct cvmx_fdt_gpio_led *link_status; 102 struct cvmx_fdt_gpio_led *error; 103 struct cvmx_fdt_gpio_led *rx_activity; 104 struct cvmx_fdt_gpio_led *tx_activity; 105 struct cvmx_fdt_gpio_led *identify; 106 107 struct cvmx_fdt_gpio_info *link_status_gpio; 108 struct cvmx_fdt_gpio_info *error_gpio; 109 /** Type of GPIO for error LED */ 110 /** If GPIO expander, describe the bus to the expander */ 111 struct cvmx_fdt_gpio_info *rx_activity_gpio; 112 struct cvmx_fdt_gpio_info *tx_activity_gpio; 113 114 u16 rx_activity_hz; /** RX activity blink time in hz */ 115 u16 tx_activity_hz; /** TX activity blink time in hz */ 116 /** 117 * Set if activity and/or link is using an Inphi/Cortina CS4343 or 118 * compatible phy that requires software assistance. NULL if not used. 119 */ 120 bool link_status_active_low; /** True if active link is active low */ 121 bool error_status_active_low; /** True if error LED is active low */ 122 bool error_active_low; /** True if error is active low */ 123 bool rx_activity_active_low; /** True if rx activity is active low */ 124 bool tx_activity_active_low; /** True if tx activity is active low */ 125 /** Set true if LEDs are shared on an interface by all ports */ 126 bool interface_leds; 127 int8_t rx_gpio_timer; /** GPIO clock generator timer [0-3] */ 128 int8_t tx_gpio_timer; /** GPIO clock generator timer [0-3] */ 129 130 /** True if LOS signal activates error LED */ 131 bool los_generate_error; 132 /** True if the error LED is hooked up to a GPIO expander */ 133 bool error_gpio_expander; 134 /** True if the link and RX activity LEDs are shared */ 135 bool link_and_rx_activity_shared; 136 /** True if the link and TX activity LEDs are shared */ 137 bool link_and_tx_activity_shared; 138 /** True if the RX activity and TX activity LEDs are shared */ 139 bool rx_and_tx_activity_shared; 140 /** True if link is driven directly by the hardware */ 141 bool link_led_hw_link; 142 bool error_lit; /** True if ERROR LED is lit */ 143 bool quad_sfp_mode; /** True if using four SFPs for XLAUI */ 144 /** User-defined function to update the link LED */ 145 void (*update_link_led)(int xiface, int index, cvmx_helper_link_info_t result); 146 /** User-defined function to update the rx activity LED */ 147 void (*update_rx_activity_led)(struct cvmx_phy_gpio_leds *led, int xiface, int index, 148 bool check_time); 149}; 150 151/** This structure contains the tap values to use for various cable lengths */ 152struct cvmx_vsc7224_tap { 153 u16 len; /** Starting cable length for tap values */ 154 u16 main_tap; /** Main tap value to use */ 155 u16 pre_tap; /** Pre-tap value to use */ 156 u16 post_tap; /** Post-tap value to use */ 157}; 158 159/** Data structure for Microsemi VSC7224 channel */ 160struct cvmx_vsc7224_chan { 161 struct cvmx_vsc7224_chan *next, *prev; /** Used for linking */ 162 int ipd_port; /** IPD port this channel belongs to */ 163 int xiface; /** xinterface of SFP */ 164 int index; /** Port index of SFP */ 165 int lane; /** Lane on port */ 166 int of_offset; /** Offset of channel info in dt */ 167 bool is_tx; /** True if is transmit channel */ 168 bool maintap_disable; /** True to disable the main tap */ 169 bool pretap_disable; /** True to disable pre-tap */ 170 bool posttap_disable; /** True to disable post-tap */ 171 int num_taps; /** Number of tap values */ 172 /** (Q)SFP attached to this channel */ 173 struct cvmx_fdt_sfp_info *sfp_info; 174 struct cvmx_vsc7224 *vsc7224; /** Pointer to parent */ 175 /** Tap values for various lengths, must be at the end */ 176 struct cvmx_vsc7224_tap taps[0]; 177}; 178 179/** Data structure for Microsemi VSC7224 reclocking chip */ 180struct cvmx_vsc7224 { 181 const char *name; /** Name */ 182 /** Pointer to cannel data */ 183 struct cvmx_vsc7224_chan *channel[4]; 184 /** I2C bus device is connected to */ 185 struct cvmx_fdt_i2c_bus_info *i2c_bus; 186 /** Address of VSC7224 on i2c bus */ 187 int i2c_addr; 188 struct cvmx_fdt_gpio_info *los_gpio; /** LoS GPIO pin */ 189 struct cvmx_fdt_gpio_info *reset_gpio; /** Reset GPIO pin */ 190 int of_offset; /** Offset in device tree */ 191}; 192 193/** Data structure for Avago AVSP5410 gearbox phy */ 194struct cvmx_avsp5410 { 195 const char *name; /** Name */ 196 /** I2C bus device is connected to */ 197 struct cvmx_fdt_i2c_bus_info *i2c_bus; 198 /** Address of AVSP5410 on i2c bus */ 199 int i2c_addr; 200 int of_offset; /** Offset in device tree */ 201 int ipd_port; /** IPD port this phy belongs to */ 202 int xiface; /** xinterface of SFP */ 203 int index; /** Port index of SFP */ 204 u64 prev_temp; /** Previous temparature recorded on Phy Core */ 205 u64 prev_temp_mins; /** Mininutes when the prev temp check is done */ 206 /** (Q)SFP attached to this phy */ 207 struct cvmx_fdt_sfp_info *sfp_info; 208}; 209 210struct cvmx_cs4343_info; 211 212/** 213 * @INTERNAL 214 * 215 * Data structure containing Inphi CS4343 slice information 216 */ 217struct cvmx_cs4343_slice_info { 218 const char *name; /** Name of this slice in device tree */ 219 struct cvmx_cs4343_info *mphy; /** Pointer to mphy cs4343 */ 220 struct cvmx_phy_info *phy_info; 221 int of_offset; /** Offset in device tree */ 222 int slice_no; /** Slice number */ 223 int reg_offset; /** Offset for this slice */ 224 u16 sr_stx_cmode_res; /** See Rainier device tree */ 225 u16 sr_stx_drv_lower_cm; /** See Rainier device tree */ 226 u16 sr_stx_level; /** See Rainier device tree */ 227 u16 sr_stx_pre_peak; /** See Rainier device tree */ 228 u16 sr_stx_muxsubrate_sel; /** See Rainier device tree */ 229 u16 sr_stx_post_peak; /** See Rainier device tree */ 230 u16 cx_stx_cmode_res; /** See Rainier device tree */ 231 u16 cx_stx_drv_lower_cm; /** See Rainier device tree */ 232 u16 cx_stx_level; /** See Rainier device tree */ 233 u16 cx_stx_pre_peak; /** See Rainier device tree */ 234 u16 cx_stx_muxsubrate_sel; /** See Rainier device tree */ 235 u16 cx_stx_post_peak; /** See Rainier device tree */ 236 u16 basex_stx_cmode_res; /** See Rainier device tree */ 237 u16 basex_stx_drv_lower_cm; /** See Rainier device tree */ 238 u16 basex_stx_level; /** See Rainier device tree */ 239 u16 basex_stx_pre_peak; /** See Rainier device tree */ 240 u16 basex_stx_muxsubrate_sel; /** See Rainier device tree */ 241 u16 basex_stx_post_peak; /** See Rainier device tree */ 242 int link_gpio; /** Link LED gpio pin number, -1 if none */ 243 int error_gpio; /** Error LED GPIO pin or -1 if none */ 244 int los_gpio; /** LoS input GPIO or -1 if none */ 245 bool los_inverted; /** True if LoS input is inverted */ 246 bool link_inverted; /** True if link output is inverted */ 247 bool error_inverted; /** True if error output is inverted */ 248}; 249 250/** 251 * @INTERNAL 252 * 253 * Data structure for Cortina/Inphi CS4343 device 254 */ 255struct cvmx_cs4343_info { 256 const char *name; /** Name of Inphi/Cortina CS4343 in DT */ 257 struct cvmx_phy_info *phy_info; 258 struct cvmx_cs4343_slice_info slice[4]; /** Slice information */ 259 int of_offset; 260}; 261 262/** 263 * @INTERNAL 264 * This data structure is used to hold PHY information and is subject to change. 265 * Please do not use this data structure directly. 266 * 267 * NOTE: The U-Boot OCTEON Ethernet drivers depends on this data structure for 268 * the mux support. 269 */ 270typedef struct cvmx_phy_info { 271 int phy_addr; /** MDIO address of PHY */ 272 int phy_sub_addr; /** Sub-address (i.e. slice), used by Cortina */ 273 int ipd_port; /** IPD port number for the PHY */ 274 /** MDIO bus PHY connected to (even if behind mux) */ 275 int mdio_unit; 276 int direct_connect; /** 1 if PHY is directly connected */ 277 int gpio[CVMX_PHY_MUX_MAX_GPIO]; /** GPIOs used to control mux, -1 if not used */ 278 279 /** Type of GPIO. It can be a local OCTEON GPIO or a TWSI GPIO */ 280 cvmx_phy_gpio_type_t gpio_type[CVMX_PHY_MUX_MAX_GPIO]; 281 282 /** Address of TWSI GPIO */ 283 int cvmx_gpio_twsi[CVMX_PHY_MUX_MAX_GPIO]; 284 285 /** Value to put into the GPIO lines to select MDIO bus */ 286 int gpio_value; 287 int gpio_parent_mux_twsi; /** -1 if not used, parent TWSI mux for ebb6600 */ 288 int gpio_parent_mux_select; /** selector to use on parent TWSI mux */ 289 cvmx_phy_type_t phy_type; /** Type of PHY */ 290 cvmx_phy_mux_type_t mux_type; /** Type of MDIO mux */ 291 int mux_twsi_addr; /** Address of the MDIO mux */ 292 cvmx_phy_host_mode_t host_mode; /** Used by Cortina PHY */ 293 void *phydev; /** Pointer to parent phy device */ 294 int fdt_offset; /** Node in flat device tree */ 295 int phy_i2c_bus; /** I2C bus for reclocking chips */ 296 int phy_i2c_addr; /** I2C address of reclocking chip */ 297 int num_vsc7224; /** Number of Microsemi VSC7224 devices */ 298 struct cvmx_vsc7224 *vsc7224; /** Info for VSC7224 devices */ 299 /** SFP/QSFP descriptor */ 300 struct cvmx_fdt_sfp_info *sfp_info; 301 /** CS4343 slice information for SGMII/XFI. This is NULL in XLAUI mode */ 302 struct cvmx_cs4343_slice_info *cs4343_slice_info; 303 /** CS4343 mphy information for XLAUI */ 304 struct cvmx_cs4343_info *cs4343_info; 305 /** Pointer to function to return link information */ 306 cvmx_helper_link_info_t (*link_function)(struct cvmx_phy_info *phy_info); 307 /** 308 * If there are LEDs driven by GPIO lines instead of by a PHY device 309 * then they are described here, otherwise gpio_leds should be NULL. 310 */ 311 struct cvmx_phy_gpio_leds *gpio_leds; 312} cvmx_phy_info_t; 313 314/* Fake IPD port, the RGMII/MII interface may use different PHY, use this 315 macro to return appropriate MIX address to read the PHY. */ 316#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 317 318/** 319 * Return the MII PHY address associated with the given IPD 320 * port. A result of -1 means there isn't a MII capable PHY 321 * connected to this port. On chips supporting multiple MII 322 * busses the bus number is encoded in bits <15:8>. 323 * 324 * This function must be modified for every new Octeon board. 325 * Internally it uses switch statements based on the cvmx_sysinfo 326 * data to determine board types and revisions. It relies on the 327 * fact that every Octeon board receives a unique board type 328 * enumeration from the bootloader. 329 * 330 * @param ipd_port Octeon IPD port to get the MII address for. 331 * 332 * @return MII PHY address and bus number or -1. 333 */ 334int cvmx_helper_board_get_mii_address(int ipd_port); 335 336/** 337 * This function as a board specific method of changing the PHY 338 * speed, duplex, and autonegotiation. This programs the PHY and 339 * not Octeon. This can be used to force Octeon's links to 340 * specific settings. 341 * 342 * @param phy_addr The address of the PHY to program 343 * @param link_flags 344 * Flags to control autonegotiation. Bit 0 is autonegotiation 345 * enable/disable to maintain backward compatibility. 346 * @param link_info Link speed to program. If the speed is zero and autonegotiation 347 * is enabled, all possible negotiation speeds are advertised. 348 * 349 * @return Zero on success, negative on failure 350 */ 351int cvmx_helper_board_link_set_phy(int phy_addr, 352 cvmx_helper_board_set_phy_link_flags_types_t link_flags, 353 cvmx_helper_link_info_t link_info); 354 355/** 356 * @INTERNAL 357 * This function is the board specific method of determining an 358 * ethernet ports link speed. Most Octeon boards have Marvell PHYs 359 * and are handled by the fall through case. This function must be 360 * updated for boards that don't have the normal Marvell PHYs. 361 * 362 * This function must be modified for every new Octeon board. 363 * Internally it uses switch statements based on the cvmx_sysinfo 364 * data to determine board types and revisions. It relies on the 365 * fact that every Octeon board receives a unique board type 366 * enumeration from the bootloader. 367 * 368 * @param ipd_port IPD input port associated with the port we want to get link 369 * status for. 370 * 371 * @return The ports link status. If the link isn't fully resolved, this must 372 * return zero. 373 */ 374cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); 375 376/** 377 * @INTERNAL 378 * This function is called by cvmx_helper_interface_probe() after it 379 * determines the number of ports Octeon can support on a specific 380 * interface. This function is the per board location to override 381 * this value. It is called with the number of ports Octeon might 382 * support and should return the number of actual ports on the 383 * board. 384 * 385 * This function must be modified for every new Octeon board. 386 * Internally it uses switch statements based on the cvmx_sysinfo 387 * data to determine board types and revisions. It relies on the 388 * fact that every Octeon board receives a unique board type 389 * enumeration from the bootloader. 390 * 391 * @param interface Interface to probe 392 * @param supported_ports 393 * Number of ports Octeon supports. 394 * 395 * @return Number of ports the actual board supports. Many times this will 396 * simple be "support_ports". 397 */ 398int __cvmx_helper_board_interface_probe(int interface, int supported_ports); 399 400/** 401 * @INTERNAL 402 * Enable packet input/output from the hardware. This function is 403 * called after by cvmx_helper_packet_hardware_enable() to 404 * perform board specific initialization. For most boards 405 * nothing is needed. 406 * 407 * @param interface Interface to enable 408 * 409 * @return Zero on success, negative on failure 410 */ 411int __cvmx_helper_board_hardware_enable(int interface); 412 413/** 414 * @INTERNAL 415 * Gets the clock type used for the USB block based on board type. 416 * Used by the USB code for auto configuration of clock type. 417 * 418 * @return USB clock type enumeration 419 */ 420cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void); 421 422/** 423 * @INTERNAL 424 * Adjusts the number of available USB ports on Octeon based on board 425 * specifics. 426 * 427 * @param supported_ports expected number of ports based on chip type; 428 * 429 * 430 * @return number of available usb ports, based on board specifics. 431 * Return value is supported_ports if function does not 432 * override. 433 */ 434int __cvmx_helper_board_usb_get_num_ports(int supported_ports); 435 436/** 437 * @INTERNAL 438 * Returns if a port is present on an interface 439 * 440 * @param fdt_addr - address fo flat device tree 441 * @param ipd_port - IPD port number 442 * 443 * @return 1 if port is present, 0 if not present, -1 if error 444 */ 445int __cvmx_helper_board_get_port_from_dt(void *fdt_addr, int ipd_port); 446 447/** 448 * Return the host mode for the PHY. Currently only the Cortina CS4321 PHY 449 * needs this. 450 * 451 * @param ipd_port - ipd port number to get the host mode for 452 * 453 * @return host mode for phy 454 */ 455cvmx_phy_host_mode_t cvmx_helper_board_get_phy_host_mode(int ipd_port); 456 457/** 458 * @INTERNAL 459 * This function outputs the cvmx_phy_info_t data structure for the specified 460 * port. 461 * 462 * @param[out] - phy_info - phy info data structure 463 * @param ipd_port - port to get phy info for 464 * 465 * @return 0 for success, -1 if info not available 466 * 467 * NOTE: The phy_info data structure is subject to change. 468 */ 469int cvmx_helper_board_get_phy_info(cvmx_phy_info_t *phy_info, int ipd_port); 470 471/** 472 * @INTERNAL 473 * Parse the device tree and set whether a port is valid or not. 474 * 475 * @param fdt_addr Pointer to device tree 476 * 477 * @return 0 for success, -1 on error. 478 */ 479int __cvmx_helper_parse_bgx_dt(const void *fdt_addr); 480 481/** 482 * @INTERNAL 483 * Parse the device tree and set whether a port is valid or not. 484 * 485 * @param fdt_addr Pointer to device tree 486 * 487 * @return 0 for success, -1 on error. 488 */ 489int __cvmx_helper_parse_bgx_rgmii_dt(const void *fdt_addr); 490 491/** 492 * @INTERNAL 493 * Updates any GPIO link LEDs if present 494 * 495 * @param xiface Interface number 496 * @param index Port index 497 * @param result Link status result 498 */ 499void cvmx_helper_update_link_led(int xiface, int index, cvmx_helper_link_info_t result); 500/** 501 * Update the RX activity LED for the specified interface and port index 502 * 503 * @param xiface Interface number 504 * @param index Port index 505 * @parma check_time True if we should bail out before the polling interval 506 */ 507void cvmx_update_rx_activity_led(int xiface, int index, bool check_time); 508 509/** 510 * @INTERNAL 511 * Figure out which mod_abs changed function to use based on the phy type 512 * 513 * @param xiface xinterface number 514 * @param index port index on interface 515 * 516 * @return 0 for success, -1 on error 517 * 518 * This function figures out the proper mod_abs_changed function to use and 519 * registers the appropriate function. This should be called after the device 520 * tree has been fully parsed for the given port as well as after all SFP 521 * slots and any Microsemi VSC7224 devices have been parsed in the device tree. 522 */ 523int cvmx_helper_phy_register_mod_abs_changed(int xiface, int index); 524 525/** 526 * @INTERNAL 527 * Return loss of signal 528 * 529 * @param xiface xinterface number 530 * @param index port index on interface 531 * 532 * @return 0 if signal present, 1 if loss of signal. 533 * 534 * @NOTE: A result of 0 is possible in some cases where the signal is 535 * not present. 536 * 537 * This is for use with __cvmx_qlm_rx_equilization 538 */ 539int __cvmx_helper_get_los(int xiface, int index); 540 541/** 542 * Given the address of the MDIO registers, output the CPU node and MDIO bus 543 * 544 * @param addr 64-bit address of MDIO registers (from device tree) 545 * @param[out] node CPU node number (78xx) 546 * @param[out] bus MDIO bus number 547 */ 548void __cvmx_mdio_addr_to_node_bus(u64 addr, int *node, int *bus); 549 550/** 551 * Turn on the error LED 552 * 553 * @param leds LEDs belonging to port 554 * @param error true to turn on LED, false to turn off 555 */ 556void cvmx_helper_leds_show_error(struct cvmx_phy_gpio_leds *leds, bool error); 557 558#endif /* __CVMX_HELPER_BOARD_H__ */ 559