LXR uboot/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 2020 Marvell International Ltd.
   4 *
   5 * Configuration and status register (CSR) type definitions for
   6 * Octeon npi.
   7 */
   8
   9#ifndef __CVMX_NPI_DEFS_H__
  10#define __CVMX_NPI_DEFS_H__
  11
  12#define CVMX_NPI_BASE_ADDR_INPUT0          CVMX_NPI_BASE_ADDR_INPUTX(0)
  13#define CVMX_NPI_BASE_ADDR_INPUT1          CVMX_NPI_BASE_ADDR_INPUTX(1)
  14#define CVMX_NPI_BASE_ADDR_INPUT2          CVMX_NPI_BASE_ADDR_INPUTX(2)
  15#define CVMX_NPI_BASE_ADDR_INPUT3          CVMX_NPI_BASE_ADDR_INPUTX(3)
  16#define CVMX_NPI_BASE_ADDR_INPUTX(offset)  (0x00011F0000000070ull + ((offset) & 3) * 16)
  17#define CVMX_NPI_BASE_ADDR_OUTPUT0         CVMX_NPI_BASE_ADDR_OUTPUTX(0)
  18#define CVMX_NPI_BASE_ADDR_OUTPUT1         CVMX_NPI_BASE_ADDR_OUTPUTX(1)
  19#define CVMX_NPI_BASE_ADDR_OUTPUT2         CVMX_NPI_BASE_ADDR_OUTPUTX(2)
  20#define CVMX_NPI_BASE_ADDR_OUTPUT3         CVMX_NPI_BASE_ADDR_OUTPUTX(3)
  21#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (0x00011F00000000B8ull + ((offset) & 3) * 8)
  22#define CVMX_NPI_BIST_STATUS               (0x00011F00000003F8ull)
  23#define CVMX_NPI_BUFF_SIZE_OUTPUT0         CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
  24#define CVMX_NPI_BUFF_SIZE_OUTPUT1         CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
  25#define CVMX_NPI_BUFF_SIZE_OUTPUT2         CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
  26#define CVMX_NPI_BUFF_SIZE_OUTPUT3         CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
  27#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (0x00011F00000000E0ull + ((offset) & 3) * 8)
  28#define CVMX_NPI_COMP_CTL                  (0x00011F0000000218ull)
  29#define CVMX_NPI_CTL_STATUS                (0x00011F0000000010ull)
  30#define CVMX_NPI_DBG_SELECT                (0x00011F0000000008ull)
  31#define CVMX_NPI_DMA_CONTROL               (0x00011F0000000128ull)
  32#define CVMX_NPI_DMA_HIGHP_COUNTS          (0x00011F0000000148ull)
  33#define CVMX_NPI_DMA_HIGHP_NADDR           (0x00011F0000000158ull)
  34#define CVMX_NPI_DMA_LOWP_COUNTS           (0x00011F0000000140ull)
  35#define CVMX_NPI_DMA_LOWP_NADDR            (0x00011F0000000150ull)
  36#define CVMX_NPI_HIGHP_DBELL               (0x00011F0000000120ull)
  37#define CVMX_NPI_HIGHP_IBUFF_SADDR         (0x00011F0000000110ull)
  38#define CVMX_NPI_INPUT_CONTROL             (0x00011F0000000138ull)
  39#define CVMX_NPI_INT_ENB                   (0x00011F0000000020ull)
  40#define CVMX_NPI_INT_SUM                   (0x00011F0000000018ull)
  41#define CVMX_NPI_LOWP_DBELL                (0x00011F0000000118ull)
  42#define CVMX_NPI_LOWP_IBUFF_SADDR          (0x00011F0000000108ull)
  43#define CVMX_NPI_MEM_ACCESS_SUBID3         CVMX_NPI_MEM_ACCESS_SUBIDX(3)
  44#define CVMX_NPI_MEM_ACCESS_SUBID4         CVMX_NPI_MEM_ACCESS_SUBIDX(4)
  45#define CVMX_NPI_MEM_ACCESS_SUBID5         CVMX_NPI_MEM_ACCESS_SUBIDX(5)
  46#define CVMX_NPI_MEM_ACCESS_SUBID6         CVMX_NPI_MEM_ACCESS_SUBIDX(6)
  47#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (0x00011F0000000028ull + ((offset) & 7) * 8 - 8 * 3)
  48#define CVMX_NPI_MSI_RCV                   (0x0000000000000190ull)
  49#define CVMX_NPI_NPI_MSI_RCV               (0x00011F0000001190ull)
  50#define CVMX_NPI_NUM_DESC_OUTPUT0          CVMX_NPI_NUM_DESC_OUTPUTX(0)
  51#define CVMX_NPI_NUM_DESC_OUTPUT1          CVMX_NPI_NUM_DESC_OUTPUTX(1)
  52#define CVMX_NPI_NUM_DESC_OUTPUT2          CVMX_NPI_NUM_DESC_OUTPUTX(2)
  53#define CVMX_NPI_NUM_DESC_OUTPUT3          CVMX_NPI_NUM_DESC_OUTPUTX(3)
  54#define CVMX_NPI_NUM_DESC_OUTPUTX(offset)  (0x00011F0000000050ull + ((offset) & 3) * 8)
  55#define CVMX_NPI_OUTPUT_CONTROL            (0x00011F0000000100ull)
  56#define CVMX_NPI_P0_DBPAIR_ADDR            CVMX_NPI_PX_DBPAIR_ADDR(0)
  57#define CVMX_NPI_P0_INSTR_ADDR             CVMX_NPI_PX_INSTR_ADDR(0)
  58#define CVMX_NPI_P0_INSTR_CNTS             CVMX_NPI_PX_INSTR_CNTS(0)
  59#define CVMX_NPI_P0_PAIR_CNTS              CVMX_NPI_PX_PAIR_CNTS(0)
  60#define CVMX_NPI_P1_DBPAIR_ADDR            CVMX_NPI_PX_DBPAIR_ADDR(1)
  61#define CVMX_NPI_P1_INSTR_ADDR             CVMX_NPI_PX_INSTR_ADDR(1)
  62#define CVMX_NPI_P1_INSTR_CNTS             CVMX_NPI_PX_INSTR_CNTS(1)
  63#define CVMX_NPI_P1_PAIR_CNTS              CVMX_NPI_PX_PAIR_CNTS(1)
  64#define CVMX_NPI_P2_DBPAIR_ADDR            CVMX_NPI_PX_DBPAIR_ADDR(2)
  65#define CVMX_NPI_P2_INSTR_ADDR             CVMX_NPI_PX_INSTR_ADDR(2)
  66#define CVMX_NPI_P2_INSTR_CNTS             CVMX_NPI_PX_INSTR_CNTS(2)
  67#define CVMX_NPI_P2_PAIR_CNTS              CVMX_NPI_PX_PAIR_CNTS(2)
  68#define CVMX_NPI_P3_DBPAIR_ADDR            CVMX_NPI_PX_DBPAIR_ADDR(3)
  69#define CVMX_NPI_P3_INSTR_ADDR             CVMX_NPI_PX_INSTR_ADDR(3)
  70#define CVMX_NPI_P3_INSTR_CNTS             CVMX_NPI_PX_INSTR_CNTS(3)
  71#define CVMX_NPI_P3_PAIR_CNTS              CVMX_NPI_PX_PAIR_CNTS(3)
  72#define CVMX_NPI_PCI_BAR1_INDEXX(offset)   (0x00011F0000001100ull + ((offset) & 31) * 4)
  73#define CVMX_NPI_PCI_BIST_REG              (0x00011F00000011C0ull)
  74#define CVMX_NPI_PCI_BURST_SIZE            (0x00011F00000000D8ull)
  75#define CVMX_NPI_PCI_CFG00                 (0x00011F0000001800ull)
  76#define CVMX_NPI_PCI_CFG01                 (0x00011F0000001804ull)
  77#define CVMX_NPI_PCI_CFG02                 (0x00011F0000001808ull)
  78#define CVMX_NPI_PCI_CFG03                 (0x00011F000000180Cull)
  79#define CVMX_NPI_PCI_CFG04                 (0x00011F0000001810ull)
  80#define CVMX_NPI_PCI_CFG05                 (0x00011F0000001814ull)
  81#define CVMX_NPI_PCI_CFG06                 (0x00011F0000001818ull)
  82#define CVMX_NPI_PCI_CFG07                 (0x00011F000000181Cull)
  83#define CVMX_NPI_PCI_CFG08                 (0x00011F0000001820ull)
  84#define CVMX_NPI_PCI_CFG09                 (0x00011F0000001824ull)
  85#define CVMX_NPI_PCI_CFG10                 (0x00011F0000001828ull)
  86#define CVMX_NPI_PCI_CFG11                 (0x00011F000000182Cull)
  87#define CVMX_NPI_PCI_CFG12                 (0x00011F0000001830ull)
  88#define CVMX_NPI_PCI_CFG13                 (0x00011F0000001834ull)
  89#define CVMX_NPI_PCI_CFG15                 (0x00011F000000183Cull)
  90#define CVMX_NPI_PCI_CFG16                 (0x00011F0000001840ull)
  91#define CVMX_NPI_PCI_CFG17                 (0x00011F0000001844ull)
  92#define CVMX_NPI_PCI_CFG18                 (0x00011F0000001848ull)
  93#define CVMX_NPI_PCI_CFG19                 (0x00011F000000184Cull)
  94#define CVMX_NPI_PCI_CFG20                 (0x00011F0000001850ull)
  95#define CVMX_NPI_PCI_CFG21                 (0x00011F0000001854ull)
  96#define CVMX_NPI_PCI_CFG22                 (0x00011F0000001858ull)
  97#define CVMX_NPI_PCI_CFG56                 (0x00011F00000018E0ull)
  98#define CVMX_NPI_PCI_CFG57                 (0x00011F00000018E4ull)
  99#define CVMX_NPI_PCI_CFG58                 (0x00011F00000018E8ull)
 100#define CVMX_NPI_PCI_CFG59                 (0x00011F00000018ECull)
 101#define CVMX_NPI_PCI_CFG60                 (0x00011F00000018F0ull)
 102#define CVMX_NPI_PCI_CFG61                 (0x00011F00000018F4ull)
 103#define CVMX_NPI_PCI_CFG62                 (0x00011F00000018F8ull)
 104#define CVMX_NPI_PCI_CFG63                 (0x00011F00000018FCull)
 105#define CVMX_NPI_PCI_CNT_REG               (0x00011F00000011B8ull)
 106#define CVMX_NPI_PCI_CTL_STATUS_2          (0x00011F000000118Cull)
 107#define CVMX_NPI_PCI_INT_ARB_CFG           (0x00011F0000000130ull)
 108#define CVMX_NPI_PCI_INT_ENB2              (0x00011F00000011A0ull)
 109#define CVMX_NPI_PCI_INT_SUM2              (0x00011F0000001198ull)
 110#define CVMX_NPI_PCI_READ_CMD              (0x00011F0000000048ull)
 111#define CVMX_NPI_PCI_READ_CMD_6            (0x00011F0000001180ull)
 112#define CVMX_NPI_PCI_READ_CMD_C            (0x00011F0000001184ull)
 113#define CVMX_NPI_PCI_READ_CMD_E            (0x00011F0000001188ull)
 114#define CVMX_NPI_PCI_SCM_REG               (0x00011F00000011A8ull)
 115#define CVMX_NPI_PCI_TSR_REG               (0x00011F00000011B0ull)
 116#define CVMX_NPI_PORT32_INSTR_HDR          (0x00011F00000001F8ull)
 117#define CVMX_NPI_PORT33_INSTR_HDR          (0x00011F0000000200ull)
 118#define CVMX_NPI_PORT34_INSTR_HDR          (0x00011F0000000208ull)
 119#define CVMX_NPI_PORT35_INSTR_HDR          (0x00011F0000000210ull)
 120#define CVMX_NPI_PORT_BP_CONTROL           (0x00011F00000001F0ull)
 121#define CVMX_NPI_PX_DBPAIR_ADDR(offset)    (0x00011F0000000180ull + ((offset) & 3) * 8)
 122#define CVMX_NPI_PX_INSTR_ADDR(offset)     (0x00011F00000001C0ull + ((offset) & 3) * 8)
 123#define CVMX_NPI_PX_INSTR_CNTS(offset)     (0x00011F00000001A0ull + ((offset) & 3) * 8)
 124#define CVMX_NPI_PX_PAIR_CNTS(offset)      (0x00011F0000000160ull + ((offset) & 3) * 8)
 125#define CVMX_NPI_RSL_INT_BLOCKS            (0x00011F0000000000ull)
 126#define CVMX_NPI_SIZE_INPUT0               CVMX_NPI_SIZE_INPUTX(0)
 127#define CVMX_NPI_SIZE_INPUT1               CVMX_NPI_SIZE_INPUTX(1)
 128#define CVMX_NPI_SIZE_INPUT2               CVMX_NPI_SIZE_INPUTX(2)
 129#define CVMX_NPI_SIZE_INPUT3               CVMX_NPI_SIZE_INPUTX(3)
 130#define CVMX_NPI_SIZE_INPUTX(offset)       (0x00011F0000000078ull + ((offset) & 3) * 16)
 131#define CVMX_NPI_WIN_READ_TO               (0x00011F00000001E0ull)
 132
 133/**
 134 * cvmx_npi_base_addr_input#
 135 *
 136 * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register
 137 *
 138 * The address to start reading Instructions from for Input-0.
 139 */
 140union cvmx_npi_base_addr_inputx {
 141        u64 u64;
 142        struct cvmx_npi_base_addr_inputx_s {
 143                u64 baddr : 61;
 144                u64 reserved_0_2 : 3;
 145        } s;
 146        struct cvmx_npi_base_addr_inputx_s cn30xx;
 147        struct cvmx_npi_base_addr_inputx_s cn31xx;
 148        struct cvmx_npi_base_addr_inputx_s cn38xx;
 149        struct cvmx_npi_base_addr_inputx_s cn38xxp2;
 150        struct cvmx_npi_base_addr_inputx_s cn50xx;
 151        struct cvmx_npi_base_addr_inputx_s cn58xx;
 152        struct cvmx_npi_base_addr_inputx_s cn58xxp1;
 153};
 154
 155typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t;
 156
 157/**
 158 * cvmx_npi_base_addr_output#
 159 *
 160 * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register
 161 *
 162 * The address to start reading Instructions from for Output-0.
 163 */
 164union cvmx_npi_base_addr_outputx {
 165        u64 u64;
 166        struct cvmx_npi_base_addr_outputx_s {
 167                u64 baddr : 61;
 168                u64 reserved_0_2 : 3;
 169        } s;
 170        struct cvmx_npi_base_addr_outputx_s cn30xx;
 171        struct cvmx_npi_base_addr_outputx_s cn31xx;
 172        struct cvmx_npi_base_addr_outputx_s cn38xx;
 173        struct cvmx_npi_base_addr_outputx_s cn38xxp2;
 174        struct cvmx_npi_base_addr_outputx_s cn50xx;
 175        struct cvmx_npi_base_addr_outputx_s cn58xx;
 176        struct cvmx_npi_base_addr_outputx_s cn58xxp1;
 177};
 178
 179typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t;
 180
 181/**
 182 * cvmx_npi_bist_status
 183 *
 184 * NPI_BIST_STATUS = NPI's BIST Status Register
 185 *
 186 * Results from BIST runs of NPI's memories.
 187 */
 188union cvmx_npi_bist_status {
 189        u64 u64;
 190        struct cvmx_npi_bist_status_s {
 191                u64 reserved_20_63 : 44;
 192                u64 csr_bs : 1;
 193                u64 dif_bs : 1;
 194                u64 rdp_bs : 1;
 195                u64 pcnc_bs : 1;
 196                u64 pcn_bs : 1;
 197                u64 rdn_bs : 1;
 198                u64 pcac_bs : 1;
 199                u64 pcad_bs : 1;
 200                u64 rdnl_bs : 1;
 201                u64 pgf_bs : 1;
 202                u64 pig_bs : 1;
 203                u64 pof0_bs : 1;
 204                u64 pof1_bs : 1;
 205                u64 pof2_bs : 1;
 206                u64 pof3_bs : 1;
 207                u64 pos_bs : 1;
 208                u64 nus_bs : 1;
 209                u64 dob_bs : 1;
 210                u64 pdf_bs : 1;
 211                u64 dpi_bs : 1;
 212        } s;
 213        struct cvmx_npi_bist_status_cn30xx {
 214                u64 reserved_20_63 : 44;
 215                u64 csr_bs : 1;
 216                u64 dif_bs : 1;
 217                u64 rdp_bs : 1;
 218                u64 pcnc_bs : 1;
 219                u64 pcn_bs : 1;
 220                u64 rdn_bs : 1;
 221                u64 pcac_bs : 1;
 222                u64 pcad_bs : 1;
 223                u64 rdnl_bs : 1;
 224                u64 pgf_bs : 1;
 225                u64 pig_bs : 1;
 226                u64 pof0_bs : 1;
 227                u64 reserved_5_7 : 3;
 228                u64 pos_bs : 1;
 229                u64 nus_bs : 1;
 230                u64 dob_bs : 1;
 231                u64 pdf_bs : 1;
 232                u64 dpi_bs : 1;
 233        } cn30xx;
 234        struct cvmx_npi_bist_status_s cn31xx;
 235        struct cvmx_npi_bist_status_s cn38xx;
 236        struct cvmx_npi_bist_status_s cn38xxp2;
 237        struct cvmx_npi_bist_status_cn50xx {
 238                u64 reserved_20_63 : 44;
 239                u64 csr_bs : 1;
 240                u64 dif_bs : 1;
 241                u64 rdp_bs : 1;
 242                u64 pcnc_bs : 1;
 243                u64 pcn_bs : 1;
 244                u64 rdn_bs : 1;
 245                u64 pcac_bs : 1;
 246                u64 pcad_bs : 1;
 247                u64 rdnl_bs : 1;
 248                u64 pgf_bs : 1;
 249                u64 pig_bs : 1;
 250                u64 pof0_bs : 1;
 251                u64 pof1_bs : 1;
 252                u64 reserved_5_6 : 2;
 253                u64 pos_bs : 1;
 254                u64 nus_bs : 1;
 255                u64 dob_bs : 1;
 256                u64 pdf_bs : 1;
 257                u64 dpi_bs : 1;
 258        } cn50xx;
 259        struct cvmx_npi_bist_status_s cn58xx;
 260        struct cvmx_npi_bist_status_s cn58xxp1;
 261};
 262
 263typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t;
 264
 265/**
 266 * cvmx_npi_buff_size_output#
 267 *
 268 * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0
 269 *
 270 * The size in bytes of the Data Bufffer and Information Buffer for output 0.
 271 */
 272union cvmx_npi_buff_size_outputx {
 273        u64 u64;
 274        struct cvmx_npi_buff_size_outputx_s {
 275                u64 reserved_23_63 : 41;
 276                u64 isize : 7;
 277                u64 bsize : 16;
 278        } s;
 279        struct cvmx_npi_buff_size_outputx_s cn30xx;
 280        struct cvmx_npi_buff_size_outputx_s cn31xx;
 281        struct cvmx_npi_buff_size_outputx_s cn38xx;
 282        struct cvmx_npi_buff_size_outputx_s cn38xxp2;
 283        struct cvmx_npi_buff_size_outputx_s cn50xx;
 284        struct cvmx_npi_buff_size_outputx_s cn58xx;
 285        struct cvmx_npi_buff_size_outputx_s cn58xxp1;
 286};
 287
 288typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t;
 289
 290/**
 291 * cvmx_npi_comp_ctl
 292 *
 293 * NPI_COMP_CTL = PCI Compensation Control
 294 *
 295 * PCI Compensation Control
 296 */
 297union cvmx_npi_comp_ctl {
 298        u64 u64;
 299        struct cvmx_npi_comp_ctl_s {
 300                u64 reserved_10_63 : 54;
 301                u64 pctl : 5;
 302                u64 nctl : 5;
 303        } s;
 304        struct cvmx_npi_comp_ctl_s cn50xx;
 305        struct cvmx_npi_comp_ctl_s cn58xx;
 306        struct cvmx_npi_comp_ctl_s cn58xxp1;
 307};
 308
 309typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t;
 310
 311/**
 312 * cvmx_npi_ctl_status
 313 *
 314 * NPI_CTL_STATUS = NPI's Control Status Register
 315 *
 316 * Contains control ans status for NPI.
 317 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
 318 * To ensure that a write has completed the user must read the register before
 319 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
 320 */
 321union cvmx_npi_ctl_status {
 322        u64 u64;
 323        struct cvmx_npi_ctl_status_s {
 324                u64 reserved_63_63 : 1;
 325                u64 chip_rev : 8;
 326                u64 dis_pniw : 1;
 327                u64 out3_enb : 1;
 328                u64 out2_enb : 1;
 329                u64 out1_enb : 1;
 330                u64 out0_enb : 1;
 331                u64 ins3_enb : 1;
 332                u64 ins2_enb : 1;
 333                u64 ins1_enb : 1;
 334                u64 ins0_enb : 1;
 335                u64 ins3_64b : 1;
 336                u64 ins2_64b : 1;
 337                u64 ins1_64b : 1;
 338                u64 ins0_64b : 1;
 339                u64 pci_wdis : 1;
 340                u64 wait_com : 1;
 341                u64 reserved_37_39 : 3;
 342                u64 max_word : 5;
 343                u64 reserved_10_31 : 22;
 344                u64 timer : 10;
 345        } s;
 346        struct cvmx_npi_ctl_status_cn30xx {
 347                u64 reserved_63_63 : 1;
 348                u64 chip_rev : 8;
 349                u64 dis_pniw : 1;
 350                u64 reserved_51_53 : 3;
 351                u64 out0_enb : 1;
 352                u64 reserved_47_49 : 3;
 353                u64 ins0_enb : 1;
 354                u64 reserved_43_45 : 3;
 355                u64 ins0_64b : 1;
 356                u64 pci_wdis : 1;
 357                u64 wait_com : 1;
 358                u64 reserved_37_39 : 3;
 359                u64 max_word : 5;
 360                u64 reserved_10_31 : 22;
 361                u64 timer : 10;
 362        } cn30xx;
 363        struct cvmx_npi_ctl_status_cn31xx {
 364                u64 reserved_63_63 : 1;
 365                u64 chip_rev : 8;
 366                u64 dis_pniw : 1;
 367                u64 reserved_52_53 : 2;
 368                u64 out1_enb : 1;
 369                u64 out0_enb : 1;
 370                u64 reserved_48_49 : 2;
 371                u64 ins1_enb : 1;
 372                u64 ins0_enb : 1;
 373                u64 reserved_44_45 : 2;
 374                u64 ins1_64b : 1;
 375                u64 ins0_64b : 1;
 376                u64 pci_wdis : 1;
 377                u64 wait_com : 1;
 378                u64 reserved_37_39 : 3;
 379                u64 max_word : 5;
 380                u64 reserved_10_31 : 22;
 381                u64 timer : 10;
 382        } cn31xx;
 383        struct cvmx_npi_ctl_status_s cn38xx;
 384        struct cvmx_npi_ctl_status_s cn38xxp2;
 385        struct cvmx_npi_ctl_status_cn31xx cn50xx;
 386        struct cvmx_npi_ctl_status_s cn58xx;
 387        struct cvmx_npi_ctl_status_s cn58xxp1;
 388};
 389
 390typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t;
 391
 392/**
 393 * cvmx_npi_dbg_select
 394 *
 395 * NPI_DBG_SELECT = Debug Select Register
 396 *
 397 * Contains the debug select value in last written to the RSLs.
 398 */
 399union cvmx_npi_dbg_select {
 400        u64 u64;
 401        struct cvmx_npi_dbg_select_s {
 402                u64 reserved_16_63 : 48;
 403                u64 dbg_sel : 16;
 404        } s;
 405        struct cvmx_npi_dbg_select_s cn30xx;
 406        struct cvmx_npi_dbg_select_s cn31xx;
 407        struct cvmx_npi_dbg_select_s cn38xx;
 408        struct cvmx_npi_dbg_select_s cn38xxp2;
 409        struct cvmx_npi_dbg_select_s cn50xx;
 410        struct cvmx_npi_dbg_select_s cn58xx;
 411        struct cvmx_npi_dbg_select_s cn58xxp1;
 412};
 413
 414typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t;
 415
 416/**
 417 * cvmx_npi_dma_control
 418 *
 419 * NPI_DMA_CONTROL = DMA Control Register
 420 *
 421 * Controls operation of the DMA IN/OUT of the NPI.
 422 */
 423union cvmx_npi_dma_control {
 424        u64 u64;
 425        struct cvmx_npi_dma_control_s {
 426                u64 reserved_36_63 : 28;
 427                u64 b0_lend : 1;
 428                u64 dwb_denb : 1;
 429                u64 dwb_ichk : 9;
 430                u64 fpa_que : 3;
 431                u64 o_add1 : 1;
 432                u64 o_ro : 1;
 433                u64 o_ns : 1;
 434                u64 o_es : 2;
 435                u64 o_mode : 1;
 436                u64 hp_enb : 1;
 437                u64 lp_enb : 1;
 438                u64 csize : 14;
 439        } s;
 440        struct cvmx_npi_dma_control_s cn30xx;
 441        struct cvmx_npi_dma_control_s cn31xx;
 442        struct cvmx_npi_dma_control_s cn38xx;
 443        struct cvmx_npi_dma_control_s cn38xxp2;
 444        struct cvmx_npi_dma_control_s cn50xx;
 445        struct cvmx_npi_dma_control_s cn58xx;
 446        struct cvmx_npi_dma_control_s cn58xxp1;
 447};
 448
 449typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t;
 450
 451/**
 452 * cvmx_npi_dma_highp_counts
 453 *
 454 * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts
 455 *
 456 * Values for determing the number of instructions for High Priority DMA in the NPI.
 457 */
 458union cvmx_npi_dma_highp_counts {
 459        u64 u64;
 460        struct cvmx_npi_dma_highp_counts_s {
 461                u64 reserved_39_63 : 25;
 462                u64 fcnt : 7;
 463                u64 dbell : 32;
 464        } s;
 465        struct cvmx_npi_dma_highp_counts_s cn30xx;
 466        struct cvmx_npi_dma_highp_counts_s cn31xx;
 467        struct cvmx_npi_dma_highp_counts_s cn38xx;
 468        struct cvmx_npi_dma_highp_counts_s cn38xxp2;
 469        struct cvmx_npi_dma_highp_counts_s cn50xx;
 470        struct cvmx_npi_dma_highp_counts_s cn58xx;
 471        struct cvmx_npi_dma_highp_counts_s cn58xxp1;
 472};
 473
 474typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t;
 475
 476/**
 477 * cvmx_npi_dma_highp_naddr
 478 *
 479 * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address
 480 *
 481 * Place NPI will read the next Ichunk data from. This is valid when state is 0
 482 */
 483union cvmx_npi_dma_highp_naddr {
 484        u64 u64;
 485        struct cvmx_npi_dma_highp_naddr_s {
 486                u64 reserved_40_63 : 24;
 487                u64 state : 4;
 488                u64 addr : 36;
 489        } s;
 490        struct cvmx_npi_dma_highp_naddr_s cn30xx;
 491        struct cvmx_npi_dma_highp_naddr_s cn31xx;
 492        struct cvmx_npi_dma_highp_naddr_s cn38xx;
 493        struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
 494        struct cvmx_npi_dma_highp_naddr_s cn50xx;
 495        struct cvmx_npi_dma_highp_naddr_s cn58xx;
 496        struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
 497};
 498
 499typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t;
 500
 501/**
 502 * cvmx_npi_dma_lowp_counts
 503 *
 504 * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts
 505 *
 506 * Values for determing the number of instructions for Low Priority DMA in the NPI.
 507 */
 508union cvmx_npi_dma_lowp_counts {
 509        u64 u64;
 510        struct cvmx_npi_dma_lowp_counts_s {
 511                u64 reserved_39_63 : 25;
 512                u64 fcnt : 7;
 513                u64 dbell : 32;
 514        } s;
 515        struct cvmx_npi_dma_lowp_counts_s cn30xx;
 516        struct cvmx_npi_dma_lowp_counts_s cn31xx;
 517        struct cvmx_npi_dma_lowp_counts_s cn38xx;
 518        struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
 519        struct cvmx_npi_dma_lowp_counts_s cn50xx;
 520        struct cvmx_npi_dma_lowp_counts_s cn58xx;
 521        struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
 522};
 523
 524typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t;
 525
 526/**
 527 * cvmx_npi_dma_lowp_naddr
 528 *
 529 * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address
 530 *
 531 * Place NPI will read the next Ichunk data from. This is valid when state is 0
 532 */
 533union cvmx_npi_dma_lowp_naddr {
 534        u64 u64;
 535        struct cvmx_npi_dma_lowp_naddr_s {
 536                u64 reserved_40_63 : 24;
 537                u64 state : 4;
 538                u64 addr : 36;
 539        } s;
 540        struct cvmx_npi_dma_lowp_naddr_s cn30xx;
 541        struct cvmx_npi_dma_lowp_naddr_s cn31xx;
 542        struct cvmx_npi_dma_lowp_naddr_s cn38xx;
 543        struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
 544        struct cvmx_npi_dma_lowp_naddr_s cn50xx;
 545        struct cvmx_npi_dma_lowp_naddr_s cn58xx;
 546        struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
 547};
 548
 549typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t;
 550
 551/**
 552 * cvmx_npi_highp_dbell
 553 *
 554 * NPI_HIGHP_DBELL = High Priority Door Bell
 555 *
 556 * The door bell register for the high priority DMA queue.
 557 */
 558union cvmx_npi_highp_dbell {
 559        u64 u64;
 560        struct cvmx_npi_highp_dbell_s {
 561                u64 reserved_16_63 : 48;
 562                u64 dbell : 16;
 563        } s;
 564        struct cvmx_npi_highp_dbell_s cn30xx;
 565        struct cvmx_npi_highp_dbell_s cn31xx;
 566        struct cvmx_npi_highp_dbell_s cn38xx;
 567        struct cvmx_npi_highp_dbell_s cn38xxp2;
 568        struct cvmx_npi_highp_dbell_s cn50xx;
 569        struct cvmx_npi_highp_dbell_s cn58xx;
 570        struct cvmx_npi_highp_dbell_s cn58xxp1;
 571};
 572
 573typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t;
 574
 575/**
 576 * cvmx_npi_highp_ibuff_saddr
 577 *
 578 * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address
 579 *
 580 * The address to start reading Instructions from for HIGHP.
 581 */
 582union cvmx_npi_highp_ibuff_saddr {
 583        u64 u64;
 584        struct cvmx_npi_highp_ibuff_saddr_s {
 585                u64 reserved_36_63 : 28;
 586                u64 saddr : 36;
 587        } s;
 588        struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
 589        struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
 590        struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
 591        struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
 592        struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
 593        struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
 594        struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
 595};
 596
 597typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t;
 598
 599/**
 600 * cvmx_npi_input_control
 601 *
 602 * NPI_INPUT_CONTROL = NPI's Input Control Register
 603 *
 604 * Control for reads for gather list and instructions.
 605 */
 606union cvmx_npi_input_control {
 607        u64 u64;
 608        struct cvmx_npi_input_control_s {
 609                u64 reserved_23_63 : 41;
 610                u64 pkt_rr : 1;
 611                u64 pbp_dhi : 13;
 612                u64 d_nsr : 1;
 613                u64 d_esr : 2;
 614                u64 d_ror : 1;
 615                u64 use_csr : 1;
 616                u64 nsr : 1;
 617                u64 esr : 2;
 618                u64 ror : 1;
 619        } s;
 620        struct cvmx_npi_input_control_cn30xx {
 621                u64 reserved_22_63 : 42;
 622                u64 pbp_dhi : 13;
 623                u64 d_nsr : 1;
 624                u64 d_esr : 2;
 625                u64 d_ror : 1;
 626                u64 use_csr : 1;
 627                u64 nsr : 1;
 628                u64 esr : 2;
 629                u64 ror : 1;
 630        } cn30xx;
 631        struct cvmx_npi_input_control_cn30xx cn31xx;
 632        struct cvmx_npi_input_control_s cn38xx;
 633        struct cvmx_npi_input_control_cn30xx cn38xxp2;
 634        struct cvmx_npi_input_control_s cn50xx;
 635        struct cvmx_npi_input_control_s cn58xx;
 636        struct cvmx_npi_input_control_s cn58xxp1;
 637};
 638
 639typedef union cvmx_npi_input_control cvmx_npi_input_control_t;
 640
 641/**
 642 * cvmx_npi_int_enb
 643 *
 644 * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register
 645 *
 646 * Used to enable the various interrupting conditions of NPI
 647 */
 648union cvmx_npi_int_enb {
 649        u64 u64;
 650        struct cvmx_npi_int_enb_s {
 651                u64 reserved_62_63 : 2;
 652                u64 q1_a_f : 1;
 653                u64 q1_s_e : 1;
 654                u64 pdf_p_f : 1;
 655                u64 pdf_p_e : 1;
 656                u64 pcf_p_f : 1;
 657                u64 pcf_p_e : 1;
 658                u64 rdx_s_e : 1;
 659                u64 rwx_s_e : 1;
 660                u64 pnc_a_f : 1;
 661                u64 pnc_s_e : 1;
 662                u64 com_a_f : 1;
 663                u64 com_s_e : 1;
 664                u64 q3_a_f : 1;
 665                u64 q3_s_e : 1;
 666                u64 q2_a_f : 1;
 667                u64 q2_s_e : 1;
 668                u64 pcr_a_f : 1;
 669                u64 pcr_s_e : 1;
 670                u64 fcr_a_f : 1;
 671                u64 fcr_s_e : 1;
 672                u64 iobdma : 1;
 673                u64 p_dperr : 1;
 674                u64 win_rto : 1;
 675                u64 i3_pperr : 1;
 676                u64 i2_pperr : 1;
 677                u64 i1_pperr : 1;
 678                u64 i0_pperr : 1;
 679                u64 p3_ptout : 1;
 680                u64 p2_ptout : 1;
 681                u64 p1_ptout : 1;
 682                u64 p0_ptout : 1;
 683                u64 p3_pperr : 1;
 684                u64 p2_pperr : 1;
 685                u64 p1_pperr : 1;
 686                u64 p0_pperr : 1;
 687                u64 g3_rtout : 1;
 688                u64 g2_rtout : 1;
 689                u64 g1_rtout : 1;
 690                u64 g0_rtout : 1;
 691                u64 p3_perr : 1;
 692                u64 p2_perr : 1;
 693                u64 p1_perr : 1;
 694                u64 p0_perr : 1;
 695                u64 p3_rtout : 1;
 696                u64 p2_rtout : 1;
 697                u64 p1_rtout : 1;
 698                u64 p0_rtout : 1;
 699                u64 i3_overf : 1;
 700                u64 i2_overf : 1;
 701                u64 i1_overf : 1;
 702                u64 i0_overf : 1;
 703                u64 i3_rtout : 1;
 704                u64 i2_rtout : 1;
 705                u64 i1_rtout : 1;
 706                u64 i0_rtout : 1;
 707                u64 po3_2sml : 1;
 708                u64 po2_2sml : 1;
 709                u64 po1_2sml : 1;
 710                u64 po0_2sml : 1;
 711                u64 pci_rsl : 1;
 712                u64 rml_wto : 1;
 713                u64 rml_rto : 1;
 714        } s;
 715        struct cvmx_npi_int_enb_cn30xx {
 716                u64 reserved_62_63 : 2;
 717                u64 q1_a_f : 1;
 718                u64 q1_s_e : 1;
 719                u64 pdf_p_f : 1;
 720                u64 pdf_p_e : 1;
 721                u64 pcf_p_f : 1;
 722                u64 pcf_p_e : 1;
 723                u64 rdx_s_e : 1;
 724                u64 rwx_s_e : 1;
 725                u64 pnc_a_f : 1;
 726                u64 pnc_s_e : 1;
 727                u64 com_a_f : 1;
 728                u64 com_s_e : 1;
 729                u64 q3_a_f : 1;
 730                u64 q3_s_e : 1;
 731                u64 q2_a_f : 1;
 732                u64 q2_s_e : 1;
 733                u64 pcr_a_f : 1;
 734                u64 pcr_s_e : 1;
 735                u64 fcr_a_f : 1;
 736                u64 fcr_s_e : 1;
 737                u64 iobdma : 1;
 738                u64 p_dperr : 1;
 739                u64 win_rto : 1;
 740                u64 reserved_36_38 : 3;
 741                u64 i0_pperr : 1;
 742                u64 reserved_32_34 : 3;
 743                u64 p0_ptout : 1;
 744                u64 reserved_28_30 : 3;
 745                u64 p0_pperr : 1;
 746                u64 reserved_24_26 : 3;
 747                u64 g0_rtout : 1;
 748                u64 reserved_20_22 : 3;
 749                u64 p0_perr : 1;
 750                u64 reserved_16_18 : 3;
 751                u64 p0_rtout : 1;
 752                u64 reserved_12_14 : 3;
 753                u64 i0_overf : 1;
 754                u64 reserved_8_10 : 3;
 755                u64 i0_rtout : 1;
 756                u64 reserved_4_6 : 3;
 757                u64 po0_2sml : 1;
 758                u64 pci_rsl : 1;
 759                u64 rml_wto : 1;
 760                u64 rml_rto : 1;
 761        } cn30xx;
 762        struct cvmx_npi_int_enb_cn31xx {
 763                u64 reserved_62_63 : 2;
 764                u64 q1_a_f : 1;
 765                u64 q1_s_e : 1;
 766                u64 pdf_p_f : 1;
 767                u64 pdf_p_e : 1;
 768                u64 pcf_p_f : 1;
 769                u64 pcf_p_e : 1;
 770                u64 rdx_s_e : 1;
 771                u64 rwx_s_e : 1;
 772                u64 pnc_a_f : 1;
 773                u64 pnc_s_e : 1;
 774                u64 com_a_f : 1;
 775                u64 com_s_e : 1;
 776                u64 q3_a_f : 1;
 777                u64 q3_s_e : 1;
 778                u64 q2_a_f : 1;
 779                u64 q2_s_e : 1;
 780                u64 pcr_a_f : 1;
 781                u64 pcr_s_e : 1;
 782                u64 fcr_a_f : 1;
 783                u64 fcr_s_e : 1;
 784                u64 iobdma : 1;
 785                u64 p_dperr : 1;
 786                u64 win_rto : 1;
 787                u64 reserved_37_38 : 2;
 788                u64 i1_pperr : 1;
 789                u64 i0_pperr : 1;
 790                u64 reserved_33_34 : 2;
 791                u64 p1_ptout : 1;
 792                u64 p0_ptout : 1;
 793                u64 reserved_29_30 : 2;
 794                u64 p1_pperr : 1;
 795                u64 p0_pperr : 1;
 796                u64 reserved_25_26 : 2;
 797                u64 g1_rtout : 1;
 798                u64 g0_rtout : 1;
 799                u64 reserved_21_22 : 2;
 800                u64 p1_perr : 1;
 801                u64 p0_perr : 1;
 802                u64 reserved_17_18 : 2;
 803                u64 p1_rtout : 1;
 804                u64 p0_rtout : 1;
 805                u64 reserved_13_14 : 2;
 806                u64 i1_overf : 1;
 807                u64 i0_overf : 1;
 808                u64 reserved_9_10 : 2;
 809                u64 i1_rtout : 1;
 810                u64 i0_rtout : 1;
 811                u64 reserved_5_6 : 2;
 812                u64 po1_2sml : 1;
 813                u64 po0_2sml : 1;
 814                u64 pci_rsl : 1;
 815                u64 rml_wto : 1;
 816                u64 rml_rto : 1;
 817        } cn31xx;
 818        struct cvmx_npi_int_enb_s cn38xx;
 819        struct cvmx_npi_int_enb_cn38xxp2 {
 820                u64 reserved_42_63 : 22;
 821                u64 iobdma : 1;
 822                u64 p_dperr : 1;
 823                u64 win_rto : 1;
 824                u64 i3_pperr : 1;
 825                u64 i2_pperr : 1;
 826                u64 i1_pperr : 1;
 827                u64 i0_pperr : 1;
 828                u64 p3_ptout : 1;
 829                u64 p2_ptout : 1;
 830                u64 p1_ptout : 1;
 831                u64 p0_ptout : 1;
 832                u64 p3_pperr : 1;
 833                u64 p2_pperr : 1;
 834                u64 p1_pperr : 1;
 835                u64 p0_pperr : 1;
 836                u64 g3_rtout : 1;
 837                u64 g2_rtout : 1;
 838                u64 g1_rtout : 1;
 839                u64 g0_rtout : 1;
 840                u64 p3_perr : 1;
 841                u64 p2_perr : 1;
 842                u64 p1_perr : 1;
 843                u64 p0_perr : 1;
 844                u64 p3_rtout : 1;
 845                u64 p2_rtout : 1;
 846                u64 p1_rtout : 1;
 847                u64 p0_rtout : 1;
 848                u64 i3_overf : 1;
 849                u64 i2_overf : 1;
 850                u64 i1_overf : 1;
 851                u64 i0_overf : 1;
 852                u64 i3_rtout : 1;
 853                u64 i2_rtout : 1;
 854                u64 i1_rtout : 1;
 855                u64 i0_rtout : 1;
 856                u64 po3_2sml : 1;
 857                u64 po2_2sml : 1;
 858                u64 po1_2sml : 1;
 859                u64 po0_2sml : 1;
 860                u64 pci_rsl : 1;
 861                u64 rml_wto : 1;
 862                u64 rml_rto : 1;
 863        } cn38xxp2;
 864        struct cvmx_npi_int_enb_cn31xx cn50xx;
 865        struct cvmx_npi_int_enb_s cn58xx;
 866        struct cvmx_npi_int_enb_s cn58xxp1;
 867};
 868
 869typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t;
 870
 871/**
 872 * cvmx_npi_int_sum
 873 *
 874 * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register
 875 *
 876 * Set when an interrupt condition occurs, write '1' to clear.
 877 */
 878union cvmx_npi_int_sum {
 879        u64 u64;
 880        struct cvmx_npi_int_sum_s {
 881                u64 reserved_62_63 : 2;
 882                u64 q1_a_f : 1;
 883                u64 q1_s_e : 1;
 884                u64 pdf_p_f : 1;
 885                u64 pdf_p_e : 1;
 886                u64 pcf_p_f : 1;
 887                u64 pcf_p_e : 1;
 888                u64 rdx_s_e : 1;
 889                u64 rwx_s_e : 1;
 890                u64 pnc_a_f : 1;
 891                u64 pnc_s_e : 1;
 892                u64 com_a_f : 1;
 893                u64 com_s_e : 1;
 894                u64 q3_a_f : 1;
 895                u64 q3_s_e : 1;
 896                u64 q2_a_f : 1;
 897                u64 q2_s_e : 1;
 898                u64 pcr_a_f : 1;
 899                u64 pcr_s_e : 1;
 900                u64 fcr_a_f : 1;
 901                u64 fcr_s_e : 1;
 902                u64 iobdma : 1;
 903                u64 p_dperr : 1;
 904                u64 win_rto : 1;
 905                u64 i3_pperr : 1;
 906                u64 i2_pperr : 1;
 907                u64 i1_pperr : 1;
 908                u64 i0_pperr : 1;
 909                u64 p3_ptout : 1;
 910                u64 p2_ptout : 1;
 911                u64 p1_ptout : 1;
 912                u64 p0_ptout : 1;
 913                u64 p3_pperr : 1;
 914                u64 p2_pperr : 1;
 915                u64 p1_pperr : 1;
 916                u64 p0_pperr : 1;
 917                u64 g3_rtout : 1;
 918                u64 g2_rtout : 1;
 919                u64 g1_rtout : 1;
 920                u64 g0_rtout : 1;
 921                u64 p3_perr : 1;
 922                u64 p2_perr : 1;
 923                u64 p1_perr : 1;
 924                u64 p0_perr : 1;
 925                u64 p3_rtout : 1;
 926                u64 p2_rtout : 1;
 927                u64 p1_rtout : 1;
 928                u64 p0_rtout : 1;
 929                u64 i3_overf : 1;
 930                u64 i2_overf : 1;
 931                u64 i1_overf : 1;
 932                u64 i0_overf : 1;
 933                u64 i3_rtout : 1;
 934                u64 i2_rtout : 1;
 935                u64 i1_rtout : 1;
 936                u64 i0_rtout : 1;
 937                u64 po3_2sml : 1;
 938                u64 po2_2sml : 1;
 939                u64 po1_2sml : 1;
 940                u64 po0_2sml : 1;
 941                u64 pci_rsl : 1;
 942                u64 rml_wto : 1;
 943                u64 rml_rto : 1;
 944        } s;
 945        struct cvmx_npi_int_sum_cn30xx {
 946                u64 reserved_62_63 : 2;
 947                u64 q1_a_f : 1;
 948                u64 q1_s_e : 1;
 949                u64 pdf_p_f : 1;
 950                u64 pdf_p_e : 1;
 951                u64 pcf_p_f : 1;
 952                u64 pcf_p_e : 1;
 953                u64 rdx_s_e : 1;
 954                u64 rwx_s_e : 1;
 955                u64 pnc_a_f : 1;
 956                u64 pnc_s_e : 1;
 957                u64 com_a_f : 1;
 958                u64 com_s_e : 1;
 959                u64 q3_a_f : 1;
 960                u64 q3_s_e : 1;
 961                u64 q2_a_f : 1;
 962                u64 q2_s_e : 1;
 963                u64 pcr_a_f : 1;
 964                u64 pcr_s_e : 1;
 965                u64 fcr_a_f : 1;
 966                u64 fcr_s_e : 1;
 967                u64 iobdma : 1;
 968                u64 p_dperr : 1;
 969                u64 win_rto : 1;
 970                u64 reserved_36_38 : 3;
 971                u64 i0_pperr : 1;
 972                u64 reserved_32_34 : 3;
 973                u64 p0_ptout : 1;
 974                u64 reserved_28_30 : 3;
 975                u64 p0_pperr : 1;
 976                u64 reserved_24_26 : 3;
 977                u64 g0_rtout : 1;
 978                u64 reserved_20_22 : 3;
 979                u64 p0_perr : 1;
 980                u64 reserved_16_18 : 3;
 981                u64 p0_rtout : 1;
 982                u64 reserved_12_14 : 3;
 983                u64 i0_overf : 1;
 984                u64 reserved_8_10 : 3;
 985                u64 i0_rtout : 1;
 986                u64 reserved_4_6 : 3;
 987                u64 po0_2sml : 1;
 988                u64 pci_rsl : 1;
 989                u64 rml_wto : 1;
 990                u64 rml_rto : 1;
 991        } cn30xx;
 992        struct cvmx_npi_int_sum_cn31xx {
 993                u64 reserved_62_63 : 2;
 994                u64 q1_a_f : 1;
 995                u64 q1_s_e : 1;
 996                u64 pdf_p_f : 1;
 997                u64 pdf_p_e : 1;
 998                u64 pcf_p_f : 1;
 999                u64 pcf_p_e : 1;
1000                u64 rdx_s_e : 1;

1001                u64 rwx_s_e : 1;
1002                u64 pnc_a_f : 1;
1003                u64 pnc_s_e : 1;
1004                u64 com_a_f : 1;
1005                u64 com_s_e : 1;
1006                u64 q3_a_f : 1;
1007                u64 q3_s_e : 1;
1008                u64 q2_a_f : 1;
1009                u64 q2_s_e : 1;
1010                u64 pcr_a_f : 1;
1011                u64 pcr_s_e : 1;
1012                u64 fcr_a_f : 1;
1013                u64 fcr_s_e : 1;
1014                u64 iobdma : 1;
1015                u64 p_dperr : 1;
1016                u64 win_rto : 1;
1017                u64 reserved_37_38 : 2;
1018                u64 i1_pperr : 1;
1019                u64 i0_pperr : 1;
1020                u64 reserved_33_34 : 2;
1021                u64 p1_ptout : 1;
1022                u64 p0_ptout : 1;
1023                u64 reserved_29_30 : 2;
1024                u64 p1_pperr : 1;
1025                u64 p0_pperr : 1;
1026                u64 reserved_25_26 : 2;
1027                u64 g1_rtout : 1;
1028                u64 g0_rtout : 1;
1029                u64 reserved_21_22 : 2;
1030                u64 p1_perr : 1;
1031                u64 p0_perr : 1;
1032                u64 reserved_17_18 : 2;
1033                u64 p1_rtout : 1;
1034                u64 p0_rtout : 1;
1035                u64 reserved_13_14 : 2;
1036                u64 i1_overf : 1;
1037                u64 i0_overf : 1;
1038                u64 reserved_9_10 : 2;
1039                u64 i1_rtout : 1;
1040                u64 i0_rtout : 1;
1041                u64 reserved_5_6 : 2;
1042                u64 po1_2sml : 1;
1043                u64 po0_2sml : 1;
1044                u64 pci_rsl : 1;
1045                u64 rml_wto : 1;
1046                u64 rml_rto : 1;
1047        } cn31xx;
1048        struct cvmx_npi_int_sum_s cn38xx;
1049        struct cvmx_npi_int_sum_cn38xxp2 {
1050                u64 reserved_42_63 : 22;
1051                u64 iobdma : 1;
1052                u64 p_dperr : 1;
1053                u64 win_rto : 1;
1054                u64 i3_pperr : 1;
1055                u64 i2_pperr : 1;
1056                u64 i1_pperr : 1;
1057                u64 i0_pperr : 1;
1058                u64 p3_ptout : 1;
1059                u64 p2_ptout : 1;
1060                u64 p1_ptout : 1;
1061                u64 p0_ptout : 1;
1062                u64 p3_pperr : 1;
1063                u64 p2_pperr : 1;
1064                u64 p1_pperr : 1;
1065                u64 p0_pperr : 1;
1066                u64 g3_rtout : 1;
1067                u64 g2_rtout : 1;
1068                u64 g1_rtout : 1;
1069                u64 g0_rtout : 1;
1070                u64 p3_perr : 1;
1071                u64 p2_perr : 1;
1072                u64 p1_perr : 1;
1073                u64 p0_perr : 1;
1074                u64 p3_rtout : 1;
1075                u64 p2_rtout : 1;
1076                u64 p1_rtout : 1;
1077                u64 p0_rtout : 1;
1078                u64 i3_overf : 1;
1079                u64 i2_overf : 1;
1080                u64 i1_overf : 1;
1081                u64 i0_overf : 1;
1082                u64 i3_rtout : 1;
1083                u64 i2_rtout : 1;
1084                u64 i1_rtout : 1;
1085                u64 i0_rtout : 1;
1086                u64 po3_2sml : 1;
1087                u64 po2_2sml : 1;
1088                u64 po1_2sml : 1;
1089                u64 po0_2sml : 1;
1090                u64 pci_rsl : 1;
1091                u64 rml_wto : 1;
1092                u64 rml_rto : 1;
1093        } cn38xxp2;
1094        struct cvmx_npi_int_sum_cn31xx cn50xx;
1095        struct cvmx_npi_int_sum_s cn58xx;
1096        struct cvmx_npi_int_sum_s cn58xxp1;
1097};
1098
1099typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t;
1100
1101/**
1102 * cvmx_npi_lowp_dbell
1103 *
1104 * NPI_LOWP_DBELL = Low Priority Door Bell
1105 *
1106 * The door bell register for the low priority DMA queue.
1107 */
1108union cvmx_npi_lowp_dbell {
1109        u64 u64;
1110        struct cvmx_npi_lowp_dbell_s {
1111                u64 reserved_16_63 : 48;
1112                u64 dbell : 16;
1113        } s;
1114        struct cvmx_npi_lowp_dbell_s cn30xx;
1115        struct cvmx_npi_lowp_dbell_s cn31xx;
1116        struct cvmx_npi_lowp_dbell_s cn38xx;
1117        struct cvmx_npi_lowp_dbell_s cn38xxp2;
1118        struct cvmx_npi_lowp_dbell_s cn50xx;
1119        struct cvmx_npi_lowp_dbell_s cn58xx;
1120        struct cvmx_npi_lowp_dbell_s cn58xxp1;
1121};
1122
1123typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t;
1124
1125/**
1126 * cvmx_npi_lowp_ibuff_saddr
1127 *
1128 * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address
1129 *
1130 * The address to start reading Instructions from for LOWP.
1131 */
1132union cvmx_npi_lowp_ibuff_saddr {
1133        u64 u64;
1134        struct cvmx_npi_lowp_ibuff_saddr_s {
1135                u64 reserved_36_63 : 28;
1136                u64 saddr : 36;
1137        } s;
1138        struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1139        struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1140        struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1141        struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1142        struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1143        struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1144        struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1145};
1146
1147typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t;
1148
1149/**
1150 * cvmx_npi_mem_access_subid#
1151 *
1152 * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register
1153 *
1154 * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.
1155 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
1156 * To ensure that a write has completed the user must read the register before
1157 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
1158 */
1159union cvmx_npi_mem_access_subidx {
1160        u64 u64;
1161        struct cvmx_npi_mem_access_subidx_s {
1162                u64 reserved_38_63 : 26;
1163                u64 shortl : 1;
1164                u64 nmerge : 1;
1165                u64 esr : 2;
1166                u64 esw : 2;
1167                u64 nsr : 1;
1168                u64 nsw : 1;
1169                u64 ror : 1;
1170                u64 row : 1;
1171                u64 ba : 28;
1172        } s;
1173        struct cvmx_npi_mem_access_subidx_s cn30xx;
1174        struct cvmx_npi_mem_access_subidx_cn31xx {
1175                u64 reserved_36_63 : 28;
1176                u64 esr : 2;
1177                u64 esw : 2;
1178                u64 nsr : 1;
1179                u64 nsw : 1;
1180                u64 ror : 1;
1181                u64 row : 1;
1182                u64 ba : 28;
1183        } cn31xx;
1184        struct cvmx_npi_mem_access_subidx_s cn38xx;
1185        struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1186        struct cvmx_npi_mem_access_subidx_s cn50xx;
1187        struct cvmx_npi_mem_access_subidx_s cn58xx;
1188        struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1189};
1190
1191typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t;
1192
1193/**
1194 * cvmx_npi_msi_rcv
1195 *
1196 * NPI_MSI_RCV = NPI MSI Receive Vector Register
1197 *
1198 * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
1199 */
1200union cvmx_npi_msi_rcv {
1201        u64 u64;
1202        struct cvmx_npi_msi_rcv_s {
1203                u64 int_vec : 64;
1204        } s;
1205        struct cvmx_npi_msi_rcv_s cn30xx;
1206        struct cvmx_npi_msi_rcv_s cn31xx;
1207        struct cvmx_npi_msi_rcv_s cn38xx;
1208        struct cvmx_npi_msi_rcv_s cn38xxp2;
1209        struct cvmx_npi_msi_rcv_s cn50xx;
1210        struct cvmx_npi_msi_rcv_s cn58xx;
1211        struct cvmx_npi_msi_rcv_s cn58xxp1;
1212};
1213
1214typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t;
1215
1216/**
1217 * cvmx_npi_num_desc_output#
1218 *
1219 * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0
1220 *
1221 * The size of the Buffer/Info Pointer Pair ring for Output-0.
1222 */
1223union cvmx_npi_num_desc_outputx {
1224        u64 u64;
1225        struct cvmx_npi_num_desc_outputx_s {
1226                u64 reserved_32_63 : 32;
1227                u64 size : 32;
1228        } s;
1229        struct cvmx_npi_num_desc_outputx_s cn30xx;
1230        struct cvmx_npi_num_desc_outputx_s cn31xx;
1231        struct cvmx_npi_num_desc_outputx_s cn38xx;
1232        struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1233        struct cvmx_npi_num_desc_outputx_s cn50xx;
1234        struct cvmx_npi_num_desc_outputx_s cn58xx;
1235        struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1236};
1237
1238typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t;
1239
1240/**
1241 * cvmx_npi_output_control
1242 *
1243 * NPI_OUTPUT_CONTROL = NPI's Output Control Register
1244 *
1245 * The address to start reading Instructions from for Output-3.
1246 */
1247union cvmx_npi_output_control {
1248        u64 u64;
1249        struct cvmx_npi_output_control_s {
1250                u64 reserved_49_63 : 15;
1251                u64 pkt_rr : 1;
1252                u64 p3_bmode : 1;
1253                u64 p2_bmode : 1;
1254                u64 p1_bmode : 1;
1255                u64 p0_bmode : 1;
1256                u64 o3_es : 2;
1257                u64 o3_ns : 1;
1258                u64 o3_ro : 1;
1259                u64 o2_es : 2;
1260                u64 o2_ns : 1;
1261                u64 o2_ro : 1;
1262                u64 o1_es : 2;
1263                u64 o1_ns : 1;
1264                u64 o1_ro : 1;
1265                u64 o0_es : 2;
1266                u64 o0_ns : 1;
1267                u64 o0_ro : 1;
1268                u64 o3_csrm : 1;
1269                u64 o2_csrm : 1;
1270                u64 o1_csrm : 1;
1271                u64 o0_csrm : 1;
1272                u64 reserved_20_23 : 4;
1273                u64 iptr_o3 : 1;
1274                u64 iptr_o2 : 1;
1275                u64 iptr_o1 : 1;
1276                u64 iptr_o0 : 1;
1277                u64 esr_sl3 : 2;
1278                u64 nsr_sl3 : 1;
1279                u64 ror_sl3 : 1;
1280                u64 esr_sl2 : 2;
1281                u64 nsr_sl2 : 1;
1282                u64 ror_sl2 : 1;
1283                u64 esr_sl1 : 2;
1284                u64 nsr_sl1 : 1;
1285                u64 ror_sl1 : 1;
1286                u64 esr_sl0 : 2;
1287                u64 nsr_sl0 : 1;
1288                u64 ror_sl0 : 1;
1289        } s;
1290        struct cvmx_npi_output_control_cn30xx {
1291                u64 reserved_45_63 : 19;
1292                u64 p0_bmode : 1;
1293                u64 reserved_32_43 : 12;
1294                u64 o0_es : 2;
1295                u64 o0_ns : 1;
1296                u64 o0_ro : 1;
1297                u64 reserved_25_27 : 3;
1298                u64 o0_csrm : 1;
1299                u64 reserved_17_23 : 7;
1300                u64 iptr_o0 : 1;
1301                u64 reserved_4_15 : 12;
1302                u64 esr_sl0 : 2;
1303                u64 nsr_sl0 : 1;
1304                u64 ror_sl0 : 1;
1305        } cn30xx;
1306        struct cvmx_npi_output_control_cn31xx {
1307                u64 reserved_46_63 : 18;
1308                u64 p1_bmode : 1;
1309                u64 p0_bmode : 1;
1310                u64 reserved_36_43 : 8;
1311                u64 o1_es : 2;
1312                u64 o1_ns : 1;
1313                u64 o1_ro : 1;
1314                u64 o0_es : 2;
1315                u64 o0_ns : 1;
1316                u64 o0_ro : 1;
1317                u64 reserved_26_27 : 2;
1318                u64 o1_csrm : 1;
1319                u64 o0_csrm : 1;
1320                u64 reserved_18_23 : 6;
1321                u64 iptr_o1 : 1;
1322                u64 iptr_o0 : 1;
1323                u64 reserved_8_15 : 8;
1324                u64 esr_sl1 : 2;
1325                u64 nsr_sl1 : 1;
1326                u64 ror_sl1 : 1;
1327                u64 esr_sl0 : 2;
1328                u64 nsr_sl0 : 1;
1329                u64 ror_sl0 : 1;
1330        } cn31xx;
1331        struct cvmx_npi_output_control_s cn38xx;
1332        struct cvmx_npi_output_control_cn38xxp2 {
1333                u64 reserved_48_63 : 16;
1334                u64 p3_bmode : 1;
1335                u64 p2_bmode : 1;
1336                u64 p1_bmode : 1;
1337                u64 p0_bmode : 1;
1338                u64 o3_es : 2;
1339                u64 o3_ns : 1;
1340                u64 o3_ro : 1;
1341                u64 o2_es : 2;
1342                u64 o2_ns : 1;
1343                u64 o2_ro : 1;
1344                u64 o1_es : 2;
1345                u64 o1_ns : 1;
1346                u64 o1_ro : 1;
1347                u64 o0_es : 2;
1348                u64 o0_ns : 1;
1349                u64 o0_ro : 1;
1350                u64 o3_csrm : 1;
1351                u64 o2_csrm : 1;
1352                u64 o1_csrm : 1;
1353                u64 o0_csrm : 1;
1354                u64 reserved_20_23 : 4;
1355                u64 iptr_o3 : 1;
1356                u64 iptr_o2 : 1;
1357                u64 iptr_o1 : 1;
1358                u64 iptr_o0 : 1;
1359                u64 esr_sl3 : 2;
1360                u64 nsr_sl3 : 1;
1361                u64 ror_sl3 : 1;
1362                u64 esr_sl2 : 2;
1363                u64 nsr_sl2 : 1;
1364                u64 ror_sl2 : 1;
1365                u64 esr_sl1 : 2;
1366                u64 nsr_sl1 : 1;
1367                u64 ror_sl1 : 1;
1368                u64 esr_sl0 : 2;
1369                u64 nsr_sl0 : 1;
1370                u64 ror_sl0 : 1;
1371        } cn38xxp2;
1372        struct cvmx_npi_output_control_cn50xx {
1373                u64 reserved_49_63 : 15;
1374                u64 pkt_rr : 1;
1375                u64 reserved_46_47 : 2;
1376                u64 p1_bmode : 1;
1377                u64 p0_bmode : 1;
1378                u64 reserved_36_43 : 8;
1379                u64 o1_es : 2;
1380                u64 o1_ns : 1;
1381                u64 o1_ro : 1;
1382                u64 o0_es : 2;
1383                u64 o0_ns : 1;
1384                u64 o0_ro : 1;
1385                u64 reserved_26_27 : 2;
1386                u64 o1_csrm : 1;
1387                u64 o0_csrm : 1;
1388                u64 reserved_18_23 : 6;
1389                u64 iptr_o1 : 1;
1390                u64 iptr_o0 : 1;
1391                u64 reserved_8_15 : 8;
1392                u64 esr_sl1 : 2;
1393                u64 nsr_sl1 : 1;
1394                u64 ror_sl1 : 1;
1395                u64 esr_sl0 : 2;
1396                u64 nsr_sl0 : 1;
1397                u64 ror_sl0 : 1;
1398        } cn50xx;
1399        struct cvmx_npi_output_control_s cn58xx;
1400        struct cvmx_npi_output_control_s cn58xxp1;
1401};
1402
1403typedef union cvmx_npi_output_control cvmx_npi_output_control_t;
1404
1405/**
1406 * cvmx_npi_p#_dbpair_addr
1407 *
1408 * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.
1409 *
1410 * Contains the next address to read for Port's-0 Data/Buffer Pair.
1411 */
1412union cvmx_npi_px_dbpair_addr {
1413        u64 u64;
1414        struct cvmx_npi_px_dbpair_addr_s {
1415                u64 reserved_63_63 : 1;
1416                u64 state : 2;
1417                u64 naddr : 61;
1418        } s;
1419        struct cvmx_npi_px_dbpair_addr_s cn30xx;
1420        struct cvmx_npi_px_dbpair_addr_s cn31xx;
1421        struct cvmx_npi_px_dbpair_addr_s cn38xx;
1422        struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1423        struct cvmx_npi_px_dbpair_addr_s cn50xx;
1424        struct cvmx_npi_px_dbpair_addr_s cn58xx;
1425        struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1426};
1427
1428typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t;
1429
1430/**
1431 * cvmx_npi_p#_instr_addr
1432 *
1433 * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.
1434 *
1435 * Contains the next address to read for Port's-0 Instructions.
1436 */
1437union cvmx_npi_px_instr_addr {
1438        u64 u64;
1439        struct cvmx_npi_px_instr_addr_s {
1440                u64 state : 3;
1441                u64 naddr : 61;
1442        } s;
1443        struct cvmx_npi_px_instr_addr_s cn30xx;
1444        struct cvmx_npi_px_instr_addr_s cn31xx;
1445        struct cvmx_npi_px_instr_addr_s cn38xx;
1446        struct cvmx_npi_px_instr_addr_s cn38xxp2;
1447        struct cvmx_npi_px_instr_addr_s cn50xx;
1448        struct cvmx_npi_px_instr_addr_s cn58xx;
1449        struct cvmx_npi_px_instr_addr_s cn58xxp1;
1450};
1451
1452typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t;
1453
1454/**
1455 * cvmx_npi_p#_instr_cnts
1456 *
1457 * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.
1458 *
1459 * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
1460 */
1461union cvmx_npi_px_instr_cnts {
1462        u64 u64;
1463        struct cvmx_npi_px_instr_cnts_s {
1464                u64 reserved_38_63 : 26;
1465                u64 fcnt : 6;
1466                u64 avail : 32;
1467        } s;
1468        struct cvmx_npi_px_instr_cnts_s cn30xx;
1469        struct cvmx_npi_px_instr_cnts_s cn31xx;
1470        struct cvmx_npi_px_instr_cnts_s cn38xx;
1471        struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1472        struct cvmx_npi_px_instr_cnts_s cn50xx;
1473        struct cvmx_npi_px_instr_cnts_s cn58xx;
1474        struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1475};
1476
1477typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t;
1478
1479/**
1480 * cvmx_npi_p#_pair_cnts
1481 *
1482 * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.
1483 *
1484 * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
1485 */
1486union cvmx_npi_px_pair_cnts {
1487        u64 u64;
1488        struct cvmx_npi_px_pair_cnts_s {
1489                u64 reserved_37_63 : 27;
1490                u64 fcnt : 5;
1491                u64 avail : 32;
1492        } s;
1493        struct cvmx_npi_px_pair_cnts_s cn30xx;
1494        struct cvmx_npi_px_pair_cnts_s cn31xx;
1495        struct cvmx_npi_px_pair_cnts_s cn38xx;
1496        struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1497        struct cvmx_npi_px_pair_cnts_s cn50xx;
1498        struct cvmx_npi_px_pair_cnts_s cn58xx;
1499        struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1500};
1501
1502typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t;
1503
1504/**
1505 * cvmx_npi_pci_burst_size
1506 *
1507 * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register
1508 *
1509 * Control the number of words the NPI will attempt to read / write to/from the PCI.
1510 */
1511union cvmx_npi_pci_burst_size {
1512        u64 u64;
1513        struct cvmx_npi_pci_burst_size_s {
1514                u64 reserved_14_63 : 50;
1515                u64 wr_brst : 7;
1516                u64 rd_brst : 7;
1517        } s;
1518        struct cvmx_npi_pci_burst_size_s cn30xx;
1519        struct cvmx_npi_pci_burst_size_s cn31xx;
1520        struct cvmx_npi_pci_burst_size_s cn38xx;
1521        struct cvmx_npi_pci_burst_size_s cn38xxp2;
1522        struct cvmx_npi_pci_burst_size_s cn50xx;
1523        struct cvmx_npi_pci_burst_size_s cn58xx;
1524        struct cvmx_npi_pci_burst_size_s cn58xxp1;
1525};
1526
1527typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t;
1528
1529/**
1530 * cvmx_npi_pci_int_arb_cfg
1531 *
1532 * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter
1533 *
1534 * Controls operation of the Internal PCI Arbiter.  This register should
1535 * only be written when PRST# is asserted.  NPI_PCI_INT_ARB_CFG[EN] should
1536 * only be set when Octane is a host.
1537 */
1538union cvmx_npi_pci_int_arb_cfg {
1539        u64 u64;
1540        struct cvmx_npi_pci_int_arb_cfg_s {
1541                u64 reserved_13_63 : 51;
1542                u64 hostmode : 1;
1543                u64 pci_ovr : 4;
1544                u64 reserved_5_7 : 3;
1545                u64 en : 1;
1546                u64 park_mod : 1;
1547                u64 park_dev : 3;
1548        } s;
1549        struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1550                u64 reserved_5_63 : 59;
1551                u64 en : 1;
1552                u64 park_mod : 1;
1553                u64 park_dev : 3;
1554        } cn30xx;
1555        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1556        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1557        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1558        struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1559        struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1560        struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1561};
1562
1563typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t;
1564
1565/**
1566 * cvmx_npi_pci_read_cmd
1567 *
1568 * NPI_PCI_READ_CMD = NPI PCI Read Command Register
1569 *
1570 * Controls the type of read command sent.
1571 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
1572 * To ensure that a write has completed the user must read the register before
1573 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
1574 * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
1575 * FIFO will use the value of this register after it has been updated.
1576 */
1577union cvmx_npi_pci_read_cmd {
1578        u64 u64;
1579        struct cvmx_npi_pci_read_cmd_s {
1580                u64 reserved_11_63 : 53;
1581                u64 cmd_size : 11;
1582        } s;
1583        struct cvmx_npi_pci_read_cmd_s cn30xx;
1584        struct cvmx_npi_pci_read_cmd_s cn31xx;
1585        struct cvmx_npi_pci_read_cmd_s cn38xx;
1586        struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1587        struct cvmx_npi_pci_read_cmd_s cn50xx;
1588        struct cvmx_npi_pci_read_cmd_s cn58xx;
1589        struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1590};
1591
1592typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t;
1593
1594/**
1595 * cvmx_npi_port32_instr_hdr
1596 *
1597 * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header
1598 *
1599 * Contains bits [62:42] of the Instruction Header for port 32.
1600 */
1601union cvmx_npi_port32_instr_hdr {
1602        u64 u64;
1603        struct cvmx_npi_port32_instr_hdr_s {
1604                u64 reserved_44_63 : 20;
1605                u64 pbp : 1;
1606                u64 rsv_f : 5;
1607                u64 rparmode : 2;
1608                u64 rsv_e : 1;
1609                u64 rskp_len : 7;
1610                u64 rsv_d : 6;
1611                u64 use_ihdr : 1;
1612                u64 rsv_c : 5;
1613                u64 par_mode : 2;
1614                u64 rsv_b : 1;
1615                u64 skp_len : 7;
1616                u64 rsv_a : 6;
1617        } s;
1618        struct cvmx_npi_port32_instr_hdr_s cn30xx;
1619        struct cvmx_npi_port32_instr_hdr_s cn31xx;
1620        struct cvmx_npi_port32_instr_hdr_s cn38xx;
1621        struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1622        struct cvmx_npi_port32_instr_hdr_s cn50xx;
1623        struct cvmx_npi_port32_instr_hdr_s cn58xx;
1624        struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1625};
1626
1627typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t;
1628
1629/**
1630 * cvmx_npi_port33_instr_hdr
1631 *
1632 * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header
1633 *
1634 * Contains bits [62:42] of the Instruction Header for port 33.
1635 */
1636union cvmx_npi_port33_instr_hdr {
1637        u64 u64;
1638        struct cvmx_npi_port33_instr_hdr_s {
1639                u64 reserved_44_63 : 20;
1640                u64 pbp : 1;
1641                u64 rsv_f : 5;
1642                u64 rparmode : 2;
1643                u64 rsv_e : 1;
1644                u64 rskp_len : 7;
1645                u64 rsv_d : 6;
1646                u64 use_ihdr : 1;
1647                u64 rsv_c : 5;
1648                u64 par_mode : 2;
1649                u64 rsv_b : 1;
1650                u64 skp_len : 7;
1651                u64 rsv_a : 6;
1652        } s;
1653        struct cvmx_npi_port33_instr_hdr_s cn31xx;
1654        struct cvmx_npi_port33_instr_hdr_s cn38xx;
1655        struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1656        struct cvmx_npi_port33_instr_hdr_s cn50xx;
1657        struct cvmx_npi_port33_instr_hdr_s cn58xx;
1658        struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1659};
1660
1661typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t;
1662
1663/**
1664 * cvmx_npi_port34_instr_hdr
1665 *
1666 * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header
1667 *
1668 * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
1669 */
1670union cvmx_npi_port34_instr_hdr {
1671        u64 u64;
1672        struct cvmx_npi_port34_instr_hdr_s {
1673                u64 reserved_44_63 : 20;
1674                u64 pbp : 1;
1675                u64 rsv_f : 5;
1676                u64 rparmode : 2;
1677                u64 rsv_e : 1;
1678                u64 rskp_len : 7;
1679                u64 rsv_d : 6;
1680                u64 use_ihdr : 1;
1681                u64 rsv_c : 5;
1682                u64 par_mode : 2;
1683                u64 rsv_b : 1;
1684                u64 skp_len : 7;
1685                u64 rsv_a : 6;
1686        } s;
1687        struct cvmx_npi_port34_instr_hdr_s cn38xx;
1688        struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1689        struct cvmx_npi_port34_instr_hdr_s cn58xx;
1690        struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1691};
1692
1693typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t;
1694
1695/**
1696 * cvmx_npi_port35_instr_hdr
1697 *
1698 * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header
1699 *
1700 * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
1701 */
1702union cvmx_npi_port35_instr_hdr {
1703        u64 u64;
1704        struct cvmx_npi_port35_instr_hdr_s {
1705                u64 reserved_44_63 : 20;
1706                u64 pbp : 1;
1707                u64 rsv_f : 5;
1708                u64 rparmode : 2;
1709                u64 rsv_e : 1;
1710                u64 rskp_len : 7;
1711                u64 rsv_d : 6;
1712                u64 use_ihdr : 1;
1713                u64 rsv_c : 5;
1714                u64 par_mode : 2;
1715                u64 rsv_b : 1;
1716                u64 skp_len : 7;
1717                u64 rsv_a : 6;
1718        } s;
1719        struct cvmx_npi_port35_instr_hdr_s cn38xx;
1720        struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1721        struct cvmx_npi_port35_instr_hdr_s cn58xx;
1722        struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1723};
1724
1725typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t;
1726
1727/**
1728 * cvmx_npi_port_bp_control
1729 *
1730 * NPI_PORT_BP_CONTROL = Port Backpressure Control
1731 *
1732 * Enables Port Level Backpressure
1733 */
1734union cvmx_npi_port_bp_control {
1735        u64 u64;
1736        struct cvmx_npi_port_bp_control_s {
1737                u64 reserved_8_63 : 56;
1738                u64 bp_on : 4;
1739                u64 enb : 4;
1740        } s;
1741        struct cvmx_npi_port_bp_control_s cn30xx;
1742        struct cvmx_npi_port_bp_control_s cn31xx;
1743        struct cvmx_npi_port_bp_control_s cn38xx;
1744        struct cvmx_npi_port_bp_control_s cn38xxp2;
1745        struct cvmx_npi_port_bp_control_s cn50xx;
1746        struct cvmx_npi_port_bp_control_s cn58xx;
1747        struct cvmx_npi_port_bp_control_s cn58xxp1;
1748};
1749
1750typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t;
1751
1752/**
1753 * cvmx_npi_rsl_int_blocks
1754 *
1755 * RSL_INT_BLOCKS = RSL Interrupt Blocks Register
1756 *
1757 * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
1758 * that presently has an interrupt pending. The Field Description below supplies the name of the
1759 * register that software should read to find out why that intterupt bit is set.
1760 */
1761union cvmx_npi_rsl_int_blocks {
1762        u64 u64;
1763        struct cvmx_npi_rsl_int_blocks_s {
1764                u64 reserved_32_63 : 32;
1765                u64 rint_31 : 1;
1766                u64 iob : 1;
1767                u64 reserved_28_29 : 2;
1768                u64 rint_27 : 1;
1769                u64 rint_26 : 1;
1770                u64 rint_25 : 1;
1771                u64 rint_24 : 1;
1772                u64 asx1 : 1;
1773                u64 asx0 : 1;
1774                u64 rint_21 : 1;
1775                u64 pip : 1;
1776                u64 spx1 : 1;
1777                u64 spx0 : 1;
1778                u64 lmc : 1;
1779                u64 l2c : 1;
1780                u64 rint_15 : 1;
1781                u64 reserved_13_14 : 2;
1782                u64 pow : 1;
1783                u64 tim : 1;
1784                u64 pko : 1;
1785                u64 ipd : 1;
1786                u64 rint_8 : 1;
1787                u64 zip : 1;
1788                u64 dfa : 1;
1789                u64 fpa : 1;
1790                u64 key : 1;
1791                u64 npi : 1;
1792                u64 gmx1 : 1;
1793                u64 gmx0 : 1;
1794                u64 mio : 1;
1795        } s;
1796        struct cvmx_npi_rsl_int_blocks_cn30xx {
1797                u64 reserved_32_63 : 32;
1798                u64 rint_31 : 1;
1799                u64 iob : 1;
1800                u64 rint_29 : 1;
1801                u64 rint_28 : 1;
1802                u64 rint_27 : 1;
1803                u64 rint_26 : 1;
1804                u64 rint_25 : 1;
1805                u64 rint_24 : 1;
1806                u64 asx1 : 1;
1807                u64 asx0 : 1;
1808                u64 rint_21 : 1;
1809                u64 pip : 1;
1810                u64 spx1 : 1;
1811                u64 spx0 : 1;
1812                u64 lmc : 1;
1813                u64 l2c : 1;
1814                u64 rint_15 : 1;
1815                u64 rint_14 : 1;
1816                u64 usb : 1;
1817                u64 pow : 1;
1818                u64 tim : 1;
1819                u64 pko : 1;
1820                u64 ipd : 1;
1821                u64 rint_8 : 1;
1822                u64 zip : 1;
1823                u64 dfa : 1;
1824                u64 fpa : 1;
1825                u64 key : 1;
1826                u64 npi : 1;
1827                u64 gmx1 : 1;
1828                u64 gmx0 : 1;
1829                u64 mio : 1;
1830        } cn30xx;
1831        struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1832        struct cvmx_npi_rsl_int_blocks_cn38xx {
1833                u64 reserved_32_63 : 32;
1834                u64 rint_31 : 1;
1835                u64 iob : 1;
1836                u64 rint_29 : 1;
1837                u64 rint_28 : 1;
1838                u64 rint_27 : 1;
1839                u64 rint_26 : 1;
1840                u64 rint_25 : 1;
1841                u64 rint_24 : 1;
1842                u64 asx1 : 1;
1843                u64 asx0 : 1;
1844                u64 rint_21 : 1;
1845                u64 pip : 1;
1846                u64 spx1 : 1;
1847                u64 spx0 : 1;
1848                u64 lmc : 1;
1849                u64 l2c : 1;
1850                u64 rint_15 : 1;
1851                u64 rint_14 : 1;
1852                u64 rint_13 : 1;
1853                u64 pow : 1;
1854                u64 tim : 1;
1855                u64 pko : 1;
1856                u64 ipd : 1;
1857                u64 rint_8 : 1;
1858                u64 zip : 1;
1859                u64 dfa : 1;
1860                u64 fpa : 1;
1861                u64 key : 1;
1862                u64 npi : 1;
1863                u64 gmx1 : 1;
1864                u64 gmx0 : 1;
1865                u64 mio : 1;
1866        } cn38xx;
1867        struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1868        struct cvmx_npi_rsl_int_blocks_cn50xx {
1869                u64 reserved_31_63 : 33;
1870                u64 iob : 1;
1871                u64 lmc1 : 1;
1872                u64 agl : 1;
1873                u64 reserved_24_27 : 4;
1874                u64 asx1 : 1;
1875                u64 asx0 : 1;
1876                u64 reserved_21_21 : 1;
1877                u64 pip : 1;
1878                u64 spx1 : 1;
1879                u64 spx0 : 1;
1880                u64 lmc : 1;
1881                u64 l2c : 1;
1882                u64 reserved_15_15 : 1;
1883                u64 rad : 1;
1884                u64 usb : 1;
1885                u64 pow : 1;
1886                u64 tim : 1;
1887                u64 pko : 1;
1888                u64 ipd : 1;
1889                u64 reserved_8_8 : 1;
1890                u64 zip : 1;
1891                u64 dfa : 1;
1892                u64 fpa : 1;
1893                u64 key : 1;
1894                u64 npi : 1;
1895                u64 gmx1 : 1;
1896                u64 gmx0 : 1;
1897                u64 mio : 1;
1898        } cn50xx;
1899        struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1900        struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1901};
1902
1903typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t;
1904
1905/**
1906 * cvmx_npi_size_input#
1907 *
1908 * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register
1909 *
1910 * The size (in instructions) of Instruction Queue-0.
1911 */
1912union cvmx_npi_size_inputx {
1913        u64 u64;
1914        struct cvmx_npi_size_inputx_s {
1915                u64 reserved_32_63 : 32;
1916                u64 size : 32;
1917        } s;
1918        struct cvmx_npi_size_inputx_s cn30xx;
1919        struct cvmx_npi_size_inputx_s cn31xx;
1920        struct cvmx_npi_size_inputx_s cn38xx;
1921        struct cvmx_npi_size_inputx_s cn38xxp2;
1922        struct cvmx_npi_size_inputx_s cn50xx;
1923        struct cvmx_npi_size_inputx_s cn58xx;
1924        struct cvmx_npi_size_inputx_s cn58xxp1;
1925};
1926
1927typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t;
1928
1929/**
1930 * cvmx_npi_win_read_to
1931 *
1932 * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register
1933 *
1934 * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
1935 */
1936union cvmx_npi_win_read_to {
1937        u64 u64;
1938        struct cvmx_npi_win_read_to_s {
1939                u64 reserved_32_63 : 32;
1940                u64 time : 32;
1941        } s;
1942        struct cvmx_npi_win_read_to_s cn30xx;
1943        struct cvmx_npi_win_read_to_s cn31xx;
1944        struct cvmx_npi_win_read_to_s cn38xx;
1945        struct cvmx_npi_win_read_to_s cn38xxp2;
1946        struct cvmx_npi_win_read_to_s cn50xx;
1947        struct cvmx_npi_win_read_to_s cn58xx;
1948        struct cvmx_npi_win_read_to_s cn58xxp1;
1949};
1950
1951typedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t;
1952
1953#endif
1954