LXR uboot/arch/mips/mach-octeon/include/mach/cvmx-pciercx-defs.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 2020 Marvell International Ltd.
   4 *
   5 * Configuration and status register (CSR) type definitions for
   6 * Octeon pciercx.
   7 */
   8
   9#ifndef __CVMX_PCIERCX_DEFS_H__
  10#define __CVMX_PCIERCX_DEFS_H__
  11
  12static inline u64 CVMX_PCIERCX_CFG000(unsigned long offset)
  13{
  14        switch (cvmx_get_octeon_family()) {
  15        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
  16                return 0x0000020000000000ull + (offset) * 0x100000000ull;
  17        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
  18                return 0x0000020000000000ull + (offset) * 0x100000000ull;
  19        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
  20                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
  21                        return 0x0000020000000000ull + (offset) * 0x100000000ull;
  22                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
  23                        return 0x0000020000000000ull + (offset) * 0x100000000ull;
  24        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
  25                return 0x0000020000000000ull + (offset) * 0x100000000ull;
  26        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  27        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  28        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  29        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  30        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  31                return 0x0000000000000000ull;
  32        }
  33        return 0x0000020000000000ull + (offset) * 0x100000000ull;
  34}
  35
  36static inline u64 CVMX_PCIERCX_CFG001(unsigned long offset)
  37{
  38        switch (cvmx_get_octeon_family()) {
  39        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
  40                return 0x0000020000000004ull + (offset) * 0x100000000ull;
  41        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
  42                return 0x0000020000000004ull + (offset) * 0x100000000ull;
  43        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
  44                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
  45                        return 0x0000020000000004ull + (offset) * 0x100000000ull;
  46                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
  47                        return 0x0000020000000004ull + (offset) * 0x100000000ull;
  48        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
  49                return 0x0000020000000004ull + (offset) * 0x100000000ull;
  50        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  51        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  52        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  53        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  54        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  55                return 0x0000000000000004ull;
  56        }
  57        return 0x0000020000000004ull + (offset) * 0x100000000ull;
  58}
  59
  60static inline u64 CVMX_PCIERCX_CFG002(unsigned long offset)
  61{
  62        switch (cvmx_get_octeon_family()) {
  63        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
  64                return 0x0000020000000008ull + (offset) * 0x100000000ull;
  65        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
  66                return 0x0000020000000008ull + (offset) * 0x100000000ull;
  67        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
  68                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
  69                        return 0x0000020000000008ull + (offset) * 0x100000000ull;
  70                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
  71                        return 0x0000020000000008ull + (offset) * 0x100000000ull;
  72        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
  73                return 0x0000020000000008ull + (offset) * 0x100000000ull;
  74        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  75        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  76        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  77        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  78        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  79                return 0x0000000000000008ull;
  80        }
  81        return 0x0000020000000008ull + (offset) * 0x100000000ull;
  82}
  83
  84static inline u64 CVMX_PCIERCX_CFG003(unsigned long offset)
  85{
  86        switch (cvmx_get_octeon_family()) {
  87        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
  88                return 0x000002000000000Cull + (offset) * 0x100000000ull;
  89        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
  90                return 0x000002000000000Cull + (offset) * 0x100000000ull;
  91        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
  92                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
  93                        return 0x000002000000000Cull + (offset) * 0x100000000ull;
  94                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
  95                        return 0x000002000000000Cull + (offset) * 0x100000000ull;
  96        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
  97                return 0x000002000000000Cull + (offset) * 0x100000000ull;
  98        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  99        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 100        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 101        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 102        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 103                return 0x000000000000000Cull;
 104        }
 105        return 0x000002000000000Cull + (offset) * 0x100000000ull;
 106}
 107
 108static inline u64 CVMX_PCIERCX_CFG004(unsigned long offset)
 109{
 110        switch (cvmx_get_octeon_family()) {
 111        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 112                return 0x0000020000000010ull + (offset) * 0x100000000ull;
 113        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 114                return 0x0000020000000010ull + (offset) * 0x100000000ull;
 115        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 116                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 117                        return 0x0000020000000010ull + (offset) * 0x100000000ull;
 118                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 119                        return 0x0000020000000010ull + (offset) * 0x100000000ull;
 120        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 121                return 0x0000020000000010ull + (offset) * 0x100000000ull;
 122        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 123        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 124        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 125        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 126        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 127                return 0x0000000000000010ull;
 128        }
 129        return 0x0000020000000010ull + (offset) * 0x100000000ull;
 130}
 131
 132static inline u64 CVMX_PCIERCX_CFG005(unsigned long offset)
 133{
 134        switch (cvmx_get_octeon_family()) {
 135        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 136                return 0x0000020000000014ull + (offset) * 0x100000000ull;
 137        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 138                return 0x0000020000000014ull + (offset) * 0x100000000ull;
 139        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 140                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 141                        return 0x0000020000000014ull + (offset) * 0x100000000ull;
 142                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 143                        return 0x0000020000000014ull + (offset) * 0x100000000ull;
 144        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 145                return 0x0000020000000014ull + (offset) * 0x100000000ull;
 146        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 147        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 148        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 149        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 150        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 151                return 0x0000000000000014ull;
 152        }
 153        return 0x0000020000000014ull + (offset) * 0x100000000ull;
 154}
 155
 156static inline u64 CVMX_PCIERCX_CFG006(unsigned long offset)
 157{
 158        switch (cvmx_get_octeon_family()) {
 159        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 160                return 0x0000020000000018ull + (offset) * 0x100000000ull;
 161        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 162                return 0x0000020000000018ull + (offset) * 0x100000000ull;
 163        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 164                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 165                        return 0x0000020000000018ull + (offset) * 0x100000000ull;
 166                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 167                        return 0x0000020000000018ull + (offset) * 0x100000000ull;
 168        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 169                return 0x0000020000000018ull + (offset) * 0x100000000ull;
 170        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 171        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 172        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 173        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 174        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 175                return 0x0000000000000018ull;
 176        }
 177        return 0x0000020000000018ull + (offset) * 0x100000000ull;
 178}
 179
 180static inline u64 CVMX_PCIERCX_CFG007(unsigned long offset)
 181{
 182        switch (cvmx_get_octeon_family()) {
 183        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 184                return 0x000002000000001Cull + (offset) * 0x100000000ull;
 185        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 186                return 0x000002000000001Cull + (offset) * 0x100000000ull;
 187        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 188                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 189                        return 0x000002000000001Cull + (offset) * 0x100000000ull;
 190                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 191                        return 0x000002000000001Cull + (offset) * 0x100000000ull;
 192        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 193                return 0x000002000000001Cull + (offset) * 0x100000000ull;
 194        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 195        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 196        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 197        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 198        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 199                return 0x000000000000001Cull;
 200        }
 201        return 0x000002000000001Cull + (offset) * 0x100000000ull;
 202}
 203
 204static inline u64 CVMX_PCIERCX_CFG008(unsigned long offset)
 205{
 206        switch (cvmx_get_octeon_family()) {
 207        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 208                return 0x0000020000000020ull + (offset) * 0x100000000ull;
 209        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 210                return 0x0000020000000020ull + (offset) * 0x100000000ull;
 211        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 212                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 213                        return 0x0000020000000020ull + (offset) * 0x100000000ull;
 214                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 215                        return 0x0000020000000020ull + (offset) * 0x100000000ull;
 216        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 217                return 0x0000020000000020ull + (offset) * 0x100000000ull;
 218        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 219        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 220        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 221        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 222        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 223                return 0x0000000000000020ull;
 224        }
 225        return 0x0000020000000020ull + (offset) * 0x100000000ull;
 226}
 227
 228static inline u64 CVMX_PCIERCX_CFG009(unsigned long offset)
 229{
 230        switch (cvmx_get_octeon_family()) {
 231        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 232                return 0x0000020000000024ull + (offset) * 0x100000000ull;
 233        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 234                return 0x0000020000000024ull + (offset) * 0x100000000ull;
 235        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 236                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 237                        return 0x0000020000000024ull + (offset) * 0x100000000ull;
 238                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 239                        return 0x0000020000000024ull + (offset) * 0x100000000ull;
 240        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 241                return 0x0000020000000024ull + (offset) * 0x100000000ull;
 242        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 243        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 244        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 245        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 246        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 247                return 0x0000000000000024ull;
 248        }
 249        return 0x0000020000000024ull + (offset) * 0x100000000ull;
 250}
 251
 252static inline u64 CVMX_PCIERCX_CFG010(unsigned long offset)
 253{
 254        switch (cvmx_get_octeon_family()) {
 255        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 256                return 0x0000020000000028ull + (offset) * 0x100000000ull;
 257        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 258                return 0x0000020000000028ull + (offset) * 0x100000000ull;
 259        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 260                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 261                        return 0x0000020000000028ull + (offset) * 0x100000000ull;
 262                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 263                        return 0x0000020000000028ull + (offset) * 0x100000000ull;
 264        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 265                return 0x0000020000000028ull + (offset) * 0x100000000ull;
 266        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 267        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 268        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 269        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 270        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 271                return 0x0000000000000028ull;
 272        }
 273        return 0x0000020000000028ull + (offset) * 0x100000000ull;
 274}
 275
 276static inline u64 CVMX_PCIERCX_CFG011(unsigned long offset)
 277{
 278        switch (cvmx_get_octeon_family()) {
 279        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 280                return 0x000002000000002Cull + (offset) * 0x100000000ull;
 281        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 282                return 0x000002000000002Cull + (offset) * 0x100000000ull;
 283        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 284                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 285                        return 0x000002000000002Cull + (offset) * 0x100000000ull;
 286                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 287                        return 0x000002000000002Cull + (offset) * 0x100000000ull;
 288        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 289                return 0x000002000000002Cull + (offset) * 0x100000000ull;
 290        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 291        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 292        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 293        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 294        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 295                return 0x000000000000002Cull;
 296        }
 297        return 0x000002000000002Cull + (offset) * 0x100000000ull;
 298}
 299
 300static inline u64 CVMX_PCIERCX_CFG012(unsigned long offset)
 301{
 302        switch (cvmx_get_octeon_family()) {
 303        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 304                return 0x0000020000000030ull + (offset) * 0x100000000ull;
 305        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 306                return 0x0000020000000030ull + (offset) * 0x100000000ull;
 307        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 308                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 309                        return 0x0000020000000030ull + (offset) * 0x100000000ull;
 310                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 311                        return 0x0000020000000030ull + (offset) * 0x100000000ull;
 312        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 313                return 0x0000020000000030ull + (offset) * 0x100000000ull;
 314        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 315        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 316        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 317        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 318        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 319                return 0x0000000000000030ull;
 320        }
 321        return 0x0000020000000030ull + (offset) * 0x100000000ull;
 322}
 323
 324static inline u64 CVMX_PCIERCX_CFG013(unsigned long offset)
 325{
 326        switch (cvmx_get_octeon_family()) {
 327        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 328                return 0x0000020000000034ull + (offset) * 0x100000000ull;
 329        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 330                return 0x0000020000000034ull + (offset) * 0x100000000ull;
 331        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 332                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 333                        return 0x0000020000000034ull + (offset) * 0x100000000ull;
 334                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 335                        return 0x0000020000000034ull + (offset) * 0x100000000ull;
 336        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 337                return 0x0000020000000034ull + (offset) * 0x100000000ull;
 338        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 339        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 340        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 341        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 342        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 343                return 0x0000000000000034ull;
 344        }
 345        return 0x0000020000000034ull + (offset) * 0x100000000ull;
 346}
 347
 348static inline u64 CVMX_PCIERCX_CFG014(unsigned long offset)
 349{
 350        switch (cvmx_get_octeon_family()) {
 351        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 352                return 0x0000020000000038ull + (offset) * 0x100000000ull;
 353        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 354                return 0x0000020000000038ull + (offset) * 0x100000000ull;
 355        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 356                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 357                        return 0x0000020000000038ull + (offset) * 0x100000000ull;
 358                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 359                        return 0x0000020000000038ull + (offset) * 0x100000000ull;
 360        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 361                return 0x0000020000000038ull + (offset) * 0x100000000ull;
 362        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 363        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 364        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 365        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 366        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 367                return 0x0000000000000038ull;
 368        }
 369        return 0x0000020000000038ull + (offset) * 0x100000000ull;
 370}
 371
 372static inline u64 CVMX_PCIERCX_CFG015(unsigned long offset)
 373{
 374        switch (cvmx_get_octeon_family()) {
 375        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 376                return 0x000002000000003Cull + (offset) * 0x100000000ull;
 377        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 378                return 0x000002000000003Cull + (offset) * 0x100000000ull;
 379        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 380                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 381                        return 0x000002000000003Cull + (offset) * 0x100000000ull;
 382                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 383                        return 0x000002000000003Cull + (offset) * 0x100000000ull;
 384        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 385                return 0x000002000000003Cull + (offset) * 0x100000000ull;
 386        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 387        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 388        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 389        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 390        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 391                return 0x000000000000003Cull;
 392        }
 393        return 0x000002000000003Cull + (offset) * 0x100000000ull;
 394}
 395
 396static inline u64 CVMX_PCIERCX_CFG016(unsigned long offset)
 397{
 398        switch (cvmx_get_octeon_family()) {
 399        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 400                return 0x0000020000000040ull + (offset) * 0x100000000ull;
 401        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 402                return 0x0000020000000040ull + (offset) * 0x100000000ull;
 403        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 404                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 405                        return 0x0000020000000040ull + (offset) * 0x100000000ull;
 406                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 407                        return 0x0000020000000040ull + (offset) * 0x100000000ull;
 408        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 409                return 0x0000020000000040ull + (offset) * 0x100000000ull;
 410        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 411        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 412        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 413        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 414        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 415                return 0x0000000000000040ull;
 416        }
 417        return 0x0000020000000040ull + (offset) * 0x100000000ull;
 418}
 419
 420static inline u64 CVMX_PCIERCX_CFG017(unsigned long offset)
 421{
 422        switch (cvmx_get_octeon_family()) {
 423        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 424                return 0x0000020000000044ull + (offset) * 0x100000000ull;
 425        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 426                return 0x0000020000000044ull + (offset) * 0x100000000ull;
 427        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 428                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 429                        return 0x0000020000000044ull + (offset) * 0x100000000ull;
 430                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 431                        return 0x0000020000000044ull + (offset) * 0x100000000ull;
 432        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 433                return 0x0000020000000044ull + (offset) * 0x100000000ull;
 434        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 435        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 436        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 437        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 438        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 439                return 0x0000000000000044ull;
 440        }
 441        return 0x0000020000000044ull + (offset) * 0x100000000ull;
 442}
 443
 444static inline u64 CVMX_PCIERCX_CFG020(unsigned long offset)
 445{
 446        switch (cvmx_get_octeon_family()) {
 447        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 448                return 0x0000020000000050ull + (offset) * 0x100000000ull;
 449        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 450                return 0x0000020000000050ull + (offset) * 0x100000000ull;
 451        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 452                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 453                        return 0x0000020000000050ull + (offset) * 0x100000000ull;
 454                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 455                        return 0x0000020000000050ull + (offset) * 0x100000000ull;
 456        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 457                return 0x0000020000000050ull + (offset) * 0x100000000ull;
 458        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 459        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 460        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 461        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 462        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 463                return 0x0000000000000050ull;
 464        }
 465        return 0x0000020000000050ull + (offset) * 0x100000000ull;
 466}
 467
 468static inline u64 CVMX_PCIERCX_CFG021(unsigned long offset)
 469{
 470        switch (cvmx_get_octeon_family()) {
 471        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 472                return 0x0000020000000054ull + (offset) * 0x100000000ull;
 473        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 474                return 0x0000020000000054ull + (offset) * 0x100000000ull;
 475        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 476                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 477                        return 0x0000020000000054ull + (offset) * 0x100000000ull;
 478                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 479                        return 0x0000020000000054ull + (offset) * 0x100000000ull;
 480        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 481                return 0x0000020000000054ull + (offset) * 0x100000000ull;
 482        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 483        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 484        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 485        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 486        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 487                return 0x0000000000000054ull;
 488        }
 489        return 0x0000020000000054ull + (offset) * 0x100000000ull;
 490}
 491
 492static inline u64 CVMX_PCIERCX_CFG022(unsigned long offset)
 493{
 494        switch (cvmx_get_octeon_family()) {
 495        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 496                return 0x0000020000000058ull + (offset) * 0x100000000ull;
 497        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 498                return 0x0000020000000058ull + (offset) * 0x100000000ull;
 499        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 500                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 501                        return 0x0000020000000058ull + (offset) * 0x100000000ull;
 502                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 503                        return 0x0000020000000058ull + (offset) * 0x100000000ull;
 504        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 505                return 0x0000020000000058ull + (offset) * 0x100000000ull;
 506        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 507        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 508        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 509        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 510        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 511                return 0x0000000000000058ull;
 512        }
 513        return 0x0000020000000058ull + (offset) * 0x100000000ull;
 514}
 515
 516static inline u64 CVMX_PCIERCX_CFG023(unsigned long offset)
 517{
 518        switch (cvmx_get_octeon_family()) {
 519        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 520                return 0x000002000000005Cull + (offset) * 0x100000000ull;
 521        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 522                return 0x000002000000005Cull + (offset) * 0x100000000ull;
 523        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 524                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 525                        return 0x000002000000005Cull + (offset) * 0x100000000ull;
 526                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 527                        return 0x000002000000005Cull + (offset) * 0x100000000ull;
 528        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 529                return 0x000002000000005Cull + (offset) * 0x100000000ull;
 530        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 531        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 532        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 533        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 534        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 535                return 0x000000000000005Cull;
 536        }
 537        return 0x000002000000005Cull + (offset) * 0x100000000ull;
 538}
 539
 540static inline u64 CVMX_PCIERCX_CFG028(unsigned long offset)
 541{
 542        switch (cvmx_get_octeon_family()) {
 543        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 544                return 0x0000020000000070ull + (offset) * 0x100000000ull;
 545        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 546                return 0x0000020000000070ull + (offset) * 0x100000000ull;
 547        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 548                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 549                        return 0x0000020000000070ull + (offset) * 0x100000000ull;
 550                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 551                        return 0x0000020000000070ull + (offset) * 0x100000000ull;
 552        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 553                return 0x0000020000000070ull + (offset) * 0x100000000ull;
 554        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 555        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 556        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 557        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 558        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 559                return 0x0000000000000070ull;
 560        }
 561        return 0x0000020000000070ull + (offset) * 0x100000000ull;
 562}
 563
 564static inline u64 CVMX_PCIERCX_CFG029(unsigned long offset)
 565{
 566        switch (cvmx_get_octeon_family()) {
 567        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 568                return 0x0000020000000074ull + (offset) * 0x100000000ull;
 569        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 570                return 0x0000020000000074ull + (offset) * 0x100000000ull;
 571        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 572                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 573                        return 0x0000020000000074ull + (offset) * 0x100000000ull;
 574                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 575                        return 0x0000020000000074ull + (offset) * 0x100000000ull;
 576        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 577                return 0x0000020000000074ull + (offset) * 0x100000000ull;
 578        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 579        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 580        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 581        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 582        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 583                return 0x0000000000000074ull;
 584        }
 585        return 0x0000020000000074ull + (offset) * 0x100000000ull;
 586}
 587
 588static inline u64 CVMX_PCIERCX_CFG030(unsigned long offset)
 589{
 590        switch (cvmx_get_octeon_family()) {
 591        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 592                return 0x0000020000000078ull + (offset) * 0x100000000ull;
 593        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 594                return 0x0000020000000078ull + (offset) * 0x100000000ull;
 595        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 596                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 597                        return 0x0000020000000078ull + (offset) * 0x100000000ull;
 598                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 599                        return 0x0000020000000078ull + (offset) * 0x100000000ull;
 600        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 601                return 0x0000020000000078ull + (offset) * 0x100000000ull;
 602        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 603        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 604        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 605        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 606        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 607                return 0x0000000000000078ull;
 608        }
 609        return 0x0000020000000078ull + (offset) * 0x100000000ull;
 610}
 611
 612static inline u64 CVMX_PCIERCX_CFG031(unsigned long offset)
 613{
 614        switch (cvmx_get_octeon_family()) {
 615        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 616                return 0x000002000000007Cull + (offset) * 0x100000000ull;
 617        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 618                return 0x000002000000007Cull + (offset) * 0x100000000ull;
 619        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 620                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 621                        return 0x000002000000007Cull + (offset) * 0x100000000ull;
 622                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 623                        return 0x000002000000007Cull + (offset) * 0x100000000ull;
 624        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 625                return 0x000002000000007Cull + (offset) * 0x100000000ull;
 626        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 627        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 628        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 629        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 630        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 631                return 0x000000000000007Cull;
 632        }
 633        return 0x000002000000007Cull + (offset) * 0x100000000ull;
 634}
 635
 636static inline u64 CVMX_PCIERCX_CFG032(unsigned long offset)
 637{
 638        switch (cvmx_get_octeon_family()) {
 639        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 640                return 0x0000020000000080ull + (offset) * 0x100000000ull;
 641        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 642                return 0x0000020000000080ull + (offset) * 0x100000000ull;
 643        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 644                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 645                        return 0x0000020000000080ull + (offset) * 0x100000000ull;
 646                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 647                        return 0x0000020000000080ull + (offset) * 0x100000000ull;
 648        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 649                return 0x0000020000000080ull + (offset) * 0x100000000ull;
 650        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 651        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 652        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 653        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 654        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 655                return 0x0000000000000080ull;
 656        }
 657        return 0x0000020000000080ull + (offset) * 0x100000000ull;
 658}
 659
 660static inline u64 CVMX_PCIERCX_CFG033(unsigned long offset)
 661{
 662        switch (cvmx_get_octeon_family()) {
 663        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 664                return 0x0000020000000084ull + (offset) * 0x100000000ull;
 665        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 666                return 0x0000020000000084ull + (offset) * 0x100000000ull;
 667        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 668                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 669                        return 0x0000020000000084ull + (offset) * 0x100000000ull;
 670                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 671                        return 0x0000020000000084ull + (offset) * 0x100000000ull;
 672        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 673                return 0x0000020000000084ull + (offset) * 0x100000000ull;
 674        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 675        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 676        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 677        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 678        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 679                return 0x0000000000000084ull;
 680        }
 681        return 0x0000020000000084ull + (offset) * 0x100000000ull;
 682}
 683
 684static inline u64 CVMX_PCIERCX_CFG034(unsigned long offset)
 685{
 686        switch (cvmx_get_octeon_family()) {
 687        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 688                return 0x0000020000000088ull + (offset) * 0x100000000ull;
 689        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 690                return 0x0000020000000088ull + (offset) * 0x100000000ull;
 691        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 692                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 693                        return 0x0000020000000088ull + (offset) * 0x100000000ull;
 694                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 695                        return 0x0000020000000088ull + (offset) * 0x100000000ull;
 696        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 697                return 0x0000020000000088ull + (offset) * 0x100000000ull;
 698        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 699        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 700        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 701        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 702        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 703                return 0x0000000000000088ull;
 704        }
 705        return 0x0000020000000088ull + (offset) * 0x100000000ull;
 706}
 707
 708static inline u64 CVMX_PCIERCX_CFG035(unsigned long offset)
 709{
 710        switch (cvmx_get_octeon_family()) {
 711        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 712                return 0x000002000000008Cull + (offset) * 0x100000000ull;
 713        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 714                return 0x000002000000008Cull + (offset) * 0x100000000ull;
 715        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 716                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 717                        return 0x000002000000008Cull + (offset) * 0x100000000ull;
 718                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 719                        return 0x000002000000008Cull + (offset) * 0x100000000ull;
 720        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 721                return 0x000002000000008Cull + (offset) * 0x100000000ull;
 722        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 723        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 724        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 725        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 726        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 727                return 0x000000000000008Cull;
 728        }
 729        return 0x000002000000008Cull + (offset) * 0x100000000ull;
 730}
 731
 732static inline u64 CVMX_PCIERCX_CFG036(unsigned long offset)
 733{
 734        switch (cvmx_get_octeon_family()) {
 735        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 736                return 0x0000020000000090ull + (offset) * 0x100000000ull;
 737        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 738                return 0x0000020000000090ull + (offset) * 0x100000000ull;
 739        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 740                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 741                        return 0x0000020000000090ull + (offset) * 0x100000000ull;
 742                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 743                        return 0x0000020000000090ull + (offset) * 0x100000000ull;
 744        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 745                return 0x0000020000000090ull + (offset) * 0x100000000ull;
 746        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 747        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 748        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 749        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 750        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 751                return 0x0000000000000090ull;
 752        }
 753        return 0x0000020000000090ull + (offset) * 0x100000000ull;
 754}
 755
 756static inline u64 CVMX_PCIERCX_CFG037(unsigned long offset)
 757{
 758        switch (cvmx_get_octeon_family()) {
 759        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 760                return 0x0000020000000094ull + (offset) * 0x100000000ull;
 761        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 762                return 0x0000020000000094ull + (offset) * 0x100000000ull;
 763        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 764                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 765                        return 0x0000020000000094ull + (offset) * 0x100000000ull;
 766                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 767                        return 0x0000020000000094ull + (offset) * 0x100000000ull;
 768        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 769                return 0x0000020000000094ull + (offset) * 0x100000000ull;
 770        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 771        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 772        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 773        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 774        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 775                return 0x0000000000000094ull;
 776        }
 777        return 0x0000020000000094ull + (offset) * 0x100000000ull;
 778}
 779
 780static inline u64 CVMX_PCIERCX_CFG038(unsigned long offset)
 781{
 782        switch (cvmx_get_octeon_family()) {
 783        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 784                return 0x0000020000000098ull + (offset) * 0x100000000ull;
 785        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 786                return 0x0000020000000098ull + (offset) * 0x100000000ull;
 787        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 788                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 789                        return 0x0000020000000098ull + (offset) * 0x100000000ull;
 790                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 791                        return 0x0000020000000098ull + (offset) * 0x100000000ull;
 792        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 793                return 0x0000020000000098ull + (offset) * 0x100000000ull;
 794        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 795        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 796        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 797        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 798        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 799                return 0x0000000000000098ull;
 800        }
 801        return 0x0000020000000098ull + (offset) * 0x100000000ull;
 802}
 803
 804static inline u64 CVMX_PCIERCX_CFG039(unsigned long offset)
 805{
 806        switch (cvmx_get_octeon_family()) {
 807        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 808                return 0x000002000000009Cull + (offset) * 0x100000000ull;
 809        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 810                return 0x000002000000009Cull + (offset) * 0x100000000ull;
 811        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 812                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 813                        return 0x000002000000009Cull + (offset) * 0x100000000ull;
 814                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 815                        return 0x000002000000009Cull + (offset) * 0x100000000ull;
 816        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 817                return 0x000002000000009Cull + (offset) * 0x100000000ull;
 818        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 819        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 820        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 821        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 822        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 823                return 0x000000000000009Cull;
 824        }
 825        return 0x000002000000009Cull + (offset) * 0x100000000ull;
 826}
 827
 828static inline u64 CVMX_PCIERCX_CFG040(unsigned long offset)
 829{
 830        switch (cvmx_get_octeon_family()) {
 831        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 832                return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 833        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 834                return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 835        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 836                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 837                        return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 838                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 839                        return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 840        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 841                return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 842        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 843        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 844        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 845        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 846        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 847                return 0x00000000000000A0ull;
 848        }
 849        return 0x00000200000000A0ull + (offset) * 0x100000000ull;
 850}
 851
 852static inline u64 CVMX_PCIERCX_CFG041(unsigned long offset)
 853{
 854        switch (cvmx_get_octeon_family()) {
 855        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 856                return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 857        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 858                return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 859        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 860                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 861                        return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 862                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 863                        return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 864        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 865                return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 866        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 867        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 868        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 869        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 870        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 871                return 0x00000000000000A4ull;
 872        }
 873        return 0x00000200000000A4ull + (offset) * 0x100000000ull;
 874}
 875
 876static inline u64 CVMX_PCIERCX_CFG042(unsigned long offset)
 877{
 878        switch (cvmx_get_octeon_family()) {
 879        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 880                return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 881        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 882                return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 883        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 884                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 885                        return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 886                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 887                        return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 888        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 889                return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 890        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 891        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 892        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 893        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 894        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 895                return 0x00000000000000A8ull;
 896        }
 897        return 0x00000200000000A8ull + (offset) * 0x100000000ull;
 898}
 899
 900#define CVMX_PCIERCX_CFG044(offset) (0x00000200000000B0ull + ((offset) & 3) * 0x100000000ull)
 901#define CVMX_PCIERCX_CFG045(offset) (0x00000200000000B4ull + ((offset) & 3) * 0x100000000ull)
 902#define CVMX_PCIERCX_CFG046(offset) (0x00000200000000B8ull + ((offset) & 3) * 0x100000000ull)
 903static inline u64 CVMX_PCIERCX_CFG064(unsigned long offset)
 904{
 905        switch (cvmx_get_octeon_family()) {
 906        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 907                return 0x0000020000000100ull + (offset) * 0x100000000ull;
 908        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 909                return 0x0000020000000100ull + (offset) * 0x100000000ull;
 910        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 911                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 912                        return 0x0000020000000100ull + (offset) * 0x100000000ull;
 913                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 914                        return 0x0000020000000100ull + (offset) * 0x100000000ull;
 915        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 916                return 0x0000020000000100ull + (offset) * 0x100000000ull;
 917        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 918        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 919        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 920        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 921        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 922                return 0x0000000000000100ull;
 923        }
 924        return 0x0000020000000100ull + (offset) * 0x100000000ull;
 925}
 926
 927static inline u64 CVMX_PCIERCX_CFG065(unsigned long offset)
 928{
 929        switch (cvmx_get_octeon_family()) {
 930        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 931                return 0x0000020000000104ull + (offset) * 0x100000000ull;
 932        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 933                return 0x0000020000000104ull + (offset) * 0x100000000ull;
 934        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 935                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 936                        return 0x0000020000000104ull + (offset) * 0x100000000ull;
 937                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 938                        return 0x0000020000000104ull + (offset) * 0x100000000ull;
 939        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 940                return 0x0000020000000104ull + (offset) * 0x100000000ull;
 941        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 942        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 943        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 944        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 945        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 946                return 0x0000000000000104ull;
 947        }
 948        return 0x0000020000000104ull + (offset) * 0x100000000ull;
 949}
 950
 951static inline u64 CVMX_PCIERCX_CFG066(unsigned long offset)
 952{
 953        switch (cvmx_get_octeon_family()) {
 954        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 955                return 0x0000020000000108ull + (offset) * 0x100000000ull;
 956        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 957                return 0x0000020000000108ull + (offset) * 0x100000000ull;
 958        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 959                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 960                        return 0x0000020000000108ull + (offset) * 0x100000000ull;
 961                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 962                        return 0x0000020000000108ull + (offset) * 0x100000000ull;
 963        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 964                return 0x0000020000000108ull + (offset) * 0x100000000ull;
 965        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 966        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 967        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 968        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 969        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 970                return 0x0000000000000108ull;
 971        }
 972        return 0x0000020000000108ull + (offset) * 0x100000000ull;
 973}
 974
 975static inline u64 CVMX_PCIERCX_CFG067(unsigned long offset)
 976{
 977        switch (cvmx_get_octeon_family()) {
 978        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
 979                return 0x000002000000010Cull + (offset) * 0x100000000ull;
 980        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
 981                return 0x000002000000010Cull + (offset) * 0x100000000ull;
 982        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
 983                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
 984                        return 0x000002000000010Cull + (offset) * 0x100000000ull;
 985                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 986                        return 0x000002000000010Cull + (offset) * 0x100000000ull;
 987        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
 988                return 0x000002000000010Cull + (offset) * 0x100000000ull;
 989        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 990        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 991        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 992        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 993        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 994                return 0x000000000000010Cull;
 995        }
 996        return 0x000002000000010Cull + (offset) * 0x100000000ull;
 997}
 998
 999static inline u64 CVMX_PCIERCX_CFG068(unsigned long offset)
1000{

1001        switch (cvmx_get_octeon_family()) {
1002        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1003                return 0x0000020000000110ull + (offset) * 0x100000000ull;
1004        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1005                return 0x0000020000000110ull + (offset) * 0x100000000ull;
1006        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1007                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1008                        return 0x0000020000000110ull + (offset) * 0x100000000ull;
1009                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1010                        return 0x0000020000000110ull + (offset) * 0x100000000ull;
1011        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1012                return 0x0000020000000110ull + (offset) * 0x100000000ull;
1013        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1014        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1015        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1016        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1017        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1018                return 0x0000000000000110ull;
1019        }
1020        return 0x0000020000000110ull + (offset) * 0x100000000ull;
1021}
1022
1023static inline u64 CVMX_PCIERCX_CFG069(unsigned long offset)
1024{
1025        switch (cvmx_get_octeon_family()) {
1026        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1027                return 0x0000020000000114ull + (offset) * 0x100000000ull;
1028        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1029                return 0x0000020000000114ull + (offset) * 0x100000000ull;
1030        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1031                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1032                        return 0x0000020000000114ull + (offset) * 0x100000000ull;
1033                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1034                        return 0x0000020000000114ull + (offset) * 0x100000000ull;
1035        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1036                return 0x0000020000000114ull + (offset) * 0x100000000ull;
1037        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1038        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1039        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1040        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1041        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1042                return 0x0000000000000114ull;
1043        }
1044        return 0x0000020000000114ull + (offset) * 0x100000000ull;
1045}
1046
1047static inline u64 CVMX_PCIERCX_CFG070(unsigned long offset)
1048{
1049        switch (cvmx_get_octeon_family()) {
1050        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1051                return 0x0000020000000118ull + (offset) * 0x100000000ull;
1052        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1053                return 0x0000020000000118ull + (offset) * 0x100000000ull;
1054        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1055                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1056                        return 0x0000020000000118ull + (offset) * 0x100000000ull;
1057                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1058                        return 0x0000020000000118ull + (offset) * 0x100000000ull;
1059        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1060                return 0x0000020000000118ull + (offset) * 0x100000000ull;
1061        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1062        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1063        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1064        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1065        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1066                return 0x0000000000000118ull;
1067        }
1068        return 0x0000020000000118ull + (offset) * 0x100000000ull;
1069}
1070
1071static inline u64 CVMX_PCIERCX_CFG071(unsigned long offset)
1072{
1073        switch (cvmx_get_octeon_family()) {
1074        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1075                return 0x000002000000011Cull + (offset) * 0x100000000ull;
1076        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1077                return 0x000002000000011Cull + (offset) * 0x100000000ull;
1078        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1079                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1080                        return 0x000002000000011Cull + (offset) * 0x100000000ull;
1081                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1082                        return 0x000002000000011Cull + (offset) * 0x100000000ull;
1083        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1084                return 0x000002000000011Cull + (offset) * 0x100000000ull;
1085        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1086        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1087        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1088        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1089        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1090                return 0x000000000000011Cull;
1091        }
1092        return 0x000002000000011Cull + (offset) * 0x100000000ull;
1093}
1094
1095static inline u64 CVMX_PCIERCX_CFG072(unsigned long offset)
1096{
1097        switch (cvmx_get_octeon_family()) {
1098        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1099                return 0x0000020000000120ull + (offset) * 0x100000000ull;
1100        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1101                return 0x0000020000000120ull + (offset) * 0x100000000ull;
1102        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1103                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1104                        return 0x0000020000000120ull + (offset) * 0x100000000ull;
1105                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1106                        return 0x0000020000000120ull + (offset) * 0x100000000ull;
1107        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1108                return 0x0000020000000120ull + (offset) * 0x100000000ull;
1109        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1110        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1111        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1112        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1113        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1114                return 0x0000000000000120ull;
1115        }
1116        return 0x0000020000000120ull + (offset) * 0x100000000ull;
1117}
1118
1119static inline u64 CVMX_PCIERCX_CFG073(unsigned long offset)
1120{
1121        switch (cvmx_get_octeon_family()) {
1122        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1123                return 0x0000020000000124ull + (offset) * 0x100000000ull;
1124        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1125                return 0x0000020000000124ull + (offset) * 0x100000000ull;
1126        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1127                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1128                        return 0x0000020000000124ull + (offset) * 0x100000000ull;
1129                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1130                        return 0x0000020000000124ull + (offset) * 0x100000000ull;
1131        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1132                return 0x0000020000000124ull + (offset) * 0x100000000ull;
1133        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1134        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1135        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1136        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1137        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1138                return 0x0000000000000124ull;
1139        }
1140        return 0x0000020000000124ull + (offset) * 0x100000000ull;
1141}
1142
1143static inline u64 CVMX_PCIERCX_CFG074(unsigned long offset)
1144{
1145        switch (cvmx_get_octeon_family()) {
1146        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1147                return 0x0000020000000128ull + (offset) * 0x100000000ull;
1148        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1149                return 0x0000020000000128ull + (offset) * 0x100000000ull;
1150        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1151                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1152                        return 0x0000020000000128ull + (offset) * 0x100000000ull;
1153                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1154                        return 0x0000020000000128ull + (offset) * 0x100000000ull;
1155        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1156                return 0x0000020000000128ull + (offset) * 0x100000000ull;
1157        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1158        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1159        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1160        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1161        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1162                return 0x0000000000000128ull;
1163        }
1164        return 0x0000020000000128ull + (offset) * 0x100000000ull;
1165}
1166
1167static inline u64 CVMX_PCIERCX_CFG075(unsigned long offset)
1168{
1169        switch (cvmx_get_octeon_family()) {
1170        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1171                return 0x000002000000012Cull + (offset) * 0x100000000ull;
1172        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1173                return 0x000002000000012Cull + (offset) * 0x100000000ull;
1174        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1175                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1176                        return 0x000002000000012Cull + (offset) * 0x100000000ull;
1177                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1178                        return 0x000002000000012Cull + (offset) * 0x100000000ull;
1179        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1180                return 0x000002000000012Cull + (offset) * 0x100000000ull;
1181        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1182        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1183        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1184        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1185        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1186                return 0x000000000000012Cull;
1187        }
1188        return 0x000002000000012Cull + (offset) * 0x100000000ull;
1189}
1190
1191static inline u64 CVMX_PCIERCX_CFG076(unsigned long offset)
1192{
1193        switch (cvmx_get_octeon_family()) {
1194        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1195                return 0x0000020000000130ull + (offset) * 0x100000000ull;
1196        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1197                return 0x0000020000000130ull + (offset) * 0x100000000ull;
1198        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1199                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1200                        return 0x0000020000000130ull + (offset) * 0x100000000ull;
1201                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1202                        return 0x0000020000000130ull + (offset) * 0x100000000ull;
1203        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1204                return 0x0000020000000130ull + (offset) * 0x100000000ull;
1205        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1206        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1207        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1208        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1209        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1210                return 0x0000000000000130ull;
1211        }
1212        return 0x0000020000000130ull + (offset) * 0x100000000ull;
1213}
1214
1215static inline u64 CVMX_PCIERCX_CFG077(unsigned long offset)
1216{
1217        switch (cvmx_get_octeon_family()) {
1218        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1219                return 0x0000020000000134ull + (offset) * 0x100000000ull;
1220        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1221                return 0x0000020000000134ull + (offset) * 0x100000000ull;
1222        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1223                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1224                        return 0x0000020000000134ull + (offset) * 0x100000000ull;
1225                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1226                        return 0x0000020000000134ull + (offset) * 0x100000000ull;
1227        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1228                return 0x0000020000000134ull + (offset) * 0x100000000ull;
1229        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1230        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1231        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1232        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1233        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1234                return 0x0000000000000134ull;
1235        }
1236        return 0x0000020000000134ull + (offset) * 0x100000000ull;
1237}
1238
1239#define CVMX_PCIERCX_CFG086(offset) (0x0000020000000158ull + ((offset) & 3) * 0x100000000ull)
1240#define CVMX_PCIERCX_CFG087(offset) (0x000002000000015Cull + ((offset) & 3) * 0x100000000ull)
1241#define CVMX_PCIERCX_CFG088(offset) (0x0000020000000160ull + ((offset) & 3) * 0x100000000ull)
1242#define CVMX_PCIERCX_CFG089(offset) (0x0000020000000164ull + ((offset) & 3) * 0x100000000ull)
1243#define CVMX_PCIERCX_CFG090(offset) (0x0000020000000168ull + ((offset) & 3) * 0x100000000ull)
1244#define CVMX_PCIERCX_CFG091(offset) (0x000002000000016Cull + ((offset) & 3) * 0x100000000ull)
1245#define CVMX_PCIERCX_CFG092(offset) (0x0000020000000170ull + ((offset) & 3) * 0x100000000ull)
1246static inline u64 CVMX_PCIERCX_CFG448(unsigned long offset)
1247{
1248        switch (cvmx_get_octeon_family()) {
1249        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1250                return 0x0000020000000700ull + (offset) * 0x100000000ull;
1251        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1252                return 0x0000020000000700ull + (offset) * 0x100000000ull;
1253        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1254                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1255                        return 0x0000020000000700ull + (offset) * 0x100000000ull;
1256                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1257                        return 0x0000020000000700ull + (offset) * 0x100000000ull;
1258        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1259                return 0x0000020000000700ull + (offset) * 0x100000000ull;
1260        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1261        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1262        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1263        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1264        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1265                return 0x0000000000000700ull;
1266        }
1267        return 0x0000020000000700ull + (offset) * 0x100000000ull;
1268}
1269
1270static inline u64 CVMX_PCIERCX_CFG449(unsigned long offset)
1271{
1272        switch (cvmx_get_octeon_family()) {
1273        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1274                return 0x0000020000000704ull + (offset) * 0x100000000ull;
1275        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1276                return 0x0000020000000704ull + (offset) * 0x100000000ull;
1277        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1278                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1279                        return 0x0000020000000704ull + (offset) * 0x100000000ull;
1280                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1281                        return 0x0000020000000704ull + (offset) * 0x100000000ull;
1282        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1283                return 0x0000020000000704ull + (offset) * 0x100000000ull;
1284        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1285        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1286        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1287        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1288        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1289                return 0x0000000000000704ull;
1290        }
1291        return 0x0000020000000704ull + (offset) * 0x100000000ull;
1292}
1293
1294static inline u64 CVMX_PCIERCX_CFG450(unsigned long offset)
1295{
1296        switch (cvmx_get_octeon_family()) {
1297        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1298                return 0x0000020000000708ull + (offset) * 0x100000000ull;
1299        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1300                return 0x0000020000000708ull + (offset) * 0x100000000ull;
1301        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1302                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1303                        return 0x0000020000000708ull + (offset) * 0x100000000ull;
1304                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1305                        return 0x0000020000000708ull + (offset) * 0x100000000ull;
1306        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1307                return 0x0000020000000708ull + (offset) * 0x100000000ull;
1308        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1309        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1310        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1311        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1312        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1313                return 0x0000000000000708ull;
1314        }
1315        return 0x0000020000000708ull + (offset) * 0x100000000ull;
1316}
1317
1318static inline u64 CVMX_PCIERCX_CFG451(unsigned long offset)
1319{
1320        switch (cvmx_get_octeon_family()) {
1321        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1322                return 0x000002000000070Cull + (offset) * 0x100000000ull;
1323        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1324                return 0x000002000000070Cull + (offset) * 0x100000000ull;
1325        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1326                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1327                        return 0x000002000000070Cull + (offset) * 0x100000000ull;
1328                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1329                        return 0x000002000000070Cull + (offset) * 0x100000000ull;
1330        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1331                return 0x000002000000070Cull + (offset) * 0x100000000ull;
1332        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1333        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1334        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1335        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1336        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1337                return 0x000000000000070Cull;
1338        }
1339        return 0x000002000000070Cull + (offset) * 0x100000000ull;
1340}
1341
1342static inline u64 CVMX_PCIERCX_CFG452(unsigned long offset)
1343{
1344        switch (cvmx_get_octeon_family()) {
1345        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1346                return 0x0000020000000710ull + (offset) * 0x100000000ull;
1347        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1348                return 0x0000020000000710ull + (offset) * 0x100000000ull;
1349        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1350                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1351                        return 0x0000020000000710ull + (offset) * 0x100000000ull;
1352                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1353                        return 0x0000020000000710ull + (offset) * 0x100000000ull;
1354        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1355                return 0x0000020000000710ull + (offset) * 0x100000000ull;
1356        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1357        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1358        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1359        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1360        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1361                return 0x0000000000000710ull;
1362        }
1363        return 0x0000020000000710ull + (offset) * 0x100000000ull;
1364}
1365
1366static inline u64 CVMX_PCIERCX_CFG453(unsigned long offset)
1367{
1368        switch (cvmx_get_octeon_family()) {
1369        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1370                return 0x0000020000000714ull + (offset) * 0x100000000ull;
1371        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1372                return 0x0000020000000714ull + (offset) * 0x100000000ull;
1373        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1374                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1375                        return 0x0000020000000714ull + (offset) * 0x100000000ull;
1376                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1377                        return 0x0000020000000714ull + (offset) * 0x100000000ull;
1378        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1379                return 0x0000020000000714ull + (offset) * 0x100000000ull;
1380        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1381        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1382        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1383        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1384        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1385                return 0x0000000000000714ull;
1386        }
1387        return 0x0000020000000714ull + (offset) * 0x100000000ull;
1388}
1389
1390static inline u64 CVMX_PCIERCX_CFG454(unsigned long offset)
1391{
1392        switch (cvmx_get_octeon_family()) {
1393        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1394                return 0x0000020000000718ull + (offset) * 0x100000000ull;
1395        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1396                return 0x0000020000000718ull + (offset) * 0x100000000ull;
1397        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1398                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1399                        return 0x0000020000000718ull + (offset) * 0x100000000ull;
1400                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1401                        return 0x0000020000000718ull + (offset) * 0x100000000ull;
1402        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1403                return 0x0000020000000718ull + (offset) * 0x100000000ull;
1404        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1405        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1406        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1407        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1408        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1409                return 0x0000000000000718ull;
1410        }
1411        return 0x0000020000000718ull + (offset) * 0x100000000ull;
1412}
1413
1414static inline u64 CVMX_PCIERCX_CFG455(unsigned long offset)
1415{
1416        switch (cvmx_get_octeon_family()) {
1417        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1418                return 0x000002000000071Cull + (offset) * 0x100000000ull;
1419        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1420                return 0x000002000000071Cull + (offset) * 0x100000000ull;
1421        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1422                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1423                        return 0x000002000000071Cull + (offset) * 0x100000000ull;
1424                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1425                        return 0x000002000000071Cull + (offset) * 0x100000000ull;
1426        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1427                return 0x000002000000071Cull + (offset) * 0x100000000ull;
1428        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1429        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1430        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1431        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1432        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1433                return 0x000000000000071Cull;
1434        }
1435        return 0x000002000000071Cull + (offset) * 0x100000000ull;
1436}
1437
1438static inline u64 CVMX_PCIERCX_CFG456(unsigned long offset)
1439{
1440        switch (cvmx_get_octeon_family()) {
1441        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1442                return 0x0000020000000720ull + (offset) * 0x100000000ull;
1443        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1444                return 0x0000020000000720ull + (offset) * 0x100000000ull;
1445        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1446                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1447                        return 0x0000020000000720ull + (offset) * 0x100000000ull;
1448                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1449                        return 0x0000020000000720ull + (offset) * 0x100000000ull;
1450        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1451                return 0x0000020000000720ull + (offset) * 0x100000000ull;
1452        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1453        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1454        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1455        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1456        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1457                return 0x0000000000000720ull;
1458        }
1459        return 0x0000020000000720ull + (offset) * 0x100000000ull;
1460}
1461
1462static inline u64 CVMX_PCIERCX_CFG458(unsigned long offset)
1463{
1464        switch (cvmx_get_octeon_family()) {
1465        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1466                return 0x0000020000000728ull + (offset) * 0x100000000ull;
1467        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1468                return 0x0000020000000728ull + (offset) * 0x100000000ull;
1469        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1470                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1471                        return 0x0000020000000728ull + (offset) * 0x100000000ull;
1472                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1473                        return 0x0000020000000728ull + (offset) * 0x100000000ull;
1474        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1475                return 0x0000020000000728ull + (offset) * 0x100000000ull;
1476        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1477        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1478        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1479        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1480        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1481                return 0x0000000000000728ull;
1482        }
1483        return 0x0000020000000728ull + (offset) * 0x100000000ull;
1484}
1485
1486static inline u64 CVMX_PCIERCX_CFG459(unsigned long offset)
1487{
1488        switch (cvmx_get_octeon_family()) {
1489        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1490                return 0x000002000000072Cull + (offset) * 0x100000000ull;
1491        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1492                return 0x000002000000072Cull + (offset) * 0x100000000ull;
1493        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1494                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1495                        return 0x000002000000072Cull + (offset) * 0x100000000ull;
1496                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1497                        return 0x000002000000072Cull + (offset) * 0x100000000ull;
1498        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1499                return 0x000002000000072Cull + (offset) * 0x100000000ull;
1500        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1501        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1502        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1503        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1504        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1505                return 0x000000000000072Cull;
1506        }
1507        return 0x000002000000072Cull + (offset) * 0x100000000ull;
1508}
1509
1510static inline u64 CVMX_PCIERCX_CFG460(unsigned long offset)
1511{
1512        switch (cvmx_get_octeon_family()) {
1513        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1514                return 0x0000020000000730ull + (offset) * 0x100000000ull;
1515        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1516                return 0x0000020000000730ull + (offset) * 0x100000000ull;
1517        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1518                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1519                        return 0x0000020000000730ull + (offset) * 0x100000000ull;
1520                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1521                        return 0x0000020000000730ull + (offset) * 0x100000000ull;
1522        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1523                return 0x0000020000000730ull + (offset) * 0x100000000ull;
1524        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1525        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1526        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1527        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1528        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1529                return 0x0000000000000730ull;
1530        }
1531        return 0x0000020000000730ull + (offset) * 0x100000000ull;
1532}
1533
1534static inline u64 CVMX_PCIERCX_CFG461(unsigned long offset)
1535{
1536        switch (cvmx_get_octeon_family()) {
1537        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1538                return 0x0000020000000734ull + (offset) * 0x100000000ull;
1539        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1540                return 0x0000020000000734ull + (offset) * 0x100000000ull;
1541        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1542                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1543                        return 0x0000020000000734ull + (offset) * 0x100000000ull;
1544                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1545                        return 0x0000020000000734ull + (offset) * 0x100000000ull;
1546        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1547                return 0x0000020000000734ull + (offset) * 0x100000000ull;
1548        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1549        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1550        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1551        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1552        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1553                return 0x0000000000000734ull;
1554        }
1555        return 0x0000020000000734ull + (offset) * 0x100000000ull;
1556}
1557
1558static inline u64 CVMX_PCIERCX_CFG462(unsigned long offset)
1559{
1560        switch (cvmx_get_octeon_family()) {
1561        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1562                return 0x0000020000000738ull + (offset) * 0x100000000ull;
1563        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1564                return 0x0000020000000738ull + (offset) * 0x100000000ull;
1565        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1566                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1567                        return 0x0000020000000738ull + (offset) * 0x100000000ull;
1568                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1569                        return 0x0000020000000738ull + (offset) * 0x100000000ull;
1570        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1571                return 0x0000020000000738ull + (offset) * 0x100000000ull;
1572        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1573        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1574        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1575        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1576        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1577                return 0x0000000000000738ull;
1578        }
1579        return 0x0000020000000738ull + (offset) * 0x100000000ull;
1580}
1581
1582static inline u64 CVMX_PCIERCX_CFG463(unsigned long offset)
1583{
1584        switch (cvmx_get_octeon_family()) {
1585        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1586                return 0x000002000000073Cull + (offset) * 0x100000000ull;
1587        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1588                return 0x000002000000073Cull + (offset) * 0x100000000ull;
1589        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1590                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1591                        return 0x000002000000073Cull + (offset) * 0x100000000ull;
1592                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1593                        return 0x000002000000073Cull + (offset) * 0x100000000ull;
1594        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1595                return 0x000002000000073Cull + (offset) * 0x100000000ull;
1596        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1597        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1598        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1599        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1600        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1601                return 0x000000000000073Cull;
1602        }
1603        return 0x000002000000073Cull + (offset) * 0x100000000ull;
1604}
1605
1606static inline u64 CVMX_PCIERCX_CFG464(unsigned long offset)
1607{
1608        switch (cvmx_get_octeon_family()) {
1609        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1610                return 0x0000020000000740ull + (offset) * 0x100000000ull;
1611        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1612                return 0x0000020000000740ull + (offset) * 0x100000000ull;
1613        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1614                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1615                        return 0x0000020000000740ull + (offset) * 0x100000000ull;
1616                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1617                        return 0x0000020000000740ull + (offset) * 0x100000000ull;
1618        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1619                return 0x0000020000000740ull + (offset) * 0x100000000ull;
1620        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1621        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1622        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1623        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1624        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1625                return 0x0000000000000740ull;
1626        }
1627        return 0x0000020000000740ull + (offset) * 0x100000000ull;
1628}
1629
1630static inline u64 CVMX_PCIERCX_CFG465(unsigned long offset)
1631{
1632        switch (cvmx_get_octeon_family()) {
1633        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1634                return 0x0000020000000744ull + (offset) * 0x100000000ull;
1635        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1636                return 0x0000020000000744ull + (offset) * 0x100000000ull;
1637        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1638                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1639                        return 0x0000020000000744ull + (offset) * 0x100000000ull;
1640                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1641                        return 0x0000020000000744ull + (offset) * 0x100000000ull;
1642        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1643                return 0x0000020000000744ull + (offset) * 0x100000000ull;
1644        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1645        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1646        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1647        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1648        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1649                return 0x0000000000000744ull;
1650        }
1651        return 0x0000020000000744ull + (offset) * 0x100000000ull;
1652}
1653
1654static inline u64 CVMX_PCIERCX_CFG466(unsigned long offset)
1655{
1656        switch (cvmx_get_octeon_family()) {
1657        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1658                return 0x0000020000000748ull + (offset) * 0x100000000ull;
1659        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1660                return 0x0000020000000748ull + (offset) * 0x100000000ull;
1661        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1662                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1663                        return 0x0000020000000748ull + (offset) * 0x100000000ull;
1664                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1665                        return 0x0000020000000748ull + (offset) * 0x100000000ull;
1666        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1667                return 0x0000020000000748ull + (offset) * 0x100000000ull;
1668        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1669        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1670        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1671        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1672        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1673                return 0x0000000000000748ull;
1674        }
1675        return 0x0000020000000748ull + (offset) * 0x100000000ull;
1676}
1677
1678static inline u64 CVMX_PCIERCX_CFG467(unsigned long offset)
1679{
1680        switch (cvmx_get_octeon_family()) {
1681        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1682                return 0x000002000000074Cull + (offset) * 0x100000000ull;
1683        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1684                return 0x000002000000074Cull + (offset) * 0x100000000ull;
1685        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1686                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1687                        return 0x000002000000074Cull + (offset) * 0x100000000ull;
1688                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1689                        return 0x000002000000074Cull + (offset) * 0x100000000ull;
1690        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1691                return 0x000002000000074Cull + (offset) * 0x100000000ull;
1692        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1693        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1694        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1695        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1696        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1697                return 0x000000000000074Cull;
1698        }
1699        return 0x000002000000074Cull + (offset) * 0x100000000ull;
1700}
1701
1702static inline u64 CVMX_PCIERCX_CFG468(unsigned long offset)
1703{
1704        switch (cvmx_get_octeon_family()) {
1705        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1706                return 0x0000020000000750ull + (offset) * 0x100000000ull;
1707        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1708                return 0x0000020000000750ull + (offset) * 0x100000000ull;
1709        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1710                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1711                        return 0x0000020000000750ull + (offset) * 0x100000000ull;
1712                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1713                        return 0x0000020000000750ull + (offset) * 0x100000000ull;
1714        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1715                return 0x0000020000000750ull + (offset) * 0x100000000ull;
1716        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1717        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1718        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1719        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1720        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1721                return 0x0000000000000750ull;
1722        }
1723        return 0x0000020000000750ull + (offset) * 0x100000000ull;
1724}
1725
1726static inline u64 CVMX_PCIERCX_CFG490(unsigned long offset)
1727{
1728        switch (cvmx_get_octeon_family()) {
1729        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1730        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1731        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1732        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1733        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1734                return 0x00000000000007A8ull;
1735        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1736                return 0x00000200000007A8ull + (offset) * 0x100000000ull;
1737        }
1738        return 0x00000000000007A8ull;
1739}
1740
1741static inline u64 CVMX_PCIERCX_CFG491(unsigned long offset)
1742{
1743        switch (cvmx_get_octeon_family()) {
1744        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1745        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1746        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1747        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1748        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1749                return 0x00000000000007ACull;
1750        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1751                return 0x00000200000007ACull + (offset) * 0x100000000ull;
1752        }
1753        return 0x00000000000007ACull;
1754}
1755
1756static inline u64 CVMX_PCIERCX_CFG492(unsigned long offset)
1757{
1758        switch (cvmx_get_octeon_family()) {
1759        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1760        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1761        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1762        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1763        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1764                return 0x00000000000007B0ull;
1765        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1766                return 0x00000200000007B0ull + (offset) * 0x100000000ull;
1767        }
1768        return 0x00000000000007B0ull;
1769}
1770
1771static inline u64 CVMX_PCIERCX_CFG515(unsigned long offset)
1772{
1773        switch (cvmx_get_octeon_family()) {
1774        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1775                return 0x000002000000080Cull + (offset) * 0x100000000ull;
1776        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1777                return 0x000002000000080Cull + (offset) * 0x100000000ull;
1778        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1779                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1780                        return 0x000002000000080Cull + (offset) * 0x100000000ull;
1781                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1782                        return 0x000002000000080Cull + (offset) * 0x100000000ull;
1783        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1784                return 0x000002000000080Cull + (offset) * 0x100000000ull;
1785        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1786        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1787        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1788        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1789        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1790                return 0x000000000000080Cull;
1791        }
1792        return 0x000002000000080Cull + (offset) * 0x100000000ull;
1793}
1794
1795static inline u64 CVMX_PCIERCX_CFG516(unsigned long offset)
1796{
1797        switch (cvmx_get_octeon_family()) {
1798        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1799                return 0x0000020000000810ull + (offset) * 0x100000000ull;
1800        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1801                return 0x0000020000000810ull + (offset) * 0x100000000ull;
1802        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1803                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1804                        return 0x0000020000000810ull + (offset) * 0x100000000ull;
1805                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1806                        return 0x0000020000000810ull + (offset) * 0x100000000ull;
1807        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1808                return 0x0000020000000810ull + (offset) * 0x100000000ull;
1809        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1810        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1811        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1812        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1813        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1814                return 0x0000000000000810ull;
1815        }
1816        return 0x0000020000000810ull + (offset) * 0x100000000ull;
1817}
1818
1819static inline u64 CVMX_PCIERCX_CFG517(unsigned long offset)
1820{
1821        switch (cvmx_get_octeon_family()) {
1822        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1823                return 0x0000020000000814ull + (offset) * 0x100000000ull;
1824        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1825                return 0x0000020000000814ull + (offset) * 0x100000000ull;
1826        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1827                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1828                        return 0x0000020000000814ull + (offset) * 0x100000000ull;
1829                if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1830                        return 0x0000020000000814ull + (offset) * 0x100000000ull;
1831        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1832                return 0x0000020000000814ull + (offset) * 0x100000000ull;
1833        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1834        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1835        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1836        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1837        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1838                return 0x0000000000000814ull;
1839        }
1840        return 0x0000020000000814ull + (offset) * 0x100000000ull;
1841}
1842
1843#define CVMX_PCIERCX_CFG548(offset) (0x0000020000000890ull + ((offset) & 3) * 0x100000000ull)
1844#define CVMX_PCIERCX_CFG554(offset) (0x00000200000008A8ull + ((offset) & 3) * 0x100000000ull)
1845#define CVMX_PCIERCX_CFG558(offset) (0x00000200000008B8ull + ((offset) & 3) * 0x100000000ull)
1846#define CVMX_PCIERCX_CFG559(offset) (0x00000200000008BCull + ((offset) & 3) * 0x100000000ull)
1847
1848/**
1849 * cvmx_pcierc#_cfg000
1850 *
1851 * This register contains the first 32-bits of PCIe type 1 configuration space.
1852 *
1853 */
1854union cvmx_pciercx_cfg000 {
1855        u32 u32;
1856        struct cvmx_pciercx_cfg000_s {
1857                u32 devid : 16;
1858                u32 vendid : 16;
1859        } s;
1860        struct cvmx_pciercx_cfg000_s cn52xx;
1861        struct cvmx_pciercx_cfg000_s cn52xxp1;
1862        struct cvmx_pciercx_cfg000_s cn56xx;
1863        struct cvmx_pciercx_cfg000_s cn56xxp1;
1864        struct cvmx_pciercx_cfg000_s cn61xx;
1865        struct cvmx_pciercx_cfg000_s cn63xx;
1866        struct cvmx_pciercx_cfg000_s cn63xxp1;
1867        struct cvmx_pciercx_cfg000_s cn66xx;
1868        struct cvmx_pciercx_cfg000_s cn68xx;
1869        struct cvmx_pciercx_cfg000_s cn68xxp1;
1870        struct cvmx_pciercx_cfg000_s cn70xx;
1871        struct cvmx_pciercx_cfg000_s cn70xxp1;
1872        struct cvmx_pciercx_cfg000_s cn73xx;
1873        struct cvmx_pciercx_cfg000_s cn78xx;
1874        struct cvmx_pciercx_cfg000_s cn78xxp1;
1875        struct cvmx_pciercx_cfg000_s cnf71xx;
1876        struct cvmx_pciercx_cfg000_s cnf75xx;
1877};
1878
1879typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t;
1880
1881/**
1882 * cvmx_pcierc#_cfg001
1883 *
1884 * This register contains the second 32-bits of PCIe type 1 configuration space.
1885 *
1886 */
1887union cvmx_pciercx_cfg001 {
1888        u32 u32;
1889        struct cvmx_pciercx_cfg001_s {
1890                u32 dpe : 1;
1891                u32 sse : 1;
1892                u32 rma : 1;
1893                u32 rta : 1;
1894                u32 sta : 1;
1895                u32 devt : 2;
1896                u32 mdpe : 1;
1897                u32 fbb : 1;
1898                u32 reserved_22_22 : 1;
1899                u32 m66 : 1;
1900                u32 cl : 1;
1901                u32 i_stat : 1;
1902                u32 reserved_11_18 : 8;
1903                u32 i_dis : 1;
1904                u32 fbbe : 1;
1905                u32 see : 1;
1906                u32 ids_wcc : 1;
1907                u32 per : 1;
1908                u32 vps : 1;
1909                u32 mwice : 1;
1910                u32 scse : 1;
1911                u32 me : 1;
1912                u32 msae : 1;
1913                u32 isae : 1;
1914        } s;
1915        struct cvmx_pciercx_cfg001_s cn52xx;
1916        struct cvmx_pciercx_cfg001_s cn52xxp1;
1917        struct cvmx_pciercx_cfg001_s cn56xx;
1918        struct cvmx_pciercx_cfg001_s cn56xxp1;
1919        struct cvmx_pciercx_cfg001_s cn61xx;
1920        struct cvmx_pciercx_cfg001_s cn63xx;
1921        struct cvmx_pciercx_cfg001_s cn63xxp1;
1922        struct cvmx_pciercx_cfg001_s cn66xx;
1923        struct cvmx_pciercx_cfg001_s cn68xx;
1924        struct cvmx_pciercx_cfg001_s cn68xxp1;
1925        struct cvmx_pciercx_cfg001_s cn70xx;
1926        struct cvmx_pciercx_cfg001_s cn70xxp1;
1927        struct cvmx_pciercx_cfg001_s cn73xx;
1928        struct cvmx_pciercx_cfg001_s cn78xx;
1929        struct cvmx_pciercx_cfg001_s cn78xxp1;
1930        struct cvmx_pciercx_cfg001_s cnf71xx;
1931        struct cvmx_pciercx_cfg001_s cnf75xx;
1932};
1933
1934typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t;
1935
1936/**
1937 * cvmx_pcierc#_cfg002
1938 *
1939 * This register contains the third 32-bits of PCIe type 1 configuration space.
1940 *
1941 */
1942union cvmx_pciercx_cfg002 {
1943        u32 u32;
1944        struct cvmx_pciercx_cfg002_s {
1945                u32 bcc : 8;
1946                u32 sc : 8;
1947                u32 pi : 8;
1948                u32 rid : 8;
1949        } s;
1950        struct cvmx_pciercx_cfg002_s cn52xx;
1951        struct cvmx_pciercx_cfg002_s cn52xxp1;
1952        struct cvmx_pciercx_cfg002_s cn56xx;
1953        struct cvmx_pciercx_cfg002_s cn56xxp1;
1954        struct cvmx_pciercx_cfg002_s cn61xx;
1955        struct cvmx_pciercx_cfg002_s cn63xx;
1956        struct cvmx_pciercx_cfg002_s cn63xxp1;
1957        struct cvmx_pciercx_cfg002_s cn66xx;
1958        struct cvmx_pciercx_cfg002_s cn68xx;
1959        struct cvmx_pciercx_cfg002_s cn68xxp1;
1960        struct cvmx_pciercx_cfg002_s cn70xx;
1961        struct cvmx_pciercx_cfg002_s cn70xxp1;
1962        struct cvmx_pciercx_cfg002_s cn73xx;
1963        struct cvmx_pciercx_cfg002_s cn78xx;
1964        struct cvmx_pciercx_cfg002_s cn78xxp1;
1965        struct cvmx_pciercx_cfg002_s cnf71xx;
1966        struct cvmx_pciercx_cfg002_s cnf75xx;
1967};
1968
1969typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t;
1970
1971/**
1972 * cvmx_pcierc#_cfg003
1973 *
1974 * This register contains the fourth 32-bits of PCIe type 1 configuration space.
1975 *
1976 */
1977union cvmx_pciercx_cfg003 {
1978        u32 u32;
1979        struct cvmx_pciercx_cfg003_s {
1980                u32 bist : 8;
1981                u32 mfd : 1;
1982                u32 chf : 7;
1983                u32 lt : 8;
1984                u32 cls : 8;
1985        } s;
1986        struct cvmx_pciercx_cfg003_s cn52xx;
1987        struct cvmx_pciercx_cfg003_s cn52xxp1;
1988        struct cvmx_pciercx_cfg003_s cn56xx;
1989        struct cvmx_pciercx_cfg003_s cn56xxp1;
1990        struct cvmx_pciercx_cfg003_s cn61xx;
1991        struct cvmx_pciercx_cfg003_s cn63xx;
1992        struct cvmx_pciercx_cfg003_s cn63xxp1;
1993        struct cvmx_pciercx_cfg003_s cn66xx;
1994        struct cvmx_pciercx_cfg003_s cn68xx;
1995        struct cvmx_pciercx_cfg003_s cn68xxp1;
1996        struct cvmx_pciercx_cfg003_s cn70xx;
1997        struct cvmx_pciercx_cfg003_s cn70xxp1;
1998        struct cvmx_pciercx_cfg003_s cn73xx;
1999        struct cvmx_pciercx_cfg003_s cn78xx;
2000        struct cvmx_pciercx_cfg003_s cn78xxp1;

2001        struct cvmx_pciercx_cfg003_s cnf71xx;
2002        struct cvmx_pciercx_cfg003_s cnf75xx;
2003};
2004
2005typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t;
2006
2007/**
2008 * cvmx_pcierc#_cfg004
2009 *
2010 * This register contains the fifth 32-bits of PCIe type 1 configuration space.
2011 *
2012 */
2013union cvmx_pciercx_cfg004 {
2014        u32 u32;
2015        struct cvmx_pciercx_cfg004_s {
2016                u32 reserved_0_31 : 32;
2017        } s;
2018        struct cvmx_pciercx_cfg004_s cn52xx;
2019        struct cvmx_pciercx_cfg004_s cn52xxp1;
2020        struct cvmx_pciercx_cfg004_s cn56xx;
2021        struct cvmx_pciercx_cfg004_s cn56xxp1;
2022        struct cvmx_pciercx_cfg004_s cn61xx;
2023        struct cvmx_pciercx_cfg004_s cn63xx;
2024        struct cvmx_pciercx_cfg004_s cn63xxp1;
2025        struct cvmx_pciercx_cfg004_s cn66xx;
2026        struct cvmx_pciercx_cfg004_s cn68xx;
2027        struct cvmx_pciercx_cfg004_s cn68xxp1;
2028        struct cvmx_pciercx_cfg004_cn70xx {
2029                u32 reserved_31_0 : 32;
2030        } cn70xx;
2031        struct cvmx_pciercx_cfg004_cn70xx cn70xxp1;
2032        struct cvmx_pciercx_cfg004_cn70xx cn73xx;
2033        struct cvmx_pciercx_cfg004_cn70xx cn78xx;
2034        struct cvmx_pciercx_cfg004_cn70xx cn78xxp1;
2035        struct cvmx_pciercx_cfg004_s cnf71xx;
2036        struct cvmx_pciercx_cfg004_cn70xx cnf75xx;
2037};
2038
2039typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t;
2040
2041/**
2042 * cvmx_pcierc#_cfg005
2043 *
2044 * This register contains the sixth 32-bits of PCIe type 1 configuration space.
2045 *
2046 */
2047union cvmx_pciercx_cfg005 {
2048        u32 u32;
2049        struct cvmx_pciercx_cfg005_s {
2050                u32 reserved_0_31 : 32;
2051        } s;
2052        struct cvmx_pciercx_cfg005_s cn52xx;
2053        struct cvmx_pciercx_cfg005_s cn52xxp1;
2054        struct cvmx_pciercx_cfg005_s cn56xx;
2055        struct cvmx_pciercx_cfg005_s cn56xxp1;
2056        struct cvmx_pciercx_cfg005_s cn61xx;
2057        struct cvmx_pciercx_cfg005_s cn63xx;
2058        struct cvmx_pciercx_cfg005_s cn63xxp1;
2059        struct cvmx_pciercx_cfg005_s cn66xx;
2060        struct cvmx_pciercx_cfg005_s cn68xx;
2061        struct cvmx_pciercx_cfg005_s cn68xxp1;
2062        struct cvmx_pciercx_cfg005_cn70xx {
2063                u32 reserved_31_0 : 32;
2064        } cn70xx;
2065        struct cvmx_pciercx_cfg005_cn70xx cn70xxp1;
2066        struct cvmx_pciercx_cfg005_cn70xx cn73xx;
2067        struct cvmx_pciercx_cfg005_cn70xx cn78xx;
2068        struct cvmx_pciercx_cfg005_cn70xx cn78xxp1;
2069        struct cvmx_pciercx_cfg005_s cnf71xx;
2070        struct cvmx_pciercx_cfg005_cn70xx cnf75xx;
2071};
2072
2073typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t;
2074
2075/**
2076 * cvmx_pcierc#_cfg006
2077 *
2078 * This register contains the seventh 32-bits of PCIe type 1 configuration space.
2079 *
2080 */
2081union cvmx_pciercx_cfg006 {
2082        u32 u32;
2083        struct cvmx_pciercx_cfg006_s {
2084                u32 slt : 8;
2085                u32 subbnum : 8;
2086                u32 sbnum : 8;
2087                u32 pbnum : 8;
2088        } s;
2089        struct cvmx_pciercx_cfg006_s cn52xx;
2090        struct cvmx_pciercx_cfg006_s cn52xxp1;
2091        struct cvmx_pciercx_cfg006_s cn56xx;
2092        struct cvmx_pciercx_cfg006_s cn56xxp1;
2093        struct cvmx_pciercx_cfg006_s cn61xx;
2094        struct cvmx_pciercx_cfg006_s cn63xx;
2095        struct cvmx_pciercx_cfg006_s cn63xxp1;
2096        struct cvmx_pciercx_cfg006_s cn66xx;
2097        struct cvmx_pciercx_cfg006_s cn68xx;
2098        struct cvmx_pciercx_cfg006_s cn68xxp1;
2099        struct cvmx_pciercx_cfg006_s cn70xx;
2100        struct cvmx_pciercx_cfg006_s cn70xxp1;
2101        struct cvmx_pciercx_cfg006_s cn73xx;
2102        struct cvmx_pciercx_cfg006_s cn78xx;
2103        struct cvmx_pciercx_cfg006_s cn78xxp1;
2104        struct cvmx_pciercx_cfg006_s cnf71xx;
2105        struct cvmx_pciercx_cfg006_s cnf75xx;
2106};
2107
2108typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t;
2109
2110/**
2111 * cvmx_pcierc#_cfg007
2112 *
2113 * This register contains the eighth 32-bits of PCIe type 1 configuration space.
2114 *
2115 */
2116union cvmx_pciercx_cfg007 {
2117        u32 u32;
2118        struct cvmx_pciercx_cfg007_s {
2119                u32 dpe : 1;
2120                u32 sse : 1;
2121                u32 rma : 1;
2122                u32 rta : 1;
2123                u32 sta : 1;
2124                u32 devt : 2;
2125                u32 mdpe : 1;
2126                u32 fbb : 1;
2127                u32 reserved_22_22 : 1;
2128                u32 m66 : 1;
2129                u32 reserved_16_20 : 5;
2130                u32 lio_limi : 4;
2131                u32 reserved_9_11 : 3;
2132                u32 io32b : 1;
2133                u32 lio_base : 4;
2134                u32 reserved_1_3 : 3;
2135                u32 io32a : 1;
2136        } s;
2137        struct cvmx_pciercx_cfg007_s cn52xx;
2138        struct cvmx_pciercx_cfg007_s cn52xxp1;
2139        struct cvmx_pciercx_cfg007_s cn56xx;
2140        struct cvmx_pciercx_cfg007_s cn56xxp1;
2141        struct cvmx_pciercx_cfg007_s cn61xx;
2142        struct cvmx_pciercx_cfg007_s cn63xx;
2143        struct cvmx_pciercx_cfg007_s cn63xxp1;
2144        struct cvmx_pciercx_cfg007_s cn66xx;
2145        struct cvmx_pciercx_cfg007_s cn68xx;
2146        struct cvmx_pciercx_cfg007_s cn68xxp1;
2147        struct cvmx_pciercx_cfg007_s cn70xx;
2148        struct cvmx_pciercx_cfg007_s cn70xxp1;
2149        struct cvmx_pciercx_cfg007_s cn73xx;
2150        struct cvmx_pciercx_cfg007_s cn78xx;
2151        struct cvmx_pciercx_cfg007_s cn78xxp1;
2152        struct cvmx_pciercx_cfg007_s cnf71xx;
2153        struct cvmx_pciercx_cfg007_s cnf75xx;
2154};
2155
2156typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t;
2157
2158/**
2159 * cvmx_pcierc#_cfg008
2160 *
2161 * This register contains the ninth 32-bits of PCIe type 1 configuration space.
2162 *
2163 */
2164union cvmx_pciercx_cfg008 {
2165        u32 u32;
2166        struct cvmx_pciercx_cfg008_s {
2167                u32 ml_addr : 12;
2168                u32 reserved_16_19 : 4;
2169                u32 mb_addr : 12;
2170                u32 reserved_0_3 : 4;
2171        } s;
2172        struct cvmx_pciercx_cfg008_s cn52xx;
2173        struct cvmx_pciercx_cfg008_s cn52xxp1;
2174        struct cvmx_pciercx_cfg008_s cn56xx;
2175        struct cvmx_pciercx_cfg008_s cn56xxp1;
2176        struct cvmx_pciercx_cfg008_s cn61xx;
2177        struct cvmx_pciercx_cfg008_s cn63xx;
2178        struct cvmx_pciercx_cfg008_s cn63xxp1;
2179        struct cvmx_pciercx_cfg008_s cn66xx;
2180        struct cvmx_pciercx_cfg008_s cn68xx;
2181        struct cvmx_pciercx_cfg008_s cn68xxp1;
2182        struct cvmx_pciercx_cfg008_cn70xx {
2183                u32 ml_addr : 12;
2184                u32 reserved_19_16 : 4;
2185                u32 mb_addr : 12;
2186                u32 reserved_3_0 : 4;
2187        } cn70xx;
2188        struct cvmx_pciercx_cfg008_cn70xx cn70xxp1;
2189        struct cvmx_pciercx_cfg008_cn70xx cn73xx;
2190        struct cvmx_pciercx_cfg008_cn70xx cn78xx;
2191        struct cvmx_pciercx_cfg008_cn70xx cn78xxp1;
2192        struct cvmx_pciercx_cfg008_s cnf71xx;
2193        struct cvmx_pciercx_cfg008_cn70xx cnf75xx;
2194};
2195
2196typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t;
2197
2198/**
2199 * cvmx_pcierc#_cfg009
2200 *
2201 * This register contains the tenth 32-bits of PCIe type 1 configuration space.
2202 *
2203 */
2204union cvmx_pciercx_cfg009 {
2205        u32 u32;
2206        struct cvmx_pciercx_cfg009_s {
2207                u32 lmem_limit : 12;
2208                u32 reserved_17_19 : 3;
2209                u32 mem64b : 1;
2210                u32 lmem_base : 12;
2211                u32 reserved_1_3 : 3;
2212                u32 mem64a : 1;
2213        } s;
2214        struct cvmx_pciercx_cfg009_s cn52xx;
2215        struct cvmx_pciercx_cfg009_s cn52xxp1;
2216        struct cvmx_pciercx_cfg009_s cn56xx;
2217        struct cvmx_pciercx_cfg009_s cn56xxp1;
2218        struct cvmx_pciercx_cfg009_s cn61xx;
2219        struct cvmx_pciercx_cfg009_s cn63xx;
2220        struct cvmx_pciercx_cfg009_s cn63xxp1;
2221        struct cvmx_pciercx_cfg009_s cn66xx;
2222        struct cvmx_pciercx_cfg009_s cn68xx;
2223        struct cvmx_pciercx_cfg009_s cn68xxp1;
2224        struct cvmx_pciercx_cfg009_cn70xx {
2225                u32 lmem_limit : 12;
2226                u32 reserved_19_17 : 3;
2227                u32 mem64b : 1;
2228                u32 lmem_base : 12;
2229                u32 reserved_3_1 : 3;
2230                u32 mem64a : 1;
2231        } cn70xx;
2232        struct cvmx_pciercx_cfg009_cn70xx cn70xxp1;
2233        struct cvmx_pciercx_cfg009_cn70xx cn73xx;
2234        struct cvmx_pciercx_cfg009_cn70xx cn78xx;
2235        struct cvmx_pciercx_cfg009_cn70xx cn78xxp1;
2236        struct cvmx_pciercx_cfg009_s cnf71xx;
2237        struct cvmx_pciercx_cfg009_cn70xx cnf75xx;
2238};
2239
2240typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t;
2241
2242/**
2243 * cvmx_pcierc#_cfg010
2244 *
2245 * This register contains the eleventh 32-bits of PCIe type 1 configuration space.
2246 *
2247 */
2248union cvmx_pciercx_cfg010 {
2249        u32 u32;
2250        struct cvmx_pciercx_cfg010_s {
2251                u32 umem_base : 32;
2252        } s;
2253        struct cvmx_pciercx_cfg010_s cn52xx;
2254        struct cvmx_pciercx_cfg010_s cn52xxp1;
2255        struct cvmx_pciercx_cfg010_s cn56xx;
2256        struct cvmx_pciercx_cfg010_s cn56xxp1;
2257        struct cvmx_pciercx_cfg010_s cn61xx;
2258        struct cvmx_pciercx_cfg010_s cn63xx;
2259        struct cvmx_pciercx_cfg010_s cn63xxp1;
2260        struct cvmx_pciercx_cfg010_s cn66xx;
2261        struct cvmx_pciercx_cfg010_s cn68xx;
2262        struct cvmx_pciercx_cfg010_s cn68xxp1;
2263        struct cvmx_pciercx_cfg010_s cn70xx;
2264        struct cvmx_pciercx_cfg010_s cn70xxp1;
2265        struct cvmx_pciercx_cfg010_s cn73xx;
2266        struct cvmx_pciercx_cfg010_s cn78xx;
2267        struct cvmx_pciercx_cfg010_s cn78xxp1;
2268        struct cvmx_pciercx_cfg010_s cnf71xx;
2269        struct cvmx_pciercx_cfg010_s cnf75xx;
2270};
2271
2272typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t;
2273
2274/**
2275 * cvmx_pcierc#_cfg011
2276 *
2277 * This register contains the twelfth 32-bits of PCIe type 1 configuration space.
2278 *
2279 */
2280union cvmx_pciercx_cfg011 {
2281        u32 u32;
2282        struct cvmx_pciercx_cfg011_s {
2283                u32 umem_limit : 32;
2284        } s;
2285        struct cvmx_pciercx_cfg011_s cn52xx;
2286        struct cvmx_pciercx_cfg011_s cn52xxp1;
2287        struct cvmx_pciercx_cfg011_s cn56xx;
2288        struct cvmx_pciercx_cfg011_s cn56xxp1;
2289        struct cvmx_pciercx_cfg011_s cn61xx;
2290        struct cvmx_pciercx_cfg011_s cn63xx;
2291        struct cvmx_pciercx_cfg011_s cn63xxp1;
2292        struct cvmx_pciercx_cfg011_s cn66xx;
2293        struct cvmx_pciercx_cfg011_s cn68xx;
2294        struct cvmx_pciercx_cfg011_s cn68xxp1;
2295        struct cvmx_pciercx_cfg011_s cn70xx;
2296        struct cvmx_pciercx_cfg011_s cn70xxp1;
2297        struct cvmx_pciercx_cfg011_s cn73xx;
2298        struct cvmx_pciercx_cfg011_s cn78xx;
2299        struct cvmx_pciercx_cfg011_s cn78xxp1;
2300        struct cvmx_pciercx_cfg011_s cnf71xx;
2301        struct cvmx_pciercx_cfg011_s cnf75xx;
2302};
2303
2304typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t;
2305
2306/**
2307 * cvmx_pcierc#_cfg012
2308 *
2309 * This register contains the thirteenth 32-bits of PCIe type 1 configuration space.
2310 *
2311 */
2312union cvmx_pciercx_cfg012 {
2313        u32 u32;
2314        struct cvmx_pciercx_cfg012_s {
2315                u32 uio_limit : 16;
2316                u32 uio_base : 16;
2317        } s;
2318        struct cvmx_pciercx_cfg012_s cn52xx;
2319        struct cvmx_pciercx_cfg012_s cn52xxp1;
2320        struct cvmx_pciercx_cfg012_s cn56xx;
2321        struct cvmx_pciercx_cfg012_s cn56xxp1;
2322        struct cvmx_pciercx_cfg012_s cn61xx;
2323        struct cvmx_pciercx_cfg012_s cn63xx;
2324        struct cvmx_pciercx_cfg012_s cn63xxp1;
2325        struct cvmx_pciercx_cfg012_s cn66xx;
2326        struct cvmx_pciercx_cfg012_s cn68xx;
2327        struct cvmx_pciercx_cfg012_s cn68xxp1;
2328        struct cvmx_pciercx_cfg012_s cn70xx;
2329        struct cvmx_pciercx_cfg012_s cn70xxp1;
2330        struct cvmx_pciercx_cfg012_s cn73xx;
2331        struct cvmx_pciercx_cfg012_s cn78xx;
2332        struct cvmx_pciercx_cfg012_s cn78xxp1;
2333        struct cvmx_pciercx_cfg012_s cnf71xx;
2334        struct cvmx_pciercx_cfg012_s cnf75xx;
2335};
2336
2337typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t;
2338
2339/**
2340 * cvmx_pcierc#_cfg013
2341 *
2342 * This register contains the fourteenth 32-bits of PCIe type 1 configuration space.
2343 *
2344 */
2345union cvmx_pciercx_cfg013 {
2346        u32 u32;
2347        struct cvmx_pciercx_cfg013_s {
2348                u32 reserved_8_31 : 24;
2349                u32 cp : 8;
2350        } s;
2351        struct cvmx_pciercx_cfg013_s cn52xx;
2352        struct cvmx_pciercx_cfg013_s cn52xxp1;
2353        struct cvmx_pciercx_cfg013_s cn56xx;
2354        struct cvmx_pciercx_cfg013_s cn56xxp1;
2355        struct cvmx_pciercx_cfg013_s cn61xx;
2356        struct cvmx_pciercx_cfg013_s cn63xx;
2357        struct cvmx_pciercx_cfg013_s cn63xxp1;
2358        struct cvmx_pciercx_cfg013_s cn66xx;
2359        struct cvmx_pciercx_cfg013_s cn68xx;
2360        struct cvmx_pciercx_cfg013_s cn68xxp1;
2361        struct cvmx_pciercx_cfg013_s cn70xx;
2362        struct cvmx_pciercx_cfg013_s cn70xxp1;
2363        struct cvmx_pciercx_cfg013_s cn73xx;
2364        struct cvmx_pciercx_cfg013_s cn78xx;
2365        struct cvmx_pciercx_cfg013_s cn78xxp1;
2366        struct cvmx_pciercx_cfg013_s cnf71xx;
2367        struct cvmx_pciercx_cfg013_s cnf75xx;
2368};
2369
2370typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t;
2371
2372/**
2373 * cvmx_pcierc#_cfg014
2374 *
2375 * This register contains the fifteenth 32-bits of PCIe type 1 configuration space.
2376 *
2377 */
2378union cvmx_pciercx_cfg014 {
2379        u32 u32;
2380        struct cvmx_pciercx_cfg014_s {
2381                u32 reserved_0_31 : 32;
2382        } s;
2383        struct cvmx_pciercx_cfg014_s cn52xx;
2384        struct cvmx_pciercx_cfg014_s cn52xxp1;
2385        struct cvmx_pciercx_cfg014_s cn56xx;
2386        struct cvmx_pciercx_cfg014_s cn56xxp1;
2387        struct cvmx_pciercx_cfg014_s cn61xx;
2388        struct cvmx_pciercx_cfg014_s cn63xx;
2389        struct cvmx_pciercx_cfg014_s cn63xxp1;
2390        struct cvmx_pciercx_cfg014_s cn66xx;
2391        struct cvmx_pciercx_cfg014_s cn68xx;
2392        struct cvmx_pciercx_cfg014_s cn68xxp1;
2393        struct cvmx_pciercx_cfg014_s cn70xx;
2394        struct cvmx_pciercx_cfg014_s cn70xxp1;
2395        struct cvmx_pciercx_cfg014_s cn73xx;
2396        struct cvmx_pciercx_cfg014_s cn78xx;
2397        struct cvmx_pciercx_cfg014_s cn78xxp1;
2398        struct cvmx_pciercx_cfg014_s cnf71xx;
2399        struct cvmx_pciercx_cfg014_s cnf75xx;
2400};
2401
2402typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t;
2403
2404/**
2405 * cvmx_pcierc#_cfg015
2406 *
2407 * This register contains the sixteenth 32-bits of PCIe type 1 configuration space.
2408 *
2409 */
2410union cvmx_pciercx_cfg015 {
2411        u32 u32;
2412        struct cvmx_pciercx_cfg015_s {
2413                u32 reserved_28_31 : 4;
2414                u32 dtsees : 1;
2415                u32 dts : 1;
2416                u32 sdt : 1;
2417                u32 pdt : 1;
2418                u32 fbbe : 1;
2419                u32 sbrst : 1;
2420                u32 mam : 1;
2421                u32 vga16d : 1;
2422                u32 vgae : 1;
2423                u32 isae : 1;
2424                u32 see : 1;
2425                u32 pere : 1;
2426                u32 inta : 8;
2427                u32 il : 8;
2428        } s;
2429        struct cvmx_pciercx_cfg015_s cn52xx;
2430        struct cvmx_pciercx_cfg015_s cn52xxp1;
2431        struct cvmx_pciercx_cfg015_s cn56xx;
2432        struct cvmx_pciercx_cfg015_s cn56xxp1;
2433        struct cvmx_pciercx_cfg015_s cn61xx;
2434        struct cvmx_pciercx_cfg015_s cn63xx;
2435        struct cvmx_pciercx_cfg015_s cn63xxp1;
2436        struct cvmx_pciercx_cfg015_s cn66xx;
2437        struct cvmx_pciercx_cfg015_s cn68xx;
2438        struct cvmx_pciercx_cfg015_s cn68xxp1;
2439        struct cvmx_pciercx_cfg015_cn70xx {
2440                u32 reserved_31_28 : 4;
2441                u32 dtsees : 1;
2442                u32 dts : 1;
2443                u32 sdt : 1;
2444                u32 pdt : 1;
2445                u32 fbbe : 1;
2446                u32 sbrst : 1;
2447                u32 mam : 1;
2448                u32 vga16d : 1;
2449                u32 vgae : 1;
2450                u32 isae : 1;
2451                u32 see : 1;
2452                u32 pere : 1;
2453                u32 inta : 8;
2454                u32 il : 8;
2455        } cn70xx;
2456        struct cvmx_pciercx_cfg015_cn70xx cn70xxp1;
2457        struct cvmx_pciercx_cfg015_cn70xx cn73xx;
2458        struct cvmx_pciercx_cfg015_cn70xx cn78xx;
2459        struct cvmx_pciercx_cfg015_cn70xx cn78xxp1;
2460        struct cvmx_pciercx_cfg015_s cnf71xx;
2461        struct cvmx_pciercx_cfg015_cn70xx cnf75xx;
2462};
2463
2464typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t;
2465
2466/**
2467 * cvmx_pcierc#_cfg016
2468 *
2469 * This register contains the seventeenth 32-bits of PCIe type 1 configuration space.
2470 *
2471 */
2472union cvmx_pciercx_cfg016 {
2473        u32 u32;
2474        struct cvmx_pciercx_cfg016_s {
2475                u32 pmes : 5;
2476                u32 d2s : 1;
2477                u32 d1s : 1;
2478                u32 auxc : 3;
2479                u32 dsi : 1;
2480                u32 reserved_20_20 : 1;
2481                u32 pme_clock : 1;
2482                u32 pmsv : 3;
2483                u32 ncp : 8;
2484                u32 pmcid : 8;
2485        } s;
2486        struct cvmx_pciercx_cfg016_s cn52xx;
2487        struct cvmx_pciercx_cfg016_s cn52xxp1;
2488        struct cvmx_pciercx_cfg016_s cn56xx;
2489        struct cvmx_pciercx_cfg016_s cn56xxp1;
2490        struct cvmx_pciercx_cfg016_s cn61xx;
2491        struct cvmx_pciercx_cfg016_s cn63xx;
2492        struct cvmx_pciercx_cfg016_s cn63xxp1;
2493        struct cvmx_pciercx_cfg016_s cn66xx;
2494        struct cvmx_pciercx_cfg016_s cn68xx;
2495        struct cvmx_pciercx_cfg016_s cn68xxp1;
2496        struct cvmx_pciercx_cfg016_s cn70xx;
2497        struct cvmx_pciercx_cfg016_s cn70xxp1;
2498        struct cvmx_pciercx_cfg016_s cn73xx;
2499        struct cvmx_pciercx_cfg016_s cn78xx;
2500        struct cvmx_pciercx_cfg016_s cn78xxp1;
2501        struct cvmx_pciercx_cfg016_s cnf71xx;
2502        struct cvmx_pciercx_cfg016_s cnf75xx;
2503};
2504
2505typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t;
2506
2507/**
2508 * cvmx_pcierc#_cfg017
2509 *
2510 * This register contains the eighteenth 32-bits of PCIe type 1 configuration space.
2511 *
2512 */
2513union cvmx_pciercx_cfg017 {
2514        u32 u32;
2515        struct cvmx_pciercx_cfg017_s {
2516                u32 pmdia : 8;
2517                u32 bpccee : 1;
2518                u32 bd3h : 1;
2519                u32 reserved_16_21 : 6;
2520                u32 pmess : 1;
2521                u32 pmedsia : 2;
2522                u32 pmds : 4;
2523                u32 pmeens : 1;
2524                u32 reserved_4_7 : 4;
2525                u32 nsr : 1;
2526                u32 reserved_2_2 : 1;
2527                u32 ps : 2;
2528        } s;
2529        struct cvmx_pciercx_cfg017_s cn52xx;
2530        struct cvmx_pciercx_cfg017_s cn52xxp1;
2531        struct cvmx_pciercx_cfg017_s cn56xx;
2532        struct cvmx_pciercx_cfg017_s cn56xxp1;
2533        struct cvmx_pciercx_cfg017_s cn61xx;
2534        struct cvmx_pciercx_cfg017_s cn63xx;
2535        struct cvmx_pciercx_cfg017_s cn63xxp1;
2536        struct cvmx_pciercx_cfg017_s cn66xx;
2537        struct cvmx_pciercx_cfg017_s cn68xx;
2538        struct cvmx_pciercx_cfg017_s cn68xxp1;
2539        struct cvmx_pciercx_cfg017_s cn70xx;
2540        struct cvmx_pciercx_cfg017_s cn70xxp1;
2541        struct cvmx_pciercx_cfg017_s cn73xx;
2542        struct cvmx_pciercx_cfg017_s cn78xx;
2543        struct cvmx_pciercx_cfg017_s cn78xxp1;
2544        struct cvmx_pciercx_cfg017_s cnf71xx;
2545        struct cvmx_pciercx_cfg017_s cnf75xx;
2546};
2547
2548typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t;
2549
2550/**
2551 * cvmx_pcierc#_cfg020
2552 *
2553 * This register contains the twenty-first 32-bits of PCIe type 1 configuration space.
2554 *
2555 */
2556union cvmx_pciercx_cfg020 {
2557        u32 u32;
2558        struct cvmx_pciercx_cfg020_s {
2559                u32 reserved_24_31 : 8;
2560                u32 m64 : 1;
2561                u32 mme : 3;
2562                u32 mmc : 3;
2563                u32 msien : 1;
2564                u32 ncp : 8;
2565                u32 msicid : 8;
2566        } s;
2567        struct cvmx_pciercx_cfg020_s cn52xx;
2568        struct cvmx_pciercx_cfg020_s cn52xxp1;
2569        struct cvmx_pciercx_cfg020_s cn56xx;
2570        struct cvmx_pciercx_cfg020_s cn56xxp1;
2571        struct cvmx_pciercx_cfg020_cn61xx {
2572                u32 reserved_25_31 : 7;
2573                u32 pvm : 1;
2574                u32 m64 : 1;
2575                u32 mme : 3;
2576                u32 mmc : 3;
2577                u32 msien : 1;
2578                u32 ncp : 8;
2579                u32 msicid : 8;
2580        } cn61xx;
2581        struct cvmx_pciercx_cfg020_s cn63xx;
2582        struct cvmx_pciercx_cfg020_s cn63xxp1;
2583        struct cvmx_pciercx_cfg020_s cn66xx;
2584        struct cvmx_pciercx_cfg020_s cn68xx;
2585        struct cvmx_pciercx_cfg020_s cn68xxp1;
2586        struct cvmx_pciercx_cfg020_cn61xx cn70xx;
2587        struct cvmx_pciercx_cfg020_cn61xx cn70xxp1;
2588        struct cvmx_pciercx_cfg020_cn73xx {
2589                u32 reserved_25_31 : 7;
2590                u32 pvms : 1;
2591                u32 m64 : 1;
2592                u32 mme : 3;
2593                u32 mmc : 3;
2594                u32 msien : 1;
2595                u32 ncp : 8;
2596                u32 msicid : 8;
2597        } cn73xx;
2598        struct cvmx_pciercx_cfg020_cn73xx cn78xx;
2599        struct cvmx_pciercx_cfg020_cn73xx cn78xxp1;
2600        struct cvmx_pciercx_cfg020_cn61xx cnf71xx;
2601        struct cvmx_pciercx_cfg020_cn73xx cnf75xx;
2602};
2603
2604typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t;
2605
2606/**
2607 * cvmx_pcierc#_cfg021
2608 *
2609 * This register contains the twenty-second 32-bits of PCIe type 1 configuration space.
2610 *
2611 */
2612union cvmx_pciercx_cfg021 {
2613        u32 u32;
2614        struct cvmx_pciercx_cfg021_s {
2615                u32 lmsi : 30;
2616                u32 reserved_0_1 : 2;
2617        } s;
2618        struct cvmx_pciercx_cfg021_s cn52xx;
2619        struct cvmx_pciercx_cfg021_s cn52xxp1;
2620        struct cvmx_pciercx_cfg021_s cn56xx;
2621        struct cvmx_pciercx_cfg021_s cn56xxp1;
2622        struct cvmx_pciercx_cfg021_s cn61xx;
2623        struct cvmx_pciercx_cfg021_s cn63xx;
2624        struct cvmx_pciercx_cfg021_s cn63xxp1;
2625        struct cvmx_pciercx_cfg021_s cn66xx;
2626        struct cvmx_pciercx_cfg021_s cn68xx;
2627        struct cvmx_pciercx_cfg021_s cn68xxp1;
2628        struct cvmx_pciercx_cfg021_s cn70xx;
2629        struct cvmx_pciercx_cfg021_s cn70xxp1;
2630        struct cvmx_pciercx_cfg021_s cn73xx;
2631        struct cvmx_pciercx_cfg021_s cn78xx;
2632        struct cvmx_pciercx_cfg021_s cn78xxp1;
2633        struct cvmx_pciercx_cfg021_s cnf71xx;
2634        struct cvmx_pciercx_cfg021_s cnf75xx;
2635};
2636
2637typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t;
2638
2639/**
2640 * cvmx_pcierc#_cfg022
2641 *
2642 * This register contains the twenty-third 32-bits of PCIe type 1 configuration space.
2643 *
2644 */
2645union cvmx_pciercx_cfg022 {
2646        u32 u32;
2647        struct cvmx_pciercx_cfg022_s {
2648                u32 umsi : 32;
2649        } s;
2650        struct cvmx_pciercx_cfg022_s cn52xx;
2651        struct cvmx_pciercx_cfg022_s cn52xxp1;
2652        struct cvmx_pciercx_cfg022_s cn56xx;
2653        struct cvmx_pciercx_cfg022_s cn56xxp1;
2654        struct cvmx_pciercx_cfg022_s cn61xx;
2655        struct cvmx_pciercx_cfg022_s cn63xx;
2656        struct cvmx_pciercx_cfg022_s cn63xxp1;
2657        struct cvmx_pciercx_cfg022_s cn66xx;
2658        struct cvmx_pciercx_cfg022_s cn68xx;
2659        struct cvmx_pciercx_cfg022_s cn68xxp1;
2660        struct cvmx_pciercx_cfg022_s cn70xx;
2661        struct cvmx_pciercx_cfg022_s cn70xxp1;
2662        struct cvmx_pciercx_cfg022_s cn73xx;
2663        struct cvmx_pciercx_cfg022_s cn78xx;
2664        struct cvmx_pciercx_cfg022_s cn78xxp1;
2665        struct cvmx_pciercx_cfg022_s cnf71xx;
2666        struct cvmx_pciercx_cfg022_s cnf75xx;
2667};
2668
2669typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t;
2670
2671/**
2672 * cvmx_pcierc#_cfg023
2673 *
2674 * This register contains the twenty-fourth 32-bits of PCIe type 1 configuration space.
2675 *
2676 */
2677union cvmx_pciercx_cfg023 {
2678        u32 u32;
2679        struct cvmx_pciercx_cfg023_s {
2680                u32 reserved_16_31 : 16;
2681                u32 msimd : 16;
2682        } s;
2683        struct cvmx_pciercx_cfg023_s cn52xx;
2684        struct cvmx_pciercx_cfg023_s cn52xxp1;
2685        struct cvmx_pciercx_cfg023_s cn56xx;
2686        struct cvmx_pciercx_cfg023_s cn56xxp1;
2687        struct cvmx_pciercx_cfg023_s cn61xx;
2688        struct cvmx_pciercx_cfg023_s cn63xx;
2689        struct cvmx_pciercx_cfg023_s cn63xxp1;
2690        struct cvmx_pciercx_cfg023_s cn66xx;
2691        struct cvmx_pciercx_cfg023_s cn68xx;
2692        struct cvmx_pciercx_cfg023_s cn68xxp1;
2693        struct cvmx_pciercx_cfg023_s cn70xx;
2694        struct cvmx_pciercx_cfg023_s cn70xxp1;
2695        struct cvmx_pciercx_cfg023_s cn73xx;
2696        struct cvmx_pciercx_cfg023_s cn78xx;
2697        struct cvmx_pciercx_cfg023_s cn78xxp1;
2698        struct cvmx_pciercx_cfg023_s cnf71xx;
2699        struct cvmx_pciercx_cfg023_s cnf75xx;
2700};
2701
2702typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t;
2703
2704/**
2705 * cvmx_pcierc#_cfg028
2706 *
2707 * This register contains the twenty-ninth 32-bits of PCIe type 1 configuration space.
2708 *
2709 */
2710union cvmx_pciercx_cfg028 {
2711        u32 u32;
2712        struct cvmx_pciercx_cfg028_s {
2713                u32 reserved_30_31 : 2;
2714                u32 imn : 5;
2715                u32 si : 1;
2716                u32 dpt : 4;
2717                u32 pciecv : 4;
2718                u32 ncp : 8;
2719                u32 pcieid : 8;
2720        } s;
2721        struct cvmx_pciercx_cfg028_s cn52xx;
2722        struct cvmx_pciercx_cfg028_s cn52xxp1;
2723        struct cvmx_pciercx_cfg028_s cn56xx;
2724        struct cvmx_pciercx_cfg028_s cn56xxp1;
2725        struct cvmx_pciercx_cfg028_s cn61xx;
2726        struct cvmx_pciercx_cfg028_s cn63xx;
2727        struct cvmx_pciercx_cfg028_s cn63xxp1;
2728        struct cvmx_pciercx_cfg028_s cn66xx;
2729        struct cvmx_pciercx_cfg028_s cn68xx;
2730        struct cvmx_pciercx_cfg028_s cn68xxp1;
2731        struct cvmx_pciercx_cfg028_s cn70xx;
2732        struct cvmx_pciercx_cfg028_s cn70xxp1;
2733        struct cvmx_pciercx_cfg028_s cn73xx;
2734        struct cvmx_pciercx_cfg028_s cn78xx;
2735        struct cvmx_pciercx_cfg028_s cn78xxp1;
2736        struct cvmx_pciercx_cfg028_s cnf71xx;
2737        struct cvmx_pciercx_cfg028_s cnf75xx;
2738};
2739
2740typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t;
2741
2742/**
2743 * cvmx_pcierc#_cfg029
2744 *
2745 * This register contains the thirtieth 32-bits of PCIe type 1 configuration space.
2746 *
2747 */
2748union cvmx_pciercx_cfg029 {
2749        u32 u32;
2750        struct cvmx_pciercx_cfg029_s {
2751                u32 reserved_29_31 : 3;
2752                u32 flr_cap : 1;
2753                u32 cspls : 2;
2754                u32 csplv : 8;
2755                u32 reserved_16_17 : 2;
2756                u32 rber : 1;
2757                u32 reserved_12_14 : 3;
2758                u32 el1al : 3;
2759                u32 el0al : 3;
2760                u32 etfs : 1;
2761                u32 pfs : 2;
2762                u32 mpss : 3;
2763        } s;
2764        struct cvmx_pciercx_cfg029_cn52xx {
2765                u32 reserved_28_31 : 4;
2766                u32 cspls : 2;
2767                u32 csplv : 8;
2768                u32 reserved_16_17 : 2;
2769                u32 rber : 1;
2770                u32 reserved_12_14 : 3;
2771                u32 el1al : 3;
2772                u32 el0al : 3;
2773                u32 etfs : 1;
2774                u32 pfs : 2;
2775                u32 mpss : 3;
2776        } cn52xx;
2777        struct cvmx_pciercx_cfg029_cn52xx cn52xxp1;
2778        struct cvmx_pciercx_cfg029_cn52xx cn56xx;
2779        struct cvmx_pciercx_cfg029_cn52xx cn56xxp1;
2780        struct cvmx_pciercx_cfg029_cn52xx cn61xx;
2781        struct cvmx_pciercx_cfg029_cn52xx cn63xx;
2782        struct cvmx_pciercx_cfg029_cn52xx cn63xxp1;
2783        struct cvmx_pciercx_cfg029_cn52xx cn66xx;
2784        struct cvmx_pciercx_cfg029_cn52xx cn68xx;
2785        struct cvmx_pciercx_cfg029_cn52xx cn68xxp1;
2786        struct cvmx_pciercx_cfg029_cn52xx cn70xx;
2787        struct cvmx_pciercx_cfg029_cn52xx cn70xxp1;
2788        struct cvmx_pciercx_cfg029_s cn73xx;
2789        struct cvmx_pciercx_cfg029_s cn78xx;
2790        struct cvmx_pciercx_cfg029_s cn78xxp1;
2791        struct cvmx_pciercx_cfg029_cn52xx cnf71xx;
2792        struct cvmx_pciercx_cfg029_s cnf75xx;
2793};
2794
2795typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t;
2796
2797/**
2798 * cvmx_pcierc#_cfg030
2799 *
2800 * This register contains the thirty-first 32-bits of PCIe type 1 configuration space.
2801 *
2802 */
2803union cvmx_pciercx_cfg030 {
2804        u32 u32;
2805        struct cvmx_pciercx_cfg030_s {
2806                u32 reserved_22_31 : 10;
2807                u32 tp : 1;
2808                u32 ap_d : 1;
2809                u32 ur_d : 1;
2810                u32 fe_d : 1;
2811                u32 nfe_d : 1;
2812                u32 ce_d : 1;
2813                u32 reserved_15_15 : 1;
2814                u32 mrrs : 3;
2815                u32 ns_en : 1;
2816                u32 ap_en : 1;
2817                u32 pf_en : 1;
2818                u32 etf_en : 1;
2819                u32 mps : 3;
2820                u32 ro_en : 1;
2821                u32 ur_en : 1;
2822                u32 fe_en : 1;
2823                u32 nfe_en : 1;
2824                u32 ce_en : 1;
2825        } s;
2826        struct cvmx_pciercx_cfg030_s cn52xx;
2827        struct cvmx_pciercx_cfg030_s cn52xxp1;
2828        struct cvmx_pciercx_cfg030_s cn56xx;
2829        struct cvmx_pciercx_cfg030_s cn56xxp1;
2830        struct cvmx_pciercx_cfg030_s cn61xx;
2831        struct cvmx_pciercx_cfg030_s cn63xx;
2832        struct cvmx_pciercx_cfg030_s cn63xxp1;
2833        struct cvmx_pciercx_cfg030_s cn66xx;
2834        struct cvmx_pciercx_cfg030_s cn68xx;
2835        struct cvmx_pciercx_cfg030_s cn68xxp1;
2836        struct cvmx_pciercx_cfg030_s cn70xx;
2837        struct cvmx_pciercx_cfg030_s cn70xxp1;
2838        struct cvmx_pciercx_cfg030_s cn73xx;
2839        struct cvmx_pciercx_cfg030_s cn78xx;
2840        struct cvmx_pciercx_cfg030_s cn78xxp1;
2841        struct cvmx_pciercx_cfg030_s cnf71xx;
2842        struct cvmx_pciercx_cfg030_s cnf75xx;
2843};
2844
2845typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t;
2846
2847/**
2848 * cvmx_pcierc#_cfg031
2849 *
2850 * This register contains the thirty-second 32-bits of PCIe type 1 configuration space.
2851 *
2852 */
2853union cvmx_pciercx_cfg031 {
2854        u32 u32;
2855        struct cvmx_pciercx_cfg031_s {
2856                u32 pnum : 8;
2857                u32 reserved_23_23 : 1;
2858                u32 aspm : 1;
2859                u32 lbnc : 1;
2860                u32 dllarc : 1;
2861                u32 sderc : 1;
2862                u32 cpm : 1;
2863                u32 l1el : 3;
2864                u32 l0el : 3;
2865                u32 aslpms : 2;
2866                u32 mlw : 6;
2867                u32 mls : 4;
2868        } s;
2869        struct cvmx_pciercx_cfg031_cn52xx {
2870                u32 pnum : 8;
2871                u32 reserved_22_23 : 2;
2872                u32 lbnc : 1;
2873                u32 dllarc : 1;
2874                u32 sderc : 1;
2875                u32 cpm : 1;
2876                u32 l1el : 3;
2877                u32 l0el : 3;
2878                u32 aslpms : 2;
2879                u32 mlw : 6;
2880                u32 mls : 4;
2881        } cn52xx;
2882        struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
2883        struct cvmx_pciercx_cfg031_cn52xx cn56xx;
2884        struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
2885        struct cvmx_pciercx_cfg031_s cn61xx;
2886        struct cvmx_pciercx_cfg031_cn52xx cn63xx;
2887        struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
2888        struct cvmx_pciercx_cfg031_s cn66xx;
2889        struct cvmx_pciercx_cfg031_s cn68xx;
2890        struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
2891        struct cvmx_pciercx_cfg031_s cn70xx;
2892        struct cvmx_pciercx_cfg031_s cn70xxp1;
2893        struct cvmx_pciercx_cfg031_s cn73xx;
2894        struct cvmx_pciercx_cfg031_s cn78xx;
2895        struct cvmx_pciercx_cfg031_s cn78xxp1;
2896        struct cvmx_pciercx_cfg031_s cnf71xx;
2897        struct cvmx_pciercx_cfg031_s cnf75xx;
2898};
2899
2900typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t;
2901
2902/**
2903 * cvmx_pcierc#_cfg032
2904 *
2905 * This register contains the thirty-third 32-bits of PCIe type 1 configuration space.
2906 *
2907 */
2908union cvmx_pciercx_cfg032 {
2909        u32 u32;
2910        struct cvmx_pciercx_cfg032_s {
2911                u32 lab : 1;
2912                u32 lbm : 1;
2913                u32 dlla : 1;
2914                u32 scc : 1;
2915                u32 lt : 1;
2916                u32 reserved_26_26 : 1;
2917                u32 nlw : 6;
2918                u32 ls : 4;
2919                u32 reserved_12_15 : 4;
2920                u32 lab_int_enb : 1;
2921                u32 lbm_int_enb : 1;
2922                u32 hawd : 1;
2923                u32 ecpm : 1;
2924                u32 es : 1;
2925                u32 ccc : 1;
2926                u32 rl : 1;
2927                u32 ld : 1;
2928                u32 rcb : 1;
2929                u32 reserved_2_2 : 1;
2930                u32 aslpc : 2;
2931        } s;
2932        struct cvmx_pciercx_cfg032_s cn52xx;
2933        struct cvmx_pciercx_cfg032_s cn52xxp1;
2934        struct cvmx_pciercx_cfg032_s cn56xx;
2935        struct cvmx_pciercx_cfg032_s cn56xxp1;
2936        struct cvmx_pciercx_cfg032_s cn61xx;
2937        struct cvmx_pciercx_cfg032_s cn63xx;
2938        struct cvmx_pciercx_cfg032_s cn63xxp1;
2939        struct cvmx_pciercx_cfg032_s cn66xx;
2940        struct cvmx_pciercx_cfg032_s cn68xx;
2941        struct cvmx_pciercx_cfg032_s cn68xxp1;
2942        struct cvmx_pciercx_cfg032_s cn70xx;
2943        struct cvmx_pciercx_cfg032_s cn70xxp1;
2944        struct cvmx_pciercx_cfg032_s cn73xx;
2945        struct cvmx_pciercx_cfg032_s cn78xx;
2946        struct cvmx_pciercx_cfg032_s cn78xxp1;
2947        struct cvmx_pciercx_cfg032_s cnf71xx;
2948        struct cvmx_pciercx_cfg032_s cnf75xx;
2949};
2950
2951typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t;
2952
2953/**
2954 * cvmx_pcierc#_cfg033
2955 *
2956 * This register contains the thirty-fourth 32-bits of PCIe type 1 configuration space.
2957 *
2958 */
2959union cvmx_pciercx_cfg033 {
2960        u32 u32;
2961        struct cvmx_pciercx_cfg033_s {
2962                u32 ps_num : 13;
2963                u32 nccs : 1;
2964                u32 emip : 1;
2965                u32 sp_ls : 2;
2966                u32 sp_lv : 8;
2967                u32 hp_c : 1;
2968                u32 hp_s : 1;
2969                u32 pip : 1;
2970                u32 aip : 1;
2971                u32 mrlsp : 1;
2972                u32 pcp : 1;
2973                u32 abp : 1;
2974        } s;
2975        struct cvmx_pciercx_cfg033_s cn52xx;
2976        struct cvmx_pciercx_cfg033_s cn52xxp1;
2977        struct cvmx_pciercx_cfg033_s cn56xx;
2978        struct cvmx_pciercx_cfg033_s cn56xxp1;
2979        struct cvmx_pciercx_cfg033_s cn61xx;
2980        struct cvmx_pciercx_cfg033_s cn63xx;
2981        struct cvmx_pciercx_cfg033_s cn63xxp1;
2982        struct cvmx_pciercx_cfg033_s cn66xx;
2983        struct cvmx_pciercx_cfg033_s cn68xx;
2984        struct cvmx_pciercx_cfg033_s cn68xxp1;
2985        struct cvmx_pciercx_cfg033_s cn70xx;
2986        struct cvmx_pciercx_cfg033_s cn70xxp1;
2987        struct cvmx_pciercx_cfg033_s cn73xx;
2988        struct cvmx_pciercx_cfg033_s cn78xx;
2989        struct cvmx_pciercx_cfg033_s cn78xxp1;
2990        struct cvmx_pciercx_cfg033_s cnf71xx;
2991        struct cvmx_pciercx_cfg033_s cnf75xx;
2992};
2993
2994typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t;
2995
2996/**
2997 * cvmx_pcierc#_cfg034
2998 *
2999 * This register contains the thirty-fifth 32-bits of PCIe type 1 configuration space.
3000 *

3001 */
3002union cvmx_pciercx_cfg034 {
3003        u32 u32;
3004        struct cvmx_pciercx_cfg034_s {
3005                u32 reserved_25_31 : 7;
3006                u32 dlls_c : 1;
3007                u32 emis : 1;
3008                u32 pds : 1;
3009                u32 mrlss : 1;
3010                u32 ccint_d : 1;
3011                u32 pd_c : 1;
3012                u32 mrls_c : 1;
3013                u32 pf_d : 1;
3014                u32 abp_d : 1;
3015                u32 reserved_13_15 : 3;
3016                u32 dlls_en : 1;
3017                u32 emic : 1;
3018                u32 pcc : 1;
3019                u32 pic : 2;
3020                u32 aic : 2;
3021                u32 hpint_en : 1;
3022                u32 ccint_en : 1;
3023                u32 pd_en : 1;
3024                u32 mrls_en : 1;
3025                u32 pf_en : 1;
3026                u32 abp_en : 1;
3027        } s;
3028        struct cvmx_pciercx_cfg034_s cn52xx;
3029        struct cvmx_pciercx_cfg034_s cn52xxp1;
3030        struct cvmx_pciercx_cfg034_s cn56xx;
3031        struct cvmx_pciercx_cfg034_s cn56xxp1;
3032        struct cvmx_pciercx_cfg034_s cn61xx;
3033        struct cvmx_pciercx_cfg034_s cn63xx;
3034        struct cvmx_pciercx_cfg034_s cn63xxp1;
3035        struct cvmx_pciercx_cfg034_s cn66xx;
3036        struct cvmx_pciercx_cfg034_s cn68xx;
3037        struct cvmx_pciercx_cfg034_s cn68xxp1;
3038        struct cvmx_pciercx_cfg034_s cn70xx;
3039        struct cvmx_pciercx_cfg034_s cn70xxp1;
3040        struct cvmx_pciercx_cfg034_s cn73xx;
3041        struct cvmx_pciercx_cfg034_s cn78xx;
3042        struct cvmx_pciercx_cfg034_s cn78xxp1;
3043        struct cvmx_pciercx_cfg034_s cnf71xx;
3044        struct cvmx_pciercx_cfg034_s cnf75xx;
3045};
3046
3047typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t;
3048
3049/**
3050 * cvmx_pcierc#_cfg035
3051 *
3052 * This register contains the thirty-sixth 32-bits of PCIe type 1 configuration space.
3053 *
3054 */
3055union cvmx_pciercx_cfg035 {
3056        u32 u32;
3057        struct cvmx_pciercx_cfg035_s {
3058                u32 reserved_17_31 : 15;
3059                u32 crssv : 1;
3060                u32 reserved_5_15 : 11;
3061                u32 crssve : 1;
3062                u32 pmeie : 1;
3063                u32 sefee : 1;
3064                u32 senfee : 1;
3065                u32 secee : 1;
3066        } s;
3067        struct cvmx_pciercx_cfg035_s cn52xx;
3068        struct cvmx_pciercx_cfg035_s cn52xxp1;
3069        struct cvmx_pciercx_cfg035_s cn56xx;
3070        struct cvmx_pciercx_cfg035_s cn56xxp1;
3071        struct cvmx_pciercx_cfg035_s cn61xx;
3072        struct cvmx_pciercx_cfg035_s cn63xx;
3073        struct cvmx_pciercx_cfg035_s cn63xxp1;
3074        struct cvmx_pciercx_cfg035_s cn66xx;
3075        struct cvmx_pciercx_cfg035_s cn68xx;
3076        struct cvmx_pciercx_cfg035_s cn68xxp1;
3077        struct cvmx_pciercx_cfg035_s cn70xx;
3078        struct cvmx_pciercx_cfg035_s cn70xxp1;
3079        struct cvmx_pciercx_cfg035_s cn73xx;
3080        struct cvmx_pciercx_cfg035_s cn78xx;
3081        struct cvmx_pciercx_cfg035_s cn78xxp1;
3082        struct cvmx_pciercx_cfg035_s cnf71xx;
3083        struct cvmx_pciercx_cfg035_s cnf75xx;
3084};
3085
3086typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t;
3087
3088/**
3089 * cvmx_pcierc#_cfg036
3090 *
3091 * This register contains the thirty-seventh 32-bits of PCIe type 1 configuration space.
3092 *
3093 */
3094union cvmx_pciercx_cfg036 {
3095        u32 u32;
3096        struct cvmx_pciercx_cfg036_s {
3097                u32 reserved_18_31 : 14;
3098                u32 pme_pend : 1;
3099                u32 pme_stat : 1;
3100                u32 pme_rid : 16;
3101        } s;
3102        struct cvmx_pciercx_cfg036_s cn52xx;
3103        struct cvmx_pciercx_cfg036_s cn52xxp1;
3104        struct cvmx_pciercx_cfg036_s cn56xx;
3105        struct cvmx_pciercx_cfg036_s cn56xxp1;
3106        struct cvmx_pciercx_cfg036_s cn61xx;
3107        struct cvmx_pciercx_cfg036_s cn63xx;
3108        struct cvmx_pciercx_cfg036_s cn63xxp1;
3109        struct cvmx_pciercx_cfg036_s cn66xx;
3110        struct cvmx_pciercx_cfg036_s cn68xx;
3111        struct cvmx_pciercx_cfg036_s cn68xxp1;
3112        struct cvmx_pciercx_cfg036_s cn70xx;
3113        struct cvmx_pciercx_cfg036_s cn70xxp1;
3114        struct cvmx_pciercx_cfg036_s cn73xx;
3115        struct cvmx_pciercx_cfg036_s cn78xx;
3116        struct cvmx_pciercx_cfg036_s cn78xxp1;
3117        struct cvmx_pciercx_cfg036_s cnf71xx;
3118        struct cvmx_pciercx_cfg036_s cnf75xx;
3119};
3120
3121typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t;
3122
3123/**
3124 * cvmx_pcierc#_cfg037
3125 *
3126 * This register contains the thirty-eighth 32-bits of PCIe type 1 configuration space.
3127 *
3128 */
3129union cvmx_pciercx_cfg037 {
3130        u32 u32;
3131        struct cvmx_pciercx_cfg037_s {
3132                u32 reserved_24_31 : 8;
3133                u32 meetp : 2;
3134                u32 eetps : 1;
3135                u32 effs : 1;
3136                u32 obffs : 2;
3137                u32 reserved_12_17 : 6;
3138                u32 ltrs : 1;
3139                u32 noroprpr : 1;
3140                u32 atom128s : 1;
3141                u32 atom64s : 1;
3142                u32 atom32s : 1;
3143                u32 atom_ops : 1;
3144                u32 reserved_5_5 : 1;
3145                u32 ctds : 1;
3146                u32 ctrs : 4;
3147        } s;
3148        struct cvmx_pciercx_cfg037_cn52xx {
3149                u32 reserved_5_31 : 27;
3150                u32 ctds : 1;
3151                u32 ctrs : 4;
3152        } cn52xx;
3153        struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
3154        struct cvmx_pciercx_cfg037_cn52xx cn56xx;
3155        struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
3156        struct cvmx_pciercx_cfg037_cn61xx {
3157                u32 reserved_14_31 : 18;
3158                u32 tph : 2;
3159                u32 reserved_11_11 : 1;
3160                u32 noroprpr : 1;
3161                u32 atom128s : 1;
3162                u32 atom64s : 1;
3163                u32 atom32s : 1;
3164                u32 atom_ops : 1;
3165                u32 ari_fw : 1;
3166                u32 ctds : 1;
3167                u32 ctrs : 4;
3168        } cn61xx;
3169        struct cvmx_pciercx_cfg037_cn52xx cn63xx;
3170        struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
3171        struct cvmx_pciercx_cfg037_cn66xx {
3172                u32 reserved_14_31 : 18;
3173                u32 tph : 2;
3174                u32 reserved_11_11 : 1;
3175                u32 noroprpr : 1;
3176                u32 atom128s : 1;
3177                u32 atom64s : 1;
3178                u32 atom32s : 1;
3179                u32 atom_ops : 1;
3180                u32 ari : 1;
3181                u32 ctds : 1;
3182                u32 ctrs : 4;
3183        } cn66xx;
3184        struct cvmx_pciercx_cfg037_cn66xx cn68xx;
3185        struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
3186        struct cvmx_pciercx_cfg037_cn61xx cn70xx;
3187        struct cvmx_pciercx_cfg037_cn61xx cn70xxp1;
3188        struct cvmx_pciercx_cfg037_cn73xx {
3189                u32 reserved_24_31 : 8;
3190                u32 meetp : 2;
3191                u32 eetps : 1;
3192                u32 effs : 1;
3193                u32 obffs : 2;
3194                u32 reserved_14_17 : 4;
3195                u32 tph : 2;
3196                u32 ltrs : 1;
3197                u32 noroprpr : 1;
3198                u32 atom128s : 1;
3199                u32 atom64s : 1;
3200                u32 atom32s : 1;
3201                u32 atom_ops : 1;
3202                u32 ari_fw : 1;
3203                u32 ctds : 1;
3204                u32 ctrs : 4;
3205        } cn73xx;
3206        struct cvmx_pciercx_cfg037_cn73xx cn78xx;
3207        struct cvmx_pciercx_cfg037_cn73xx cn78xxp1;
3208        struct cvmx_pciercx_cfg037_cnf71xx {
3209                u32 reserved_20_31 : 12;
3210                u32 obffs : 2;
3211                u32 reserved_14_17 : 4;
3212                u32 tphs : 2;
3213                u32 ltrs : 1;
3214                u32 noroprpr : 1;
3215                u32 atom128s : 1;
3216                u32 atom64s : 1;
3217                u32 atom32s : 1;
3218                u32 atom_ops : 1;
3219                u32 ari_fw : 1;
3220                u32 ctds : 1;
3221                u32 ctrs : 4;
3222        } cnf71xx;
3223        struct cvmx_pciercx_cfg037_cn73xx cnf75xx;
3224};
3225
3226typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t;
3227
3228/**
3229 * cvmx_pcierc#_cfg038
3230 *
3231 * This register contains the thirty-ninth 32-bits of PCIe type 1 configuration space.
3232 *
3233 */
3234union cvmx_pciercx_cfg038 {
3235        u32 u32;
3236        struct cvmx_pciercx_cfg038_s {
3237                u32 reserved_16_31 : 16;
3238                u32 eetpb : 1;
3239                u32 obffe : 2;
3240                u32 reserved_11_12 : 2;
3241                u32 ltre : 1;
3242                u32 id0_cp : 1;
3243                u32 id0_rq : 1;
3244                u32 atom_op_eb : 1;
3245                u32 atom_op : 1;
3246                u32 ari : 1;
3247                u32 ctd : 1;
3248                u32 ctv : 4;
3249        } s;
3250        struct cvmx_pciercx_cfg038_cn52xx {
3251                u32 reserved_5_31 : 27;
3252                u32 ctd : 1;
3253                u32 ctv : 4;
3254        } cn52xx;
3255        struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
3256        struct cvmx_pciercx_cfg038_cn52xx cn56xx;
3257        struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
3258        struct cvmx_pciercx_cfg038_cn61xx {
3259                u32 reserved_10_31 : 22;
3260                u32 id0_cp : 1;
3261                u32 id0_rq : 1;
3262                u32 atom_op_eb : 1;
3263                u32 atom_op : 1;
3264                u32 ari : 1;
3265                u32 ctd : 1;
3266                u32 ctv : 4;
3267        } cn61xx;
3268        struct cvmx_pciercx_cfg038_cn52xx cn63xx;
3269        struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
3270        struct cvmx_pciercx_cfg038_cn61xx cn66xx;
3271        struct cvmx_pciercx_cfg038_cn61xx cn68xx;
3272        struct cvmx_pciercx_cfg038_cn61xx cn68xxp1;
3273        struct cvmx_pciercx_cfg038_cn61xx cn70xx;
3274        struct cvmx_pciercx_cfg038_cn61xx cn70xxp1;
3275        struct cvmx_pciercx_cfg038_s cn73xx;
3276        struct cvmx_pciercx_cfg038_s cn78xx;
3277        struct cvmx_pciercx_cfg038_s cn78xxp1;
3278        struct cvmx_pciercx_cfg038_cnf71xx {
3279                u32 reserved_15_31 : 17;
3280                u32 obffe : 2;
3281                u32 reserved_11_12 : 2;
3282                u32 ltre : 1;
3283                u32 id0_cp : 1;
3284                u32 id0_rq : 1;
3285                u32 atom_op_eb : 1;
3286                u32 atom_op : 1;
3287                u32 ari : 1;
3288                u32 ctd : 1;
3289                u32 ctv : 4;
3290        } cnf71xx;
3291        struct cvmx_pciercx_cfg038_s cnf75xx;
3292};
3293
3294typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t;
3295
3296/**
3297 * cvmx_pcierc#_cfg039
3298 *
3299 * This register contains the fortieth 32-bits of PCIe type 1 configuration space.
3300 *
3301 */
3302union cvmx_pciercx_cfg039 {
3303        u32 u32;
3304        struct cvmx_pciercx_cfg039_s {
3305                u32 reserved_9_31 : 23;
3306                u32 cls : 1;
3307                u32 slsv : 7;
3308                u32 reserved_0_0 : 1;
3309        } s;
3310        struct cvmx_pciercx_cfg039_cn52xx {
3311                u32 reserved_0_31 : 32;
3312        } cn52xx;
3313        struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
3314        struct cvmx_pciercx_cfg039_cn52xx cn56xx;
3315        struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
3316        struct cvmx_pciercx_cfg039_s cn61xx;
3317        struct cvmx_pciercx_cfg039_s cn63xx;
3318        struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
3319        struct cvmx_pciercx_cfg039_s cn66xx;
3320        struct cvmx_pciercx_cfg039_s cn68xx;
3321        struct cvmx_pciercx_cfg039_s cn68xxp1;
3322        struct cvmx_pciercx_cfg039_s cn70xx;
3323        struct cvmx_pciercx_cfg039_s cn70xxp1;
3324        struct cvmx_pciercx_cfg039_s cn73xx;
3325        struct cvmx_pciercx_cfg039_s cn78xx;
3326        struct cvmx_pciercx_cfg039_s cn78xxp1;
3327        struct cvmx_pciercx_cfg039_s cnf71xx;
3328        struct cvmx_pciercx_cfg039_s cnf75xx;
3329};
3330
3331typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t;
3332
3333/**
3334 * cvmx_pcierc#_cfg040
3335 *
3336 * This register contains the forty-first 32-bits of PCIe type 1 configuration space.
3337 *
3338 */
3339union cvmx_pciercx_cfg040 {
3340        u32 u32;
3341        struct cvmx_pciercx_cfg040_s {
3342                u32 reserved_22_31 : 10;
3343                u32 ler : 1;
3344                u32 ep3s : 1;
3345                u32 ep2s : 1;
3346                u32 ep1s : 1;
3347                u32 eqc : 1;
3348                u32 cdl : 1;
3349                u32 cde : 4;
3350                u32 csos : 1;
3351                u32 emc : 1;
3352                u32 tm : 3;
3353                u32 sde : 1;
3354                u32 hasd : 1;
3355                u32 ec : 1;
3356                u32 tls : 4;
3357        } s;
3358        struct cvmx_pciercx_cfg040_cn52xx {
3359                u32 reserved_0_31 : 32;
3360        } cn52xx;
3361        struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
3362        struct cvmx_pciercx_cfg040_cn52xx cn56xx;
3363        struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
3364        struct cvmx_pciercx_cfg040_cn61xx {
3365                u32 reserved_17_31 : 15;
3366                u32 cdl : 1;
3367                u32 reserved_13_15 : 3;
3368                u32 cde : 1;
3369                u32 csos : 1;
3370                u32 emc : 1;
3371                u32 tm : 3;
3372                u32 sde : 1;
3373                u32 hasd : 1;
3374                u32 ec : 1;
3375                u32 tls : 4;
3376        } cn61xx;
3377        struct cvmx_pciercx_cfg040_cn61xx cn63xx;
3378        struct cvmx_pciercx_cfg040_cn61xx cn63xxp1;
3379        struct cvmx_pciercx_cfg040_cn61xx cn66xx;
3380        struct cvmx_pciercx_cfg040_cn61xx cn68xx;
3381        struct cvmx_pciercx_cfg040_cn61xx cn68xxp1;
3382        struct cvmx_pciercx_cfg040_cn61xx cn70xx;
3383        struct cvmx_pciercx_cfg040_cn61xx cn70xxp1;
3384        struct cvmx_pciercx_cfg040_s cn73xx;
3385        struct cvmx_pciercx_cfg040_s cn78xx;
3386        struct cvmx_pciercx_cfg040_s cn78xxp1;
3387        struct cvmx_pciercx_cfg040_cn61xx cnf71xx;
3388        struct cvmx_pciercx_cfg040_s cnf75xx;
3389};
3390
3391typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t;
3392
3393/**
3394 * cvmx_pcierc#_cfg041
3395 *
3396 * This register contains the forty-second 32-bits of PCIe type 1 configuration space.
3397 *
3398 */
3399union cvmx_pciercx_cfg041 {
3400        u32 u32;
3401        struct cvmx_pciercx_cfg041_s {
3402                u32 reserved_0_31 : 32;
3403        } s;
3404        struct cvmx_pciercx_cfg041_s cn52xx;
3405        struct cvmx_pciercx_cfg041_s cn52xxp1;
3406        struct cvmx_pciercx_cfg041_s cn56xx;
3407        struct cvmx_pciercx_cfg041_s cn56xxp1;
3408        struct cvmx_pciercx_cfg041_s cn61xx;
3409        struct cvmx_pciercx_cfg041_s cn63xx;
3410        struct cvmx_pciercx_cfg041_s cn63xxp1;
3411        struct cvmx_pciercx_cfg041_s cn66xx;
3412        struct cvmx_pciercx_cfg041_s cn68xx;
3413        struct cvmx_pciercx_cfg041_s cn68xxp1;
3414        struct cvmx_pciercx_cfg041_s cn70xx;
3415        struct cvmx_pciercx_cfg041_s cn70xxp1;
3416        struct cvmx_pciercx_cfg041_s cn73xx;
3417        struct cvmx_pciercx_cfg041_s cn78xx;
3418        struct cvmx_pciercx_cfg041_s cn78xxp1;
3419        struct cvmx_pciercx_cfg041_s cnf71xx;
3420        struct cvmx_pciercx_cfg041_s cnf75xx;
3421};
3422
3423typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t;
3424
3425/**
3426 * cvmx_pcierc#_cfg042
3427 *
3428 * This register contains the forty-third 32-bits of PCIe type 1 configuration space.
3429 *
3430 */
3431union cvmx_pciercx_cfg042 {
3432        u32 u32;
3433        struct cvmx_pciercx_cfg042_s {
3434                u32 reserved_0_31 : 32;
3435        } s;
3436        struct cvmx_pciercx_cfg042_s cn52xx;
3437        struct cvmx_pciercx_cfg042_s cn52xxp1;
3438        struct cvmx_pciercx_cfg042_s cn56xx;
3439        struct cvmx_pciercx_cfg042_s cn56xxp1;
3440        struct cvmx_pciercx_cfg042_s cn61xx;
3441        struct cvmx_pciercx_cfg042_s cn63xx;
3442        struct cvmx_pciercx_cfg042_s cn63xxp1;
3443        struct cvmx_pciercx_cfg042_s cn66xx;
3444        struct cvmx_pciercx_cfg042_s cn68xx;
3445        struct cvmx_pciercx_cfg042_s cn68xxp1;
3446        struct cvmx_pciercx_cfg042_s cn70xx;
3447        struct cvmx_pciercx_cfg042_s cn70xxp1;
3448        struct cvmx_pciercx_cfg042_s cn73xx;
3449        struct cvmx_pciercx_cfg042_s cn78xx;
3450        struct cvmx_pciercx_cfg042_s cn78xxp1;
3451        struct cvmx_pciercx_cfg042_s cnf71xx;
3452        struct cvmx_pciercx_cfg042_s cnf75xx;
3453};
3454
3455typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t;
3456
3457/**
3458 * cvmx_pcierc#_cfg044
3459 *
3460 * This register contains the forty-fifth 32-bits of PCIe type 1 configuration space.
3461 *
3462 */
3463union cvmx_pciercx_cfg044 {
3464        u32 u32;
3465        struct cvmx_pciercx_cfg044_s {
3466                u32 msixen : 1;
3467                u32 funm : 1;
3468                u32 reserved_27_29 : 3;
3469                u32 msixts : 11;
3470                u32 ncp : 8;
3471                u32 msixcid : 8;
3472        } s;
3473        struct cvmx_pciercx_cfg044_s cn73xx;
3474        struct cvmx_pciercx_cfg044_s cn78xx;
3475        struct cvmx_pciercx_cfg044_s cn78xxp1;
3476        struct cvmx_pciercx_cfg044_s cnf75xx;
3477};
3478
3479typedef union cvmx_pciercx_cfg044 cvmx_pciercx_cfg044_t;
3480
3481/**
3482 * cvmx_pcierc#_cfg045
3483 *
3484 * This register contains the forty-sixth 32-bits of PCIe type 1 configuration space.
3485 *
3486 */
3487union cvmx_pciercx_cfg045 {
3488        u32 u32;
3489        struct cvmx_pciercx_cfg045_s {
3490                u32 msixtoffs : 29;
3491                u32 msixtbir : 3;
3492        } s;
3493        struct cvmx_pciercx_cfg045_s cn73xx;
3494        struct cvmx_pciercx_cfg045_s cn78xx;
3495        struct cvmx_pciercx_cfg045_s cn78xxp1;
3496        struct cvmx_pciercx_cfg045_s cnf75xx;
3497};
3498
3499typedef union cvmx_pciercx_cfg045 cvmx_pciercx_cfg045_t;
3500
3501/**
3502 * cvmx_pcierc#_cfg046
3503 *
3504 * This register contains the forty-seventh 32-bits of PCIe type 1 configuration space.
3505 *
3506 */
3507union cvmx_pciercx_cfg046 {
3508        u32 u32;
3509        struct cvmx_pciercx_cfg046_s {
3510                u32 msixpoffs : 29;
3511                u32 msixpbir : 3;
3512        } s;
3513        struct cvmx_pciercx_cfg046_s cn73xx;
3514        struct cvmx_pciercx_cfg046_s cn78xx;
3515        struct cvmx_pciercx_cfg046_s cn78xxp1;
3516        struct cvmx_pciercx_cfg046_s cnf75xx;
3517};
3518
3519typedef union cvmx_pciercx_cfg046 cvmx_pciercx_cfg046_t;
3520
3521/**
3522 * cvmx_pcierc#_cfg064
3523 *
3524 * This register contains the sixty-fifth 32-bits of PCIe type 1 configuration space.
3525 *
3526 */
3527union cvmx_pciercx_cfg064 {
3528        u32 u32;
3529        struct cvmx_pciercx_cfg064_s {
3530                u32 nco : 12;
3531                u32 cv : 4;
3532                u32 pcieec : 16;
3533        } s;
3534        struct cvmx_pciercx_cfg064_s cn52xx;
3535        struct cvmx_pciercx_cfg064_s cn52xxp1;
3536        struct cvmx_pciercx_cfg064_s cn56xx;
3537        struct cvmx_pciercx_cfg064_s cn56xxp1;
3538        struct cvmx_pciercx_cfg064_s cn61xx;
3539        struct cvmx_pciercx_cfg064_s cn63xx;
3540        struct cvmx_pciercx_cfg064_s cn63xxp1;
3541        struct cvmx_pciercx_cfg064_s cn66xx;
3542        struct cvmx_pciercx_cfg064_s cn68xx;
3543        struct cvmx_pciercx_cfg064_s cn68xxp1;
3544        struct cvmx_pciercx_cfg064_s cn70xx;
3545        struct cvmx_pciercx_cfg064_s cn70xxp1;
3546        struct cvmx_pciercx_cfg064_s cn73xx;
3547        struct cvmx_pciercx_cfg064_s cn78xx;
3548        struct cvmx_pciercx_cfg064_s cn78xxp1;
3549        struct cvmx_pciercx_cfg064_s cnf71xx;
3550        struct cvmx_pciercx_cfg064_s cnf75xx;
3551};
3552
3553typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t;
3554
3555/**
3556 * cvmx_pcierc#_cfg065
3557 *
3558 * This register contains the sixty-sixth 32-bits of PCIe type 1 configuration space.
3559 *
3560 */
3561union cvmx_pciercx_cfg065 {
3562        u32 u32;
3563        struct cvmx_pciercx_cfg065_s {
3564                u32 reserved_26_31 : 6;
3565                u32 tpbes : 1;
3566                u32 uatombs : 1;
3567                u32 reserved_23_23 : 1;
3568                u32 ucies : 1;
3569                u32 reserved_21_21 : 1;
3570                u32 ures : 1;
3571                u32 ecrces : 1;
3572                u32 mtlps : 1;
3573                u32 ros : 1;
3574                u32 ucs : 1;
3575                u32 cas : 1;
3576                u32 cts : 1;
3577                u32 fcpes : 1;
3578                u32 ptlps : 1;
3579                u32 reserved_6_11 : 6;
3580                u32 sdes : 1;
3581                u32 dlpes : 1;
3582                u32 reserved_0_3 : 4;
3583        } s;
3584        struct cvmx_pciercx_cfg065_cn52xx {
3585                u32 reserved_21_31 : 11;
3586                u32 ures : 1;
3587                u32 ecrces : 1;
3588                u32 mtlps : 1;
3589                u32 ros : 1;
3590                u32 ucs : 1;
3591                u32 cas : 1;
3592                u32 cts : 1;
3593                u32 fcpes : 1;
3594                u32 ptlps : 1;
3595                u32 reserved_6_11 : 6;
3596                u32 sdes : 1;
3597                u32 dlpes : 1;
3598                u32 reserved_0_3 : 4;
3599        } cn52xx;
3600        struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
3601        struct cvmx_pciercx_cfg065_cn52xx cn56xx;
3602        struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
3603        struct cvmx_pciercx_cfg065_cn61xx {
3604                u32 reserved_25_31 : 7;
3605                u32 uatombs : 1;
3606                u32 reserved_21_23 : 3;
3607                u32 ures : 1;
3608                u32 ecrces : 1;
3609                u32 mtlps : 1;
3610                u32 ros : 1;
3611                u32 ucs : 1;
3612                u32 cas : 1;
3613                u32 cts : 1;
3614                u32 fcpes : 1;
3615                u32 ptlps : 1;
3616                u32 reserved_6_11 : 6;
3617                u32 sdes : 1;
3618                u32 dlpes : 1;
3619                u32 reserved_0_3 : 4;
3620        } cn61xx;
3621        struct cvmx_pciercx_cfg065_cn52xx cn63xx;
3622        struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
3623        struct cvmx_pciercx_cfg065_cn61xx cn66xx;
3624        struct cvmx_pciercx_cfg065_cn61xx cn68xx;
3625        struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
3626        struct cvmx_pciercx_cfg065_cn70xx {
3627                u32 reserved_25_31 : 7;
3628                u32 uatombs : 1;
3629                u32 reserved_23_23 : 1;
3630                u32 ucies : 1;
3631                u32 reserved_21_21 : 1;
3632                u32 ures : 1;
3633                u32 ecrces : 1;
3634                u32 mtlps : 1;
3635                u32 ros : 1;
3636                u32 ucs : 1;
3637                u32 cas : 1;
3638                u32 cts : 1;
3639                u32 fcpes : 1;
3640                u32 ptlps : 1;
3641                u32 reserved_6_11 : 6;
3642                u32 sdes : 1;
3643                u32 dlpes : 1;
3644                u32 reserved_0_3 : 4;
3645        } cn70xx;
3646        struct cvmx_pciercx_cfg065_cn70xx cn70xxp1;
3647        struct cvmx_pciercx_cfg065_s cn73xx;
3648        struct cvmx_pciercx_cfg065_s cn78xx;
3649        struct cvmx_pciercx_cfg065_s cn78xxp1;
3650        struct cvmx_pciercx_cfg065_cn70xx cnf71xx;
3651        struct cvmx_pciercx_cfg065_s cnf75xx;
3652};
3653
3654typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t;
3655
3656/**
3657 * cvmx_pcierc#_cfg066
3658 *
3659 * This register contains the sixty-seventh 32-bits of PCIe type 1 configuration space.
3660 *
3661 */
3662union cvmx_pciercx_cfg066 {
3663        u32 u32;
3664        struct cvmx_pciercx_cfg066_s {
3665                u32 reserved_26_31 : 6;
3666                u32 tpbem : 1;
3667                u32 uatombm : 1;
3668                u32 reserved_23_23 : 1;
3669                u32 uciem : 1;
3670                u32 reserved_21_21 : 1;
3671                u32 urem : 1;
3672                u32 ecrcem : 1;
3673                u32 mtlpm : 1;
3674                u32 rom : 1;
3675                u32 ucm : 1;
3676                u32 cam : 1;
3677                u32 ctm : 1;
3678                u32 fcpem : 1;
3679                u32 ptlpm : 1;
3680                u32 reserved_6_11 : 6;
3681                u32 sdem : 1;
3682                u32 dlpem : 1;
3683                u32 reserved_0_3 : 4;
3684        } s;
3685        struct cvmx_pciercx_cfg066_cn52xx {
3686                u32 reserved_21_31 : 11;
3687                u32 urem : 1;
3688                u32 ecrcem : 1;
3689                u32 mtlpm : 1;
3690                u32 rom : 1;
3691                u32 ucm : 1;
3692                u32 cam : 1;
3693                u32 ctm : 1;
3694                u32 fcpem : 1;
3695                u32 ptlpm : 1;
3696                u32 reserved_6_11 : 6;
3697                u32 sdem : 1;
3698                u32 dlpem : 1;
3699                u32 reserved_0_3 : 4;
3700        } cn52xx;
3701        struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
3702        struct cvmx_pciercx_cfg066_cn52xx cn56xx;
3703        struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
3704        struct cvmx_pciercx_cfg066_cn61xx {
3705                u32 reserved_25_31 : 7;
3706                u32 uatombm : 1;
3707                u32 reserved_21_23 : 3;
3708                u32 urem : 1;
3709                u32 ecrcem : 1;
3710                u32 mtlpm : 1;
3711                u32 rom : 1;
3712                u32 ucm : 1;
3713                u32 cam : 1;
3714                u32 ctm : 1;
3715                u32 fcpem : 1;
3716                u32 ptlpm : 1;
3717                u32 reserved_6_11 : 6;
3718                u32 sdem : 1;
3719                u32 dlpem : 1;
3720                u32 reserved_0_3 : 4;
3721        } cn61xx;
3722        struct cvmx_pciercx_cfg066_cn52xx cn63xx;
3723        struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
3724        struct cvmx_pciercx_cfg066_cn61xx cn66xx;
3725        struct cvmx_pciercx_cfg066_cn61xx cn68xx;
3726        struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
3727        struct cvmx_pciercx_cfg066_cn70xx {
3728                u32 reserved_25_31 : 7;
3729                u32 uatombm : 1;
3730                u32 reserved_23_23 : 1;
3731                u32 uciem : 1;
3732                u32 reserved_21_21 : 1;
3733                u32 urem : 1;
3734                u32 ecrcem : 1;
3735                u32 mtlpm : 1;
3736                u32 rom : 1;
3737                u32 ucm : 1;
3738                u32 cam : 1;
3739                u32 ctm : 1;
3740                u32 fcpem : 1;
3741                u32 ptlpm : 1;
3742                u32 reserved_6_11 : 6;
3743                u32 sdem : 1;
3744                u32 dlpem : 1;
3745                u32 reserved_0_3 : 4;
3746        } cn70xx;
3747        struct cvmx_pciercx_cfg066_cn70xx cn70xxp1;
3748        struct cvmx_pciercx_cfg066_s cn73xx;
3749        struct cvmx_pciercx_cfg066_s cn78xx;
3750        struct cvmx_pciercx_cfg066_s cn78xxp1;
3751        struct cvmx_pciercx_cfg066_cn70xx cnf71xx;
3752        struct cvmx_pciercx_cfg066_s cnf75xx;
3753};
3754
3755typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t;
3756
3757/**
3758 * cvmx_pcierc#_cfg067
3759 *
3760 * This register contains the sixty-eighth 32-bits of PCIe type 1 configuration space.
3761 *
3762 */
3763union cvmx_pciercx_cfg067 {
3764        u32 u32;
3765        struct cvmx_pciercx_cfg067_s {
3766                u32 reserved_26_31 : 6;
3767                u32 tpbes : 1;
3768                u32 uatombs : 1;
3769                u32 reserved_21_23 : 3;
3770                u32 ures : 1;
3771                u32 ecrces : 1;
3772                u32 mtlps : 1;
3773                u32 ros : 1;
3774                u32 ucs : 1;
3775                u32 cas : 1;
3776                u32 cts : 1;
3777                u32 fcpes : 1;
3778                u32 ptlps : 1;
3779                u32 reserved_6_11 : 6;
3780                u32 sdes : 1;
3781                u32 dlpes : 1;
3782                u32 reserved_0_3 : 4;
3783        } s;
3784        struct cvmx_pciercx_cfg067_cn52xx {
3785                u32 reserved_21_31 : 11;
3786                u32 ures : 1;
3787                u32 ecrces : 1;
3788                u32 mtlps : 1;
3789                u32 ros : 1;
3790                u32 ucs : 1;
3791                u32 cas : 1;
3792                u32 cts : 1;
3793                u32 fcpes : 1;
3794                u32 ptlps : 1;
3795                u32 reserved_6_11 : 6;
3796                u32 sdes : 1;
3797                u32 dlpes : 1;
3798                u32 reserved_0_3 : 4;
3799        } cn52xx;
3800        struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
3801        struct cvmx_pciercx_cfg067_cn52xx cn56xx;
3802        struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
3803        struct cvmx_pciercx_cfg067_cn61xx {
3804                u32 reserved_25_31 : 7;
3805                u32 uatombs : 1;
3806                u32 reserved_21_23 : 3;
3807                u32 ures : 1;
3808                u32 ecrces : 1;
3809                u32 mtlps : 1;
3810                u32 ros : 1;
3811                u32 ucs : 1;
3812                u32 cas : 1;
3813                u32 cts : 1;
3814                u32 fcpes : 1;
3815                u32 ptlps : 1;
3816                u32 reserved_6_11 : 6;
3817                u32 sdes : 1;
3818                u32 dlpes : 1;
3819                u32 reserved_0_3 : 4;
3820        } cn61xx;
3821        struct cvmx_pciercx_cfg067_cn52xx cn63xx;
3822        struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
3823        struct cvmx_pciercx_cfg067_cn61xx cn66xx;
3824        struct cvmx_pciercx_cfg067_cn61xx cn68xx;
3825        struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
3826        struct cvmx_pciercx_cfg067_cn70xx {
3827                u32 reserved_25_31 : 7;
3828                u32 uatombs : 1;
3829                u32 reserved_23_23 : 1;
3830                u32 ucies : 1;
3831                u32 reserved_21_21 : 1;
3832                u32 ures : 1;
3833                u32 ecrces : 1;
3834                u32 mtlps : 1;
3835                u32 ros : 1;
3836                u32 ucs : 1;
3837                u32 cas : 1;
3838                u32 cts : 1;
3839                u32 fcpes : 1;
3840                u32 ptlps : 1;
3841                u32 reserved_6_11 : 6;
3842                u32 sdes : 1;
3843                u32 dlpes : 1;
3844                u32 reserved_0_3 : 4;
3845        } cn70xx;
3846        struct cvmx_pciercx_cfg067_cn70xx cn70xxp1;
3847        struct cvmx_pciercx_cfg067_cn73xx {
3848                u32 reserved_26_31 : 6;
3849                u32 tpbes : 1;
3850                u32 uatombs : 1;
3851                u32 unsuperr : 3;
3852                u32 ures : 1;
3853                u32 ecrces : 1;
3854                u32 mtlps : 1;
3855                u32 ros : 1;
3856                u32 ucs : 1;
3857                u32 cas : 1;
3858                u32 cts : 1;
3859                u32 fcpes : 1;
3860                u32 ptlps : 1;
3861                u32 reserved_6_11 : 6;
3862                u32 sdes : 1;
3863                u32 dlpes : 1;
3864                u32 reserved_0_3 : 4;
3865        } cn73xx;
3866        struct cvmx_pciercx_cfg067_cn73xx cn78xx;
3867        struct cvmx_pciercx_cfg067_cn73xx cn78xxp1;
3868        struct cvmx_pciercx_cfg067_cn70xx cnf71xx;
3869        struct cvmx_pciercx_cfg067_cn73xx cnf75xx;
3870};
3871
3872typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t;
3873
3874/**
3875 * cvmx_pcierc#_cfg068
3876 *
3877 * This register contains the sixty-ninth 32-bits of PCIe type 1 configuration space.
3878 *
3879 */
3880union cvmx_pciercx_cfg068 {
3881        u32 u32;
3882        struct cvmx_pciercx_cfg068_s {
3883                u32 reserved_15_31 : 17;
3884                u32 cies : 1;
3885                u32 anfes : 1;
3886                u32 rtts : 1;
3887                u32 reserved_9_11 : 3;
3888                u32 rnrs : 1;
3889                u32 bdllps : 1;
3890                u32 btlps : 1;
3891                u32 reserved_1_5 : 5;
3892                u32 res : 1;
3893        } s;
3894        struct cvmx_pciercx_cfg068_cn52xx {
3895                u32 reserved_14_31 : 18;
3896                u32 anfes : 1;
3897                u32 rtts : 1;
3898                u32 reserved_9_11 : 3;
3899                u32 rnrs : 1;
3900                u32 bdllps : 1;
3901                u32 btlps : 1;
3902                u32 reserved_1_5 : 5;
3903                u32 res : 1;
3904        } cn52xx;
3905        struct cvmx_pciercx_cfg068_cn52xx cn52xxp1;
3906        struct cvmx_pciercx_cfg068_cn52xx cn56xx;
3907        struct cvmx_pciercx_cfg068_cn52xx cn56xxp1;
3908        struct cvmx_pciercx_cfg068_cn52xx cn61xx;
3909        struct cvmx_pciercx_cfg068_cn52xx cn63xx;
3910        struct cvmx_pciercx_cfg068_cn52xx cn63xxp1;
3911        struct cvmx_pciercx_cfg068_cn52xx cn66xx;
3912        struct cvmx_pciercx_cfg068_cn52xx cn68xx;
3913        struct cvmx_pciercx_cfg068_cn52xx cn68xxp1;
3914        struct cvmx_pciercx_cfg068_s cn70xx;
3915        struct cvmx_pciercx_cfg068_s cn70xxp1;
3916        struct cvmx_pciercx_cfg068_s cn73xx;
3917        struct cvmx_pciercx_cfg068_s cn78xx;
3918        struct cvmx_pciercx_cfg068_s cn78xxp1;
3919        struct cvmx_pciercx_cfg068_s cnf71xx;
3920        struct cvmx_pciercx_cfg068_s cnf75xx;
3921};
3922
3923typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t;
3924
3925/**
3926 * cvmx_pcierc#_cfg069
3927 *
3928 * This register contains the seventieth 32-bits of PCIe type 1 configuration space.
3929 *
3930 */
3931union cvmx_pciercx_cfg069 {
3932        u32 u32;
3933        struct cvmx_pciercx_cfg069_s {
3934                u32 reserved_15_31 : 17;
3935                u32 ciem : 1;
3936                u32 anfem : 1;
3937                u32 rttm : 1;
3938                u32 reserved_9_11 : 3;
3939                u32 rnrm : 1;
3940                u32 bdllpm : 1;
3941                u32 btlpm : 1;
3942                u32 reserved_1_5 : 5;
3943                u32 rem : 1;
3944        } s;
3945        struct cvmx_pciercx_cfg069_cn52xx {
3946                u32 reserved_14_31 : 18;
3947                u32 anfem : 1;
3948                u32 rttm : 1;
3949                u32 reserved_9_11 : 3;
3950                u32 rnrm : 1;
3951                u32 bdllpm : 1;
3952                u32 btlpm : 1;
3953                u32 reserved_1_5 : 5;
3954                u32 rem : 1;
3955        } cn52xx;
3956        struct cvmx_pciercx_cfg069_cn52xx cn52xxp1;
3957        struct cvmx_pciercx_cfg069_cn52xx cn56xx;
3958        struct cvmx_pciercx_cfg069_cn52xx cn56xxp1;
3959        struct cvmx_pciercx_cfg069_cn52xx cn61xx;
3960        struct cvmx_pciercx_cfg069_cn52xx cn63xx;
3961        struct cvmx_pciercx_cfg069_cn52xx cn63xxp1;
3962        struct cvmx_pciercx_cfg069_cn52xx cn66xx;
3963        struct cvmx_pciercx_cfg069_cn52xx cn68xx;
3964        struct cvmx_pciercx_cfg069_cn52xx cn68xxp1;
3965        struct cvmx_pciercx_cfg069_s cn70xx;
3966        struct cvmx_pciercx_cfg069_s cn70xxp1;
3967        struct cvmx_pciercx_cfg069_s cn73xx;
3968        struct cvmx_pciercx_cfg069_s cn78xx;
3969        struct cvmx_pciercx_cfg069_s cn78xxp1;
3970        struct cvmx_pciercx_cfg069_s cnf71xx;
3971        struct cvmx_pciercx_cfg069_s cnf75xx;
3972};
3973
3974typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t;
3975
3976/**
3977 * cvmx_pcierc#_cfg070
3978 *
3979 * This register contains the seventy-first 32-bits of PCIe type 1 configuration space.
3980 *
3981 */
3982union cvmx_pciercx_cfg070 {
3983        u32 u32;
3984        struct cvmx_pciercx_cfg070_s {
3985                u32 reserved_12_31 : 20;
3986                u32 tplp : 1;
3987                u32 reserved_9_10 : 2;
3988                u32 ce : 1;
3989                u32 cc : 1;
3990                u32 ge : 1;
3991                u32 gc : 1;
3992                u32 fep : 5;
3993        } s;
3994        struct cvmx_pciercx_cfg070_cn52xx {
3995                u32 reserved_9_31 : 23;
3996                u32 ce : 1;
3997                u32 cc : 1;
3998                u32 ge : 1;
3999                u32 gc : 1;
4000                u32 fep : 5;

4001        } cn52xx;
4002        struct cvmx_pciercx_cfg070_cn52xx cn52xxp1;
4003        struct cvmx_pciercx_cfg070_cn52xx cn56xx;
4004        struct cvmx_pciercx_cfg070_cn52xx cn56xxp1;
4005        struct cvmx_pciercx_cfg070_cn52xx cn61xx;
4006        struct cvmx_pciercx_cfg070_cn52xx cn63xx;
4007        struct cvmx_pciercx_cfg070_cn52xx cn63xxp1;
4008        struct cvmx_pciercx_cfg070_cn52xx cn66xx;
4009        struct cvmx_pciercx_cfg070_cn52xx cn68xx;
4010        struct cvmx_pciercx_cfg070_cn52xx cn68xxp1;
4011        struct cvmx_pciercx_cfg070_cn52xx cn70xx;
4012        struct cvmx_pciercx_cfg070_cn52xx cn70xxp1;
4013        struct cvmx_pciercx_cfg070_s cn73xx;
4014        struct cvmx_pciercx_cfg070_s cn78xx;
4015        struct cvmx_pciercx_cfg070_s cn78xxp1;
4016        struct cvmx_pciercx_cfg070_cn52xx cnf71xx;
4017        struct cvmx_pciercx_cfg070_s cnf75xx;
4018};
4019
4020typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t;
4021
4022/**
4023 * cvmx_pcierc#_cfg071
4024 *
4025 * This register contains the seventy-second 32-bits of PCIe type 1 configuration space.  The
4026 * header log registers collect the header for the TLP corresponding to a detected error.
4027 */
4028union cvmx_pciercx_cfg071 {
4029        u32 u32;
4030        struct cvmx_pciercx_cfg071_s {
4031                u32 dword1 : 32;
4032        } s;
4033        struct cvmx_pciercx_cfg071_s cn52xx;
4034        struct cvmx_pciercx_cfg071_s cn52xxp1;
4035        struct cvmx_pciercx_cfg071_s cn56xx;
4036        struct cvmx_pciercx_cfg071_s cn56xxp1;
4037        struct cvmx_pciercx_cfg071_s cn61xx;
4038        struct cvmx_pciercx_cfg071_s cn63xx;
4039        struct cvmx_pciercx_cfg071_s cn63xxp1;
4040        struct cvmx_pciercx_cfg071_s cn66xx;
4041        struct cvmx_pciercx_cfg071_s cn68xx;
4042        struct cvmx_pciercx_cfg071_s cn68xxp1;
4043        struct cvmx_pciercx_cfg071_s cn70xx;
4044        struct cvmx_pciercx_cfg071_s cn70xxp1;
4045        struct cvmx_pciercx_cfg071_s cn73xx;
4046        struct cvmx_pciercx_cfg071_s cn78xx;
4047        struct cvmx_pciercx_cfg071_s cn78xxp1;
4048        struct cvmx_pciercx_cfg071_s cnf71xx;
4049        struct cvmx_pciercx_cfg071_s cnf75xx;
4050};
4051
4052typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t;
4053
4054/**
4055 * cvmx_pcierc#_cfg072
4056 *
4057 * This register contains the seventy-third 32-bits of PCIe type 1 configuration space.  The
4058 * header log registers collect the header for the TLP corresponding to a detected error.
4059 */
4060union cvmx_pciercx_cfg072 {
4061        u32 u32;
4062        struct cvmx_pciercx_cfg072_s {
4063                u32 dword2 : 32;
4064        } s;
4065        struct cvmx_pciercx_cfg072_s cn52xx;
4066        struct cvmx_pciercx_cfg072_s cn52xxp1;
4067        struct cvmx_pciercx_cfg072_s cn56xx;
4068        struct cvmx_pciercx_cfg072_s cn56xxp1;
4069        struct cvmx_pciercx_cfg072_s cn61xx;
4070        struct cvmx_pciercx_cfg072_s cn63xx;
4071        struct cvmx_pciercx_cfg072_s cn63xxp1;
4072        struct cvmx_pciercx_cfg072_s cn66xx;
4073        struct cvmx_pciercx_cfg072_s cn68xx;
4074        struct cvmx_pciercx_cfg072_s cn68xxp1;
4075        struct cvmx_pciercx_cfg072_s cn70xx;
4076        struct cvmx_pciercx_cfg072_s cn70xxp1;
4077        struct cvmx_pciercx_cfg072_s cn73xx;
4078        struct cvmx_pciercx_cfg072_s cn78xx;
4079        struct cvmx_pciercx_cfg072_s cn78xxp1;
4080        struct cvmx_pciercx_cfg072_s cnf71xx;
4081        struct cvmx_pciercx_cfg072_s cnf75xx;
4082};
4083
4084typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t;
4085
4086/**
4087 * cvmx_pcierc#_cfg073
4088 *
4089 * This register contains the seventy-fourth 32-bits of PCIe type 1 configuration space.  The
4090 * header log registers collect the header for the TLP corresponding to a detected error.
4091 */
4092union cvmx_pciercx_cfg073 {
4093        u32 u32;
4094        struct cvmx_pciercx_cfg073_s {
4095                u32 dword3 : 32;
4096        } s;
4097        struct cvmx_pciercx_cfg073_s cn52xx;
4098        struct cvmx_pciercx_cfg073_s cn52xxp1;
4099        struct cvmx_pciercx_cfg073_s cn56xx;
4100        struct cvmx_pciercx_cfg073_s cn56xxp1;
4101        struct cvmx_pciercx_cfg073_s cn61xx;
4102        struct cvmx_pciercx_cfg073_s cn63xx;
4103        struct cvmx_pciercx_cfg073_s cn63xxp1;
4104        struct cvmx_pciercx_cfg073_s cn66xx;
4105        struct cvmx_pciercx_cfg073_s cn68xx;
4106        struct cvmx_pciercx_cfg073_s cn68xxp1;
4107        struct cvmx_pciercx_cfg073_s cn70xx;
4108        struct cvmx_pciercx_cfg073_s cn70xxp1;
4109        struct cvmx_pciercx_cfg073_s cn73xx;
4110        struct cvmx_pciercx_cfg073_s cn78xx;
4111        struct cvmx_pciercx_cfg073_s cn78xxp1;
4112        struct cvmx_pciercx_cfg073_s cnf71xx;
4113        struct cvmx_pciercx_cfg073_s cnf75xx;
4114};
4115
4116typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t;
4117
4118/**
4119 * cvmx_pcierc#_cfg074
4120 *
4121 * This register contains the seventy-fifth 32-bits of PCIe type 1 configuration space.  The
4122 * header log registers collect the header for the TLP corresponding to a detected error.
4123 */
4124union cvmx_pciercx_cfg074 {
4125        u32 u32;
4126        struct cvmx_pciercx_cfg074_s {
4127                u32 dword4 : 32;
4128        } s;
4129        struct cvmx_pciercx_cfg074_s cn52xx;
4130        struct cvmx_pciercx_cfg074_s cn52xxp1;
4131        struct cvmx_pciercx_cfg074_s cn56xx;
4132        struct cvmx_pciercx_cfg074_s cn56xxp1;
4133        struct cvmx_pciercx_cfg074_s cn61xx;
4134        struct cvmx_pciercx_cfg074_s cn63xx;
4135        struct cvmx_pciercx_cfg074_s cn63xxp1;
4136        struct cvmx_pciercx_cfg074_s cn66xx;
4137        struct cvmx_pciercx_cfg074_s cn68xx;
4138        struct cvmx_pciercx_cfg074_s cn68xxp1;
4139        struct cvmx_pciercx_cfg074_s cn70xx;
4140        struct cvmx_pciercx_cfg074_s cn70xxp1;
4141        struct cvmx_pciercx_cfg074_s cn73xx;
4142        struct cvmx_pciercx_cfg074_s cn78xx;
4143        struct cvmx_pciercx_cfg074_s cn78xxp1;
4144        struct cvmx_pciercx_cfg074_s cnf71xx;
4145        struct cvmx_pciercx_cfg074_s cnf75xx;
4146};
4147
4148typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t;
4149
4150/**
4151 * cvmx_pcierc#_cfg075
4152 *
4153 * This register contains the seventy-sixth 32-bits of PCIe type 1 configuration space.
4154 *
4155 */
4156union cvmx_pciercx_cfg075 {
4157        u32 u32;
4158        struct cvmx_pciercx_cfg075_s {
4159                u32 reserved_3_31 : 29;
4160                u32 fere : 1;
4161                u32 nfere : 1;
4162                u32 cere : 1;
4163        } s;
4164        struct cvmx_pciercx_cfg075_s cn52xx;
4165        struct cvmx_pciercx_cfg075_s cn52xxp1;
4166        struct cvmx_pciercx_cfg075_s cn56xx;
4167        struct cvmx_pciercx_cfg075_s cn56xxp1;
4168        struct cvmx_pciercx_cfg075_s cn61xx;
4169        struct cvmx_pciercx_cfg075_s cn63xx;
4170        struct cvmx_pciercx_cfg075_s cn63xxp1;
4171        struct cvmx_pciercx_cfg075_s cn66xx;
4172        struct cvmx_pciercx_cfg075_s cn68xx;
4173        struct cvmx_pciercx_cfg075_s cn68xxp1;
4174        struct cvmx_pciercx_cfg075_s cn70xx;
4175        struct cvmx_pciercx_cfg075_s cn70xxp1;
4176        struct cvmx_pciercx_cfg075_s cn73xx;
4177        struct cvmx_pciercx_cfg075_s cn78xx;
4178        struct cvmx_pciercx_cfg075_s cn78xxp1;
4179        struct cvmx_pciercx_cfg075_s cnf71xx;
4180        struct cvmx_pciercx_cfg075_s cnf75xx;
4181};
4182
4183typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t;
4184
4185/**
4186 * cvmx_pcierc#_cfg076
4187 *
4188 * This register contains the seventy-seventh 32-bits of PCIe type 1 configuration space.
4189 *
4190 */
4191union cvmx_pciercx_cfg076 {
4192        u32 u32;
4193        struct cvmx_pciercx_cfg076_s {
4194                u32 aeimn : 5;
4195                u32 reserved_7_26 : 20;
4196                u32 femr : 1;
4197                u32 nfemr : 1;
4198                u32 fuf : 1;
4199                u32 multi_efnfr : 1;
4200                u32 efnfr : 1;
4201                u32 multi_ecr : 1;
4202                u32 ecr : 1;
4203        } s;
4204        struct cvmx_pciercx_cfg076_s cn52xx;
4205        struct cvmx_pciercx_cfg076_s cn52xxp1;
4206        struct cvmx_pciercx_cfg076_s cn56xx;
4207        struct cvmx_pciercx_cfg076_s cn56xxp1;
4208        struct cvmx_pciercx_cfg076_s cn61xx;
4209        struct cvmx_pciercx_cfg076_s cn63xx;
4210        struct cvmx_pciercx_cfg076_s cn63xxp1;
4211        struct cvmx_pciercx_cfg076_s cn66xx;
4212        struct cvmx_pciercx_cfg076_s cn68xx;
4213        struct cvmx_pciercx_cfg076_s cn68xxp1;
4214        struct cvmx_pciercx_cfg076_s cn70xx;
4215        struct cvmx_pciercx_cfg076_s cn70xxp1;
4216        struct cvmx_pciercx_cfg076_s cn73xx;
4217        struct cvmx_pciercx_cfg076_s cn78xx;
4218        struct cvmx_pciercx_cfg076_s cn78xxp1;
4219        struct cvmx_pciercx_cfg076_s cnf71xx;
4220        struct cvmx_pciercx_cfg076_s cnf75xx;
4221};
4222
4223typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t;
4224
4225/**
4226 * cvmx_pcierc#_cfg077
4227 *
4228 * This register contains the seventy-eighth 32-bits of PCIe type 1 configuration space.
4229 *
4230 */
4231union cvmx_pciercx_cfg077 {
4232        u32 u32;
4233        struct cvmx_pciercx_cfg077_s {
4234                u32 efnfsi : 16;
4235                u32 ecsi : 16;
4236        } s;
4237        struct cvmx_pciercx_cfg077_s cn52xx;
4238        struct cvmx_pciercx_cfg077_s cn52xxp1;
4239        struct cvmx_pciercx_cfg077_s cn56xx;
4240        struct cvmx_pciercx_cfg077_s cn56xxp1;
4241        struct cvmx_pciercx_cfg077_s cn61xx;
4242        struct cvmx_pciercx_cfg077_s cn63xx;
4243        struct cvmx_pciercx_cfg077_s cn63xxp1;
4244        struct cvmx_pciercx_cfg077_s cn66xx;
4245        struct cvmx_pciercx_cfg077_s cn68xx;
4246        struct cvmx_pciercx_cfg077_s cn68xxp1;
4247        struct cvmx_pciercx_cfg077_s cn70xx;
4248        struct cvmx_pciercx_cfg077_s cn70xxp1;
4249        struct cvmx_pciercx_cfg077_s cn73xx;
4250        struct cvmx_pciercx_cfg077_s cn78xx;
4251        struct cvmx_pciercx_cfg077_s cn78xxp1;
4252        struct cvmx_pciercx_cfg077_s cnf71xx;
4253        struct cvmx_pciercx_cfg077_s cnf75xx;
4254};
4255
4256typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t;
4257
4258/**
4259 * cvmx_pcierc#_cfg086
4260 *
4261 * This register contains the eighty-ninth 32-bits of type 0 PCIe configuration space.
4262 *
4263 */
4264union cvmx_pciercx_cfg086 {
4265        u32 u32;
4266        struct cvmx_pciercx_cfg086_s {
4267                u32 nco : 12;
4268                u32 cv : 4;
4269                u32 pcieec : 16;
4270        } s;
4271        struct cvmx_pciercx_cfg086_s cn73xx;
4272        struct cvmx_pciercx_cfg086_s cn78xx;
4273        struct cvmx_pciercx_cfg086_s cn78xxp1;
4274        struct cvmx_pciercx_cfg086_s cnf75xx;
4275};
4276
4277typedef union cvmx_pciercx_cfg086 cvmx_pciercx_cfg086_t;
4278
4279/**
4280 * cvmx_pcierc#_cfg087
4281 *
4282 * This register contains the eighty-eighth 32-bits of type 0 PCIe configuration space.
4283 *
4284 */
4285union cvmx_pciercx_cfg087 {
4286        u32 u32;
4287        struct cvmx_pciercx_cfg087_s {
4288                u32 reserved_2_31 : 30;
4289                u32 ler : 1;
4290                u32 pe : 1;
4291        } s;
4292        struct cvmx_pciercx_cfg087_s cn73xx;
4293        struct cvmx_pciercx_cfg087_s cn78xx;
4294        struct cvmx_pciercx_cfg087_s cn78xxp1;
4295        struct cvmx_pciercx_cfg087_s cnf75xx;
4296};
4297
4298typedef union cvmx_pciercx_cfg087 cvmx_pciercx_cfg087_t;
4299
4300/**
4301 * cvmx_pcierc#_cfg088
4302 *
4303 * This register contains the eighty-ninth 32-bits of type 0 PCIe configuration space.
4304 *
4305 */
4306union cvmx_pciercx_cfg088 {
4307        u32 u32;
4308        struct cvmx_pciercx_cfg088_s {
4309                u32 reserved_8_31 : 24;
4310                u32 les : 8;
4311        } s;
4312        struct cvmx_pciercx_cfg088_s cn73xx;
4313        struct cvmx_pciercx_cfg088_s cn78xx;
4314        struct cvmx_pciercx_cfg088_s cn78xxp1;
4315        struct cvmx_pciercx_cfg088_s cnf75xx;
4316};
4317
4318typedef union cvmx_pciercx_cfg088 cvmx_pciercx_cfg088_t;
4319
4320/**
4321 * cvmx_pcierc#_cfg089
4322 *
4323 * This register contains the ninetieth 32-bits of type 0 PCIe configuration space.
4324 *
4325 */
4326union cvmx_pciercx_cfg089 {
4327        u32 u32;
4328        struct cvmx_pciercx_cfg089_s {
4329                u32 reserved_31_31 : 1;
4330                u32 l1urph : 3;
4331                u32 l1utp : 4;
4332                u32 reserved_23_23 : 1;
4333                u32 l1drph : 3;
4334                u32 l1ddtp : 4;
4335                u32 reserved_15_15 : 1;
4336                u32 l0urph : 3;
4337                u32 l0utp : 4;
4338                u32 reserved_7_7 : 1;
4339                u32 l0drph : 3;
4340                u32 l0dtp : 4;
4341        } s;
4342        struct cvmx_pciercx_cfg089_s cn73xx;
4343        struct cvmx_pciercx_cfg089_s cn78xx;
4344        struct cvmx_pciercx_cfg089_s cn78xxp1;
4345        struct cvmx_pciercx_cfg089_s cnf75xx;
4346};
4347
4348typedef union cvmx_pciercx_cfg089 cvmx_pciercx_cfg089_t;
4349
4350/**
4351 * cvmx_pcierc#_cfg090
4352 *
4353 * This register contains the ninety-first 32-bits of type 0 PCIe configuration space.
4354 *
4355 */
4356union cvmx_pciercx_cfg090 {
4357        u32 u32;
4358        struct cvmx_pciercx_cfg090_s {
4359                u32 reserved_31_31 : 1;
4360                u32 l3urph : 3;
4361                u32 l3utp : 4;
4362                u32 reserved_23_23 : 1;
4363                u32 l3drph : 3;
4364                u32 l3dtp : 4;
4365                u32 reserved_15_15 : 1;
4366                u32 l2urph : 3;
4367                u32 l2utp : 4;
4368                u32 reserved_7_7 : 1;
4369                u32 l2drph : 3;
4370                u32 l2dtp : 4;
4371        } s;
4372        struct cvmx_pciercx_cfg090_s cn73xx;
4373        struct cvmx_pciercx_cfg090_s cn78xx;
4374        struct cvmx_pciercx_cfg090_s cn78xxp1;
4375        struct cvmx_pciercx_cfg090_s cnf75xx;
4376};
4377
4378typedef union cvmx_pciercx_cfg090 cvmx_pciercx_cfg090_t;
4379
4380/**
4381 * cvmx_pcierc#_cfg091
4382 *
4383 * This register contains the ninety-second 32-bits of type 0 PCIe configuration space.
4384 *
4385 */
4386union cvmx_pciercx_cfg091 {
4387        u32 u32;
4388        struct cvmx_pciercx_cfg091_s {
4389                u32 reserved_31_31 : 1;
4390                u32 l5urph : 3;
4391                u32 l5utp : 4;
4392                u32 reserved_23_23 : 1;
4393                u32 l5drph : 3;
4394                u32 l5dtp : 4;
4395                u32 reserved_15_15 : 1;
4396                u32 l4urph : 3;
4397                u32 l4utp : 4;
4398                u32 reserved_7_7 : 1;
4399                u32 l4drph : 3;
4400                u32 l4dtp : 4;
4401        } s;
4402        struct cvmx_pciercx_cfg091_s cn73xx;
4403        struct cvmx_pciercx_cfg091_s cn78xx;
4404        struct cvmx_pciercx_cfg091_s cn78xxp1;
4405        struct cvmx_pciercx_cfg091_s cnf75xx;
4406};
4407
4408typedef union cvmx_pciercx_cfg091 cvmx_pciercx_cfg091_t;
4409
4410/**
4411 * cvmx_pcierc#_cfg092
4412 *
4413 * This register contains the ninety-third 32-bits of type 0 PCIe configuration space.
4414 *
4415 */
4416union cvmx_pciercx_cfg092 {
4417        u32 u32;
4418        struct cvmx_pciercx_cfg092_s {
4419                u32 reserved_31_31 : 1;
4420                u32 l7urph : 3;
4421                u32 l7utp : 4;
4422                u32 reserved_23_23 : 1;
4423                u32 l7drph : 3;
4424                u32 l7dtp : 4;
4425                u32 reserved_15_15 : 1;
4426                u32 l6urph : 3;
4427                u32 l6utp : 4;
4428                u32 reserved_7_7 : 1;
4429                u32 l6drph : 3;
4430                u32 l6dtp : 4;
4431        } s;
4432        struct cvmx_pciercx_cfg092_s cn73xx;
4433        struct cvmx_pciercx_cfg092_s cn78xx;
4434        struct cvmx_pciercx_cfg092_s cn78xxp1;
4435        struct cvmx_pciercx_cfg092_s cnf75xx;
4436};
4437
4438typedef union cvmx_pciercx_cfg092 cvmx_pciercx_cfg092_t;
4439
4440/**
4441 * cvmx_pcierc#_cfg448
4442 *
4443 * This register contains the four hundred forty-ninth 32-bits of PCIe type 1 configuration space.
4444 *
4445 */
4446union cvmx_pciercx_cfg448 {
4447        u32 u32;
4448        struct cvmx_pciercx_cfg448_s {
4449                u32 rtl : 16;
4450                u32 rtltl : 16;
4451        } s;
4452        struct cvmx_pciercx_cfg448_s cn52xx;
4453        struct cvmx_pciercx_cfg448_s cn52xxp1;
4454        struct cvmx_pciercx_cfg448_s cn56xx;
4455        struct cvmx_pciercx_cfg448_s cn56xxp1;
4456        struct cvmx_pciercx_cfg448_s cn61xx;
4457        struct cvmx_pciercx_cfg448_s cn63xx;
4458        struct cvmx_pciercx_cfg448_s cn63xxp1;
4459        struct cvmx_pciercx_cfg448_s cn66xx;
4460        struct cvmx_pciercx_cfg448_s cn68xx;
4461        struct cvmx_pciercx_cfg448_s cn68xxp1;
4462        struct cvmx_pciercx_cfg448_s cn70xx;
4463        struct cvmx_pciercx_cfg448_s cn70xxp1;
4464        struct cvmx_pciercx_cfg448_s cn73xx;
4465        struct cvmx_pciercx_cfg448_s cn78xx;
4466        struct cvmx_pciercx_cfg448_s cn78xxp1;
4467        struct cvmx_pciercx_cfg448_s cnf71xx;
4468        struct cvmx_pciercx_cfg448_s cnf75xx;
4469};
4470
4471typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t;
4472
4473/**
4474 * cvmx_pcierc#_cfg449
4475 *
4476 * This register contains the four hundred fiftieth 32-bits of PCIe type 1 configuration space.
4477 *
4478 */
4479union cvmx_pciercx_cfg449 {
4480        u32 u32;
4481        struct cvmx_pciercx_cfg449_s {
4482                u32 omr : 32;
4483        } s;
4484        struct cvmx_pciercx_cfg449_s cn52xx;
4485        struct cvmx_pciercx_cfg449_s cn52xxp1;
4486        struct cvmx_pciercx_cfg449_s cn56xx;
4487        struct cvmx_pciercx_cfg449_s cn56xxp1;
4488        struct cvmx_pciercx_cfg449_s cn61xx;
4489        struct cvmx_pciercx_cfg449_s cn63xx;
4490        struct cvmx_pciercx_cfg449_s cn63xxp1;
4491        struct cvmx_pciercx_cfg449_s cn66xx;
4492        struct cvmx_pciercx_cfg449_s cn68xx;
4493        struct cvmx_pciercx_cfg449_s cn68xxp1;
4494        struct cvmx_pciercx_cfg449_s cn70xx;
4495        struct cvmx_pciercx_cfg449_s cn70xxp1;
4496        struct cvmx_pciercx_cfg449_s cn73xx;
4497        struct cvmx_pciercx_cfg449_s cn78xx;
4498        struct cvmx_pciercx_cfg449_s cn78xxp1;
4499        struct cvmx_pciercx_cfg449_s cnf71xx;
4500        struct cvmx_pciercx_cfg449_s cnf75xx;
4501};
4502
4503typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t;
4504
4505/**
4506 * cvmx_pcierc#_cfg450
4507 *
4508 * This register contains the four hundred fifty-first 32-bits of PCIe type 1 configuration space.
4509 *
4510 */
4511union cvmx_pciercx_cfg450 {
4512        u32 u32;
4513        struct cvmx_pciercx_cfg450_s {
4514                u32 lpec : 8;
4515                u32 reserved_22_23 : 2;
4516                u32 link_state : 6;
4517                u32 force_link : 1;
4518                u32 reserved_8_14 : 7;
4519                u32 link_num : 8;
4520        } s;
4521        struct cvmx_pciercx_cfg450_s cn52xx;
4522        struct cvmx_pciercx_cfg450_s cn52xxp1;
4523        struct cvmx_pciercx_cfg450_s cn56xx;
4524        struct cvmx_pciercx_cfg450_s cn56xxp1;
4525        struct cvmx_pciercx_cfg450_s cn61xx;
4526        struct cvmx_pciercx_cfg450_s cn63xx;
4527        struct cvmx_pciercx_cfg450_s cn63xxp1;
4528        struct cvmx_pciercx_cfg450_s cn66xx;
4529        struct cvmx_pciercx_cfg450_s cn68xx;
4530        struct cvmx_pciercx_cfg450_s cn68xxp1;
4531        struct cvmx_pciercx_cfg450_cn70xx {
4532                u32 lpec : 8;
4533                u32 reserved_22_23 : 2;
4534                u32 link_state : 6;
4535                u32 force_link : 1;
4536                u32 reserved_12_14 : 3;
4537                u32 link_cmd : 4;
4538                u32 link_num : 8;
4539        } cn70xx;
4540        struct cvmx_pciercx_cfg450_cn70xx cn70xxp1;
4541        struct cvmx_pciercx_cfg450_cn73xx {
4542                u32 lpec : 8;
4543                u32 reserved_22_23 : 2;
4544                u32 link_state : 6;
4545                u32 force_link : 1;
4546                u32 reserved_12_14 : 3;
4547                u32 forced_ltssm : 4;
4548                u32 link_num : 8;
4549        } cn73xx;
4550        struct cvmx_pciercx_cfg450_cn73xx cn78xx;
4551        struct cvmx_pciercx_cfg450_cn73xx cn78xxp1;
4552        struct cvmx_pciercx_cfg450_s cnf71xx;
4553        struct cvmx_pciercx_cfg450_cn73xx cnf75xx;
4554};
4555
4556typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t;
4557
4558/**
4559 * cvmx_pcierc#_cfg451
4560 *
4561 * This register contains the four hundred fifty-second 32-bits of PCIe type 1 configuration space.
4562 *
4563 */
4564union cvmx_pciercx_cfg451 {
4565        u32 u32;
4566        struct cvmx_pciercx_cfg451_s {
4567                u32 reserved_31_31 : 1;
4568                u32 easpml1 : 1;
4569                u32 l1el : 3;
4570                u32 l0el : 3;
4571                u32 n_fts_cc : 8;
4572                u32 n_fts : 8;
4573                u32 ack_freq : 8;
4574        } s;
4575        struct cvmx_pciercx_cfg451_cn52xx {
4576                u32 reserved_30_31 : 2;
4577                u32 l1el : 3;
4578                u32 l0el : 3;
4579                u32 n_fts_cc : 8;
4580                u32 n_fts : 8;
4581                u32 ack_freq : 8;
4582        } cn52xx;
4583        struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
4584        struct cvmx_pciercx_cfg451_cn52xx cn56xx;
4585        struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
4586        struct cvmx_pciercx_cfg451_s cn61xx;
4587        struct cvmx_pciercx_cfg451_cn52xx cn63xx;
4588        struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
4589        struct cvmx_pciercx_cfg451_s cn66xx;
4590        struct cvmx_pciercx_cfg451_s cn68xx;
4591        struct cvmx_pciercx_cfg451_s cn68xxp1;
4592        struct cvmx_pciercx_cfg451_s cn70xx;
4593        struct cvmx_pciercx_cfg451_s cn70xxp1;
4594        struct cvmx_pciercx_cfg451_s cn73xx;
4595        struct cvmx_pciercx_cfg451_s cn78xx;
4596        struct cvmx_pciercx_cfg451_s cn78xxp1;
4597        struct cvmx_pciercx_cfg451_s cnf71xx;
4598        struct cvmx_pciercx_cfg451_s cnf75xx;
4599};
4600
4601typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t;
4602
4603/**
4604 * cvmx_pcierc#_cfg452
4605 *
4606 * This register contains the four hundred fifty-third 32-bits of PCIe type 1 configuration space.
4607 *
4608 */
4609union cvmx_pciercx_cfg452 {
4610        u32 u32;
4611        struct cvmx_pciercx_cfg452_s {
4612                u32 reserved_26_31 : 6;
4613                u32 eccrc : 1;
4614                u32 reserved_22_24 : 3;
4615                u32 lme : 6;
4616                u32 reserved_12_15 : 4;
4617                u32 link_rate : 4;
4618                u32 flm : 1;
4619                u32 reserved_6_6 : 1;
4620                u32 dllle : 1;
4621                u32 reserved_4_4 : 1;
4622                u32 ra : 1;
4623                u32 le : 1;
4624                u32 sd : 1;
4625                u32 omr : 1;
4626        } s;
4627        struct cvmx_pciercx_cfg452_cn52xx {
4628                u32 reserved_26_31 : 6;
4629                u32 eccrc : 1;
4630                u32 reserved_22_24 : 3;
4631                u32 lme : 6;
4632                u32 reserved_8_15 : 8;
4633                u32 flm : 1;
4634                u32 reserved_6_6 : 1;
4635                u32 dllle : 1;
4636                u32 reserved_4_4 : 1;
4637                u32 ra : 1;
4638                u32 le : 1;
4639                u32 sd : 1;
4640                u32 omr : 1;
4641        } cn52xx;
4642        struct cvmx_pciercx_cfg452_cn52xx cn52xxp1;
4643        struct cvmx_pciercx_cfg452_cn52xx cn56xx;
4644        struct cvmx_pciercx_cfg452_cn52xx cn56xxp1;
4645        struct cvmx_pciercx_cfg452_cn61xx {
4646                u32 reserved_22_31 : 10;
4647                u32 lme : 6;
4648                u32 reserved_8_15 : 8;
4649                u32 flm : 1;
4650                u32 reserved_6_6 : 1;
4651                u32 dllle : 1;
4652                u32 reserved_4_4 : 1;
4653                u32 ra : 1;
4654                u32 le : 1;
4655                u32 sd : 1;
4656                u32 omr : 1;
4657        } cn61xx;
4658        struct cvmx_pciercx_cfg452_cn52xx cn63xx;
4659        struct cvmx_pciercx_cfg452_cn52xx cn63xxp1;
4660        struct cvmx_pciercx_cfg452_cn61xx cn66xx;
4661        struct cvmx_pciercx_cfg452_cn61xx cn68xx;
4662        struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
4663        struct cvmx_pciercx_cfg452_cn70xx {
4664                u32 reserved_22_31 : 10;
4665                u32 lme : 6;
4666                u32 reserved_12_15 : 4;
4667                u32 link_rate : 4;
4668                u32 flm : 1;
4669                u32 reserved_6_6 : 1;
4670                u32 dllle : 1;
4671                u32 reserved_4_4 : 1;
4672                u32 ra : 1;
4673                u32 le : 1;
4674                u32 sd : 1;
4675                u32 omr : 1;
4676        } cn70xx;
4677        struct cvmx_pciercx_cfg452_cn70xx cn70xxp1;
4678        struct cvmx_pciercx_cfg452_cn70xx cn73xx;
4679        struct cvmx_pciercx_cfg452_cn70xx cn78xx;
4680        struct cvmx_pciercx_cfg452_cn70xx cn78xxp1;
4681        struct cvmx_pciercx_cfg452_cn61xx cnf71xx;
4682        struct cvmx_pciercx_cfg452_cn70xx cnf75xx;
4683};
4684
4685typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t;
4686
4687/**
4688 * cvmx_pcierc#_cfg453
4689 *
4690 * This register contains the four hundred fifty-fourth 32-bits of PCIe type 1 configuration space.
4691 *
4692 */
4693union cvmx_pciercx_cfg453 {
4694        u32 u32;
4695        struct cvmx_pciercx_cfg453_s {
4696                u32 dlld : 1;
4697                u32 reserved_26_30 : 5;
4698                u32 ack_nak : 1;
4699                u32 fcd : 1;
4700                u32 ilst : 24;
4701        } s;
4702        struct cvmx_pciercx_cfg453_s cn52xx;
4703        struct cvmx_pciercx_cfg453_s cn52xxp1;
4704        struct cvmx_pciercx_cfg453_s cn56xx;
4705        struct cvmx_pciercx_cfg453_s cn56xxp1;
4706        struct cvmx_pciercx_cfg453_s cn61xx;
4707        struct cvmx_pciercx_cfg453_s cn63xx;
4708        struct cvmx_pciercx_cfg453_s cn63xxp1;
4709        struct cvmx_pciercx_cfg453_s cn66xx;
4710        struct cvmx_pciercx_cfg453_s cn68xx;
4711        struct cvmx_pciercx_cfg453_s cn68xxp1;
4712        struct cvmx_pciercx_cfg453_s cn70xx;
4713        struct cvmx_pciercx_cfg453_s cn70xxp1;
4714        struct cvmx_pciercx_cfg453_s cn73xx;
4715        struct cvmx_pciercx_cfg453_s cn78xx;
4716        struct cvmx_pciercx_cfg453_s cn78xxp1;
4717        struct cvmx_pciercx_cfg453_s cnf71xx;
4718        struct cvmx_pciercx_cfg453_s cnf75xx;
4719};
4720
4721typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t;
4722
4723/**
4724 * cvmx_pcierc#_cfg454
4725 *
4726 * This register contains the four hundred fifty-fifth 32-bits of PCIe type 1 configuration space.
4727 *
4728 */
4729union cvmx_pciercx_cfg454 {
4730        u32 u32;
4731        struct cvmx_pciercx_cfg454_s {
4732                u32 cx_nfunc : 3;
4733                u32 tmfcwt : 5;
4734                u32 tmanlt : 5;
4735                u32 tmrt : 5;
4736                u32 reserved_11_13 : 3;
4737                u32 nskps : 3;
4738                u32 reserved_0_7 : 8;
4739        } s;
4740        struct cvmx_pciercx_cfg454_cn52xx {
4741                u32 reserved_29_31 : 3;
4742                u32 tmfcwt : 5;
4743                u32 tmanlt : 5;
4744                u32 tmrt : 5;
4745                u32 reserved_11_13 : 3;
4746                u32 nskps : 3;
4747                u32 reserved_4_7 : 4;
4748                u32 ntss : 4;
4749        } cn52xx;
4750        struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
4751        struct cvmx_pciercx_cfg454_cn52xx cn56xx;
4752        struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
4753        struct cvmx_pciercx_cfg454_cn61xx {
4754                u32 cx_nfunc : 3;
4755                u32 tmfcwt : 5;
4756                u32 tmanlt : 5;
4757                u32 tmrt : 5;
4758                u32 reserved_8_13 : 6;
4759                u32 mfuncn : 8;
4760        } cn61xx;
4761        struct cvmx_pciercx_cfg454_cn52xx cn63xx;
4762        struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
4763        struct cvmx_pciercx_cfg454_cn61xx cn66xx;
4764        struct cvmx_pciercx_cfg454_cn61xx cn68xx;
4765        struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
4766        struct cvmx_pciercx_cfg454_cn70xx {
4767                u32 reserved_24_31 : 8;
4768                u32 tmanlt : 5;
4769                u32 tmrt : 5;
4770                u32 reserved_8_13 : 6;
4771                u32 mfuncn : 8;
4772        } cn70xx;
4773        struct cvmx_pciercx_cfg454_cn70xx cn70xxp1;
4774        struct cvmx_pciercx_cfg454_cn73xx {
4775                u32 reserved_29_31 : 3;
4776                u32 tmfcwt : 5;
4777                u32 tmanlt : 5;
4778                u32 tmrt : 5;
4779                u32 reserved_8_13 : 6;
4780                u32 mfuncn : 8;
4781        } cn73xx;
4782        struct cvmx_pciercx_cfg454_cn73xx cn78xx;
4783        struct cvmx_pciercx_cfg454_cn73xx cn78xxp1;
4784        struct cvmx_pciercx_cfg454_cn61xx cnf71xx;
4785        struct cvmx_pciercx_cfg454_cn73xx cnf75xx;
4786};
4787
4788typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t;
4789
4790/**
4791 * cvmx_pcierc#_cfg455
4792 *
4793 * This register contains the four hundred fifty-sixth 32-bits of PCIe type 1 configuration space.
4794 *
4795 */
4796union cvmx_pciercx_cfg455 {
4797        u32 u32;
4798        struct cvmx_pciercx_cfg455_s {
4799                u32 m_cfg0_filt : 1;
4800                u32 m_io_filt : 1;
4801                u32 msg_ctrl : 1;
4802                u32 m_cpl_ecrc_filt : 1;
4803                u32 m_ecrc_filt : 1;
4804                u32 m_cpl_len_err : 1;
4805                u32 m_cpl_attr_err : 1;
4806                u32 m_cpl_tc_err : 1;
4807                u32 m_cpl_fun_err : 1;
4808                u32 m_cpl_rid_err : 1;
4809                u32 m_cpl_tag_err : 1;
4810                u32 m_lk_filt : 1;
4811                u32 m_cfg1_filt : 1;
4812                u32 m_bar_match : 1;
4813                u32 m_pois_filt : 1;
4814                u32 m_fun : 1;
4815                u32 dfcwt : 1;
4816                u32 reserved_11_14 : 4;
4817                u32 skpiv : 11;
4818        } s;
4819        struct cvmx_pciercx_cfg455_s cn52xx;
4820        struct cvmx_pciercx_cfg455_s cn52xxp1;
4821        struct cvmx_pciercx_cfg455_s cn56xx;
4822        struct cvmx_pciercx_cfg455_s cn56xxp1;
4823        struct cvmx_pciercx_cfg455_s cn61xx;
4824        struct cvmx_pciercx_cfg455_s cn63xx;
4825        struct cvmx_pciercx_cfg455_s cn63xxp1;
4826        struct cvmx_pciercx_cfg455_s cn66xx;
4827        struct cvmx_pciercx_cfg455_s cn68xx;
4828        struct cvmx_pciercx_cfg455_s cn68xxp1;
4829        struct cvmx_pciercx_cfg455_s cn70xx;
4830        struct cvmx_pciercx_cfg455_s cn70xxp1;
4831        struct cvmx_pciercx_cfg455_s cn73xx;
4832        struct cvmx_pciercx_cfg455_s cn78xx;
4833        struct cvmx_pciercx_cfg455_s cn78xxp1;
4834        struct cvmx_pciercx_cfg455_s cnf71xx;
4835        struct cvmx_pciercx_cfg455_s cnf75xx;
4836};
4837
4838typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t;
4839
4840/**
4841 * cvmx_pcierc#_cfg456
4842 *
4843 * This register contains the four hundred fifty-seventh 32-bits of PCIe type 1 configuration space.
4844 *
4845 */
4846union cvmx_pciercx_cfg456 {
4847        u32 u32;
4848        struct cvmx_pciercx_cfg456_s {
4849                u32 reserved_4_31 : 28;
4850                u32 m_handle_flush : 1;
4851                u32 m_dabort_4ucpl : 1;
4852                u32 m_vend1_drp : 1;
4853                u32 m_vend0_drp : 1;
4854        } s;
4855        struct cvmx_pciercx_cfg456_cn52xx {
4856                u32 reserved_2_31 : 30;
4857                u32 m_vend1_drp : 1;
4858                u32 m_vend0_drp : 1;
4859        } cn52xx;
4860        struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
4861        struct cvmx_pciercx_cfg456_cn52xx cn56xx;
4862        struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
4863        struct cvmx_pciercx_cfg456_s cn61xx;
4864        struct cvmx_pciercx_cfg456_cn52xx cn63xx;
4865        struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
4866        struct cvmx_pciercx_cfg456_s cn66xx;
4867        struct cvmx_pciercx_cfg456_s cn68xx;
4868        struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
4869        struct cvmx_pciercx_cfg456_s cn70xx;
4870        struct cvmx_pciercx_cfg456_s cn70xxp1;
4871        struct cvmx_pciercx_cfg456_s cn73xx;
4872        struct cvmx_pciercx_cfg456_s cn78xx;
4873        struct cvmx_pciercx_cfg456_s cn78xxp1;
4874        struct cvmx_pciercx_cfg456_s cnf71xx;
4875        struct cvmx_pciercx_cfg456_s cnf75xx;
4876};
4877
4878typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t;
4879
4880/**
4881 * cvmx_pcierc#_cfg458
4882 *
4883 * This register contains the four hundred fifty-ninth 32-bits of PCIe type 1 configuration space.
4884 *
4885 */
4886union cvmx_pciercx_cfg458 {
4887        u32 u32;
4888        struct cvmx_pciercx_cfg458_s {
4889                u32 dbg_info_l32 : 32;
4890        } s;
4891        struct cvmx_pciercx_cfg458_s cn52xx;
4892        struct cvmx_pciercx_cfg458_s cn52xxp1;
4893        struct cvmx_pciercx_cfg458_s cn56xx;
4894        struct cvmx_pciercx_cfg458_s cn56xxp1;
4895        struct cvmx_pciercx_cfg458_s cn61xx;
4896        struct cvmx_pciercx_cfg458_s cn63xx;
4897        struct cvmx_pciercx_cfg458_s cn63xxp1;
4898        struct cvmx_pciercx_cfg458_s cn66xx;
4899        struct cvmx_pciercx_cfg458_s cn68xx;
4900        struct cvmx_pciercx_cfg458_s cn68xxp1;
4901        struct cvmx_pciercx_cfg458_s cn70xx;
4902        struct cvmx_pciercx_cfg458_s cn70xxp1;
4903        struct cvmx_pciercx_cfg458_s cn73xx;
4904        struct cvmx_pciercx_cfg458_s cn78xx;
4905        struct cvmx_pciercx_cfg458_s cn78xxp1;
4906        struct cvmx_pciercx_cfg458_s cnf71xx;
4907        struct cvmx_pciercx_cfg458_s cnf75xx;
4908};
4909
4910typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t;
4911
4912/**
4913 * cvmx_pcierc#_cfg459
4914 *
4915 * This register contains the four hundred sixtieth 32-bits of PCIe type 1 configuration space.
4916 *
4917 */
4918union cvmx_pciercx_cfg459 {
4919        u32 u32;
4920        struct cvmx_pciercx_cfg459_s {
4921                u32 dbg_info_u32 : 32;
4922        } s;
4923        struct cvmx_pciercx_cfg459_s cn52xx;
4924        struct cvmx_pciercx_cfg459_s cn52xxp1;
4925        struct cvmx_pciercx_cfg459_s cn56xx;
4926        struct cvmx_pciercx_cfg459_s cn56xxp1;
4927        struct cvmx_pciercx_cfg459_s cn61xx;
4928        struct cvmx_pciercx_cfg459_s cn63xx;
4929        struct cvmx_pciercx_cfg459_s cn63xxp1;
4930        struct cvmx_pciercx_cfg459_s cn66xx;
4931        struct cvmx_pciercx_cfg459_s cn68xx;
4932        struct cvmx_pciercx_cfg459_s cn68xxp1;
4933        struct cvmx_pciercx_cfg459_s cn70xx;
4934        struct cvmx_pciercx_cfg459_s cn70xxp1;
4935        struct cvmx_pciercx_cfg459_s cn73xx;
4936        struct cvmx_pciercx_cfg459_s cn78xx;
4937        struct cvmx_pciercx_cfg459_s cn78xxp1;
4938        struct cvmx_pciercx_cfg459_s cnf71xx;
4939        struct cvmx_pciercx_cfg459_s cnf75xx;
4940};
4941
4942typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t;
4943
4944/**
4945 * cvmx_pcierc#_cfg460
4946 *
4947 * This register contains the four hundred sixty-first 32-bits of PCIe type 1 configuration space.
4948 *
4949 */
4950union cvmx_pciercx_cfg460 {
4951        u32 u32;
4952        struct cvmx_pciercx_cfg460_s {
4953                u32 reserved_20_31 : 12;
4954                u32 tphfcc : 8;
4955                u32 tpdfcc : 12;
4956        } s;
4957        struct cvmx_pciercx_cfg460_s cn52xx;
4958        struct cvmx_pciercx_cfg460_s cn52xxp1;
4959        struct cvmx_pciercx_cfg460_s cn56xx;
4960        struct cvmx_pciercx_cfg460_s cn56xxp1;
4961        struct cvmx_pciercx_cfg460_s cn61xx;
4962        struct cvmx_pciercx_cfg460_s cn63xx;
4963        struct cvmx_pciercx_cfg460_s cn63xxp1;
4964        struct cvmx_pciercx_cfg460_s cn66xx;
4965        struct cvmx_pciercx_cfg460_s cn68xx;
4966        struct cvmx_pciercx_cfg460_s cn68xxp1;
4967        struct cvmx_pciercx_cfg460_s cn70xx;
4968        struct cvmx_pciercx_cfg460_s cn70xxp1;
4969        struct cvmx_pciercx_cfg460_s cn73xx;
4970        struct cvmx_pciercx_cfg460_s cn78xx;
4971        struct cvmx_pciercx_cfg460_s cn78xxp1;
4972        struct cvmx_pciercx_cfg460_s cnf71xx;
4973        struct cvmx_pciercx_cfg460_s cnf75xx;
4974};
4975
4976typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t;
4977
4978/**
4979 * cvmx_pcierc#_cfg461
4980 *
4981 * This register contains the four hundred sixty-second 32-bits of PCIe type 1 configuration space.
4982 *
4983 */
4984union cvmx_pciercx_cfg461 {
4985        u32 u32;
4986        struct cvmx_pciercx_cfg461_s {
4987                u32 reserved_20_31 : 12;
4988                u32 tchfcc : 8;
4989                u32 tcdfcc : 12;
4990        } s;
4991        struct cvmx_pciercx_cfg461_s cn52xx;
4992        struct cvmx_pciercx_cfg461_s cn52xxp1;
4993        struct cvmx_pciercx_cfg461_s cn56xx;
4994        struct cvmx_pciercx_cfg461_s cn56xxp1;
4995        struct cvmx_pciercx_cfg461_s cn61xx;
4996        struct cvmx_pciercx_cfg461_s cn63xx;
4997        struct cvmx_pciercx_cfg461_s cn63xxp1;
4998        struct cvmx_pciercx_cfg461_s cn66xx;
4999        struct cvmx_pciercx_cfg461_s cn68xx;
5000        struct cvmx_pciercx_cfg461_s cn68xxp1;

5001        struct cvmx_pciercx_cfg461_s cn70xx;
5002        struct cvmx_pciercx_cfg461_s cn70xxp1;
5003        struct cvmx_pciercx_cfg461_s cn73xx;
5004        struct cvmx_pciercx_cfg461_s cn78xx;
5005        struct cvmx_pciercx_cfg461_s cn78xxp1;
5006        struct cvmx_pciercx_cfg461_s cnf71xx;
5007        struct cvmx_pciercx_cfg461_s cnf75xx;
5008};
5009
5010typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t;
5011
5012/**
5013 * cvmx_pcierc#_cfg462
5014 *
5015 * This register contains the four hundred sixty-third 32-bits of PCIe type 1 configuration space.
5016 *
5017 */
5018union cvmx_pciercx_cfg462 {
5019        u32 u32;
5020        struct cvmx_pciercx_cfg462_s {
5021                u32 reserved_20_31 : 12;
5022                u32 tchfcc : 8;
5023                u32 tcdfcc : 12;
5024        } s;
5025        struct cvmx_pciercx_cfg462_s cn52xx;
5026        struct cvmx_pciercx_cfg462_s cn52xxp1;
5027        struct cvmx_pciercx_cfg462_s cn56xx;
5028        struct cvmx_pciercx_cfg462_s cn56xxp1;
5029        struct cvmx_pciercx_cfg462_s cn61xx;
5030        struct cvmx_pciercx_cfg462_s cn63xx;
5031        struct cvmx_pciercx_cfg462_s cn63xxp1;
5032        struct cvmx_pciercx_cfg462_s cn66xx;
5033        struct cvmx_pciercx_cfg462_s cn68xx;
5034        struct cvmx_pciercx_cfg462_s cn68xxp1;
5035        struct cvmx_pciercx_cfg462_s cn70xx;
5036        struct cvmx_pciercx_cfg462_s cn70xxp1;
5037        struct cvmx_pciercx_cfg462_s cn73xx;
5038        struct cvmx_pciercx_cfg462_s cn78xx;
5039        struct cvmx_pciercx_cfg462_s cn78xxp1;
5040        struct cvmx_pciercx_cfg462_s cnf71xx;
5041        struct cvmx_pciercx_cfg462_s cnf75xx;
5042};
5043
5044typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t;
5045
5046/**
5047 * cvmx_pcierc#_cfg463
5048 *
5049 * This register contains the four hundred sixty-fourth 32-bits of PCIe type 1 configuration space.
5050 *
5051 */
5052union cvmx_pciercx_cfg463 {
5053        u32 u32;
5054        struct cvmx_pciercx_cfg463_s {
5055                u32 fcltoe : 1;
5056                u32 reserved_29_30 : 2;
5057                u32 fcltov : 13;
5058                u32 reserved_3_15 : 13;
5059                u32 rqne : 1;
5060                u32 trbne : 1;
5061                u32 rtlpfccnr : 1;
5062        } s;
5063        struct cvmx_pciercx_cfg463_cn52xx {
5064                u32 reserved_3_31 : 29;
5065                u32 rqne : 1;
5066                u32 trbne : 1;
5067                u32 rtlpfccnr : 1;
5068        } cn52xx;
5069        struct cvmx_pciercx_cfg463_cn52xx cn52xxp1;
5070        struct cvmx_pciercx_cfg463_cn52xx cn56xx;
5071        struct cvmx_pciercx_cfg463_cn52xx cn56xxp1;
5072        struct cvmx_pciercx_cfg463_cn52xx cn61xx;
5073        struct cvmx_pciercx_cfg463_cn52xx cn63xx;
5074        struct cvmx_pciercx_cfg463_cn52xx cn63xxp1;
5075        struct cvmx_pciercx_cfg463_cn52xx cn66xx;
5076        struct cvmx_pciercx_cfg463_cn52xx cn68xx;
5077        struct cvmx_pciercx_cfg463_cn52xx cn68xxp1;
5078        struct cvmx_pciercx_cfg463_cn52xx cn70xx;
5079        struct cvmx_pciercx_cfg463_cn52xx cn70xxp1;
5080        struct cvmx_pciercx_cfg463_s cn73xx;
5081        struct cvmx_pciercx_cfg463_s cn78xx;
5082        struct cvmx_pciercx_cfg463_s cn78xxp1;
5083        struct cvmx_pciercx_cfg463_cn52xx cnf71xx;
5084        struct cvmx_pciercx_cfg463_s cnf75xx;
5085};
5086
5087typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t;
5088
5089/**
5090 * cvmx_pcierc#_cfg464
5091 *
5092 * This register contains the four hundred sixty-fifth 32-bits of PCIe type 1 configuration space.
5093 *
5094 */
5095union cvmx_pciercx_cfg464 {
5096        u32 u32;
5097        struct cvmx_pciercx_cfg464_s {
5098                u32 wrr_vc3 : 8;
5099                u32 wrr_vc2 : 8;
5100                u32 wrr_vc1 : 8;
5101                u32 wrr_vc0 : 8;
5102        } s;
5103        struct cvmx_pciercx_cfg464_s cn52xx;
5104        struct cvmx_pciercx_cfg464_s cn52xxp1;
5105        struct cvmx_pciercx_cfg464_s cn56xx;
5106        struct cvmx_pciercx_cfg464_s cn56xxp1;
5107        struct cvmx_pciercx_cfg464_s cn61xx;
5108        struct cvmx_pciercx_cfg464_s cn63xx;
5109        struct cvmx_pciercx_cfg464_s cn63xxp1;
5110        struct cvmx_pciercx_cfg464_s cn66xx;
5111        struct cvmx_pciercx_cfg464_s cn68xx;
5112        struct cvmx_pciercx_cfg464_s cn68xxp1;
5113        struct cvmx_pciercx_cfg464_s cn70xx;
5114        struct cvmx_pciercx_cfg464_s cn70xxp1;
5115        struct cvmx_pciercx_cfg464_s cn73xx;
5116        struct cvmx_pciercx_cfg464_s cn78xx;
5117        struct cvmx_pciercx_cfg464_s cn78xxp1;
5118        struct cvmx_pciercx_cfg464_s cnf71xx;
5119        struct cvmx_pciercx_cfg464_s cnf75xx;
5120};
5121
5122typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t;
5123
5124/**
5125 * cvmx_pcierc#_cfg465
5126 *
5127 * This register contains the four hundred sixty-sixth 32-bits of configuration space.
5128 *
5129 */
5130union cvmx_pciercx_cfg465 {
5131        u32 u32;
5132        struct cvmx_pciercx_cfg465_s {
5133                u32 wrr_vc7 : 8;
5134                u32 wrr_vc6 : 8;
5135                u32 wrr_vc5 : 8;
5136                u32 wrr_vc4 : 8;
5137        } s;
5138        struct cvmx_pciercx_cfg465_s cn52xx;
5139        struct cvmx_pciercx_cfg465_s cn52xxp1;
5140        struct cvmx_pciercx_cfg465_s cn56xx;
5141        struct cvmx_pciercx_cfg465_s cn56xxp1;
5142        struct cvmx_pciercx_cfg465_s cn61xx;
5143        struct cvmx_pciercx_cfg465_s cn63xx;
5144        struct cvmx_pciercx_cfg465_s cn63xxp1;
5145        struct cvmx_pciercx_cfg465_s cn66xx;
5146        struct cvmx_pciercx_cfg465_s cn68xx;
5147        struct cvmx_pciercx_cfg465_s cn68xxp1;
5148        struct cvmx_pciercx_cfg465_s cn70xx;
5149        struct cvmx_pciercx_cfg465_s cn70xxp1;
5150        struct cvmx_pciercx_cfg465_s cn73xx;
5151        struct cvmx_pciercx_cfg465_s cn78xx;
5152        struct cvmx_pciercx_cfg465_s cn78xxp1;
5153        struct cvmx_pciercx_cfg465_s cnf71xx;
5154        struct cvmx_pciercx_cfg465_s cnf75xx;
5155};
5156
5157typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t;
5158
5159/**
5160 * cvmx_pcierc#_cfg466
5161 *
5162 * This register contains the four hundred sixty-seventh 32-bits of PCIe type 1 configuration space.
5163 *
5164 */
5165union cvmx_pciercx_cfg466 {
5166        u32 u32;
5167        struct cvmx_pciercx_cfg466_s {
5168                u32 rx_queue_order : 1;
5169                u32 type_ordering : 1;
5170                u32 reserved_24_29 : 6;
5171                u32 queue_mode : 3;
5172                u32 reserved_20_20 : 1;
5173                u32 header_credits : 8;
5174                u32 data_credits : 12;
5175        } s;
5176        struct cvmx_pciercx_cfg466_s cn52xx;
5177        struct cvmx_pciercx_cfg466_s cn52xxp1;
5178        struct cvmx_pciercx_cfg466_s cn56xx;
5179        struct cvmx_pciercx_cfg466_s cn56xxp1;
5180        struct cvmx_pciercx_cfg466_s cn61xx;
5181        struct cvmx_pciercx_cfg466_s cn63xx;
5182        struct cvmx_pciercx_cfg466_s cn63xxp1;
5183        struct cvmx_pciercx_cfg466_s cn66xx;
5184        struct cvmx_pciercx_cfg466_s cn68xx;
5185        struct cvmx_pciercx_cfg466_s cn68xxp1;
5186        struct cvmx_pciercx_cfg466_s cn70xx;
5187        struct cvmx_pciercx_cfg466_s cn70xxp1;
5188        struct cvmx_pciercx_cfg466_s cn73xx;
5189        struct cvmx_pciercx_cfg466_s cn78xx;
5190        struct cvmx_pciercx_cfg466_s cn78xxp1;
5191        struct cvmx_pciercx_cfg466_s cnf71xx;
5192        struct cvmx_pciercx_cfg466_s cnf75xx;
5193};
5194
5195typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t;
5196
5197/**
5198 * cvmx_pcierc#_cfg467
5199 *
5200 * This register contains the four hundred sixty-eighth 32-bits of PCIe type 1 configuration space.
5201 *
5202 */
5203union cvmx_pciercx_cfg467 {
5204        u32 u32;
5205        struct cvmx_pciercx_cfg467_s {
5206                u32 reserved_24_31 : 8;
5207                u32 queue_mode : 3;
5208                u32 reserved_20_20 : 1;
5209                u32 header_credits : 8;
5210                u32 data_credits : 12;
5211        } s;
5212        struct cvmx_pciercx_cfg467_s cn52xx;
5213        struct cvmx_pciercx_cfg467_s cn52xxp1;
5214        struct cvmx_pciercx_cfg467_s cn56xx;
5215        struct cvmx_pciercx_cfg467_s cn56xxp1;
5216        struct cvmx_pciercx_cfg467_s cn61xx;
5217        struct cvmx_pciercx_cfg467_s cn63xx;
5218        struct cvmx_pciercx_cfg467_s cn63xxp1;
5219        struct cvmx_pciercx_cfg467_s cn66xx;
5220        struct cvmx_pciercx_cfg467_s cn68xx;
5221        struct cvmx_pciercx_cfg467_s cn68xxp1;
5222        struct cvmx_pciercx_cfg467_s cn70xx;
5223        struct cvmx_pciercx_cfg467_s cn70xxp1;
5224        struct cvmx_pciercx_cfg467_s cn73xx;
5225        struct cvmx_pciercx_cfg467_s cn78xx;
5226        struct cvmx_pciercx_cfg467_s cn78xxp1;
5227        struct cvmx_pciercx_cfg467_s cnf71xx;
5228        struct cvmx_pciercx_cfg467_s cnf75xx;
5229};
5230
5231typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t;
5232
5233/**
5234 * cvmx_pcierc#_cfg468
5235 *
5236 * This register contains the four hundred sixty-ninth 32-bits of PCIe type 1 configuration space.
5237 *
5238 */
5239union cvmx_pciercx_cfg468 {
5240        u32 u32;
5241        struct cvmx_pciercx_cfg468_s {
5242                u32 reserved_24_31 : 8;
5243                u32 queue_mode : 3;
5244                u32 reserved_20_20 : 1;
5245                u32 header_credits : 8;
5246                u32 data_credits : 12;
5247        } s;
5248        struct cvmx_pciercx_cfg468_s cn52xx;
5249        struct cvmx_pciercx_cfg468_s cn52xxp1;
5250        struct cvmx_pciercx_cfg468_s cn56xx;
5251        struct cvmx_pciercx_cfg468_s cn56xxp1;
5252        struct cvmx_pciercx_cfg468_s cn61xx;
5253        struct cvmx_pciercx_cfg468_s cn63xx;
5254        struct cvmx_pciercx_cfg468_s cn63xxp1;
5255        struct cvmx_pciercx_cfg468_s cn66xx;
5256        struct cvmx_pciercx_cfg468_s cn68xx;
5257        struct cvmx_pciercx_cfg468_s cn68xxp1;
5258        struct cvmx_pciercx_cfg468_s cn70xx;
5259        struct cvmx_pciercx_cfg468_s cn70xxp1;
5260        struct cvmx_pciercx_cfg468_s cn73xx;
5261        struct cvmx_pciercx_cfg468_s cn78xx;
5262        struct cvmx_pciercx_cfg468_s cn78xxp1;
5263        struct cvmx_pciercx_cfg468_s cnf71xx;
5264        struct cvmx_pciercx_cfg468_s cnf75xx;
5265};
5266
5267typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t;
5268
5269/**
5270 * cvmx_pcierc#_cfg490
5271 *
5272 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space
5273 * (VC0 Posted Buffer Depth)
5274 */
5275union cvmx_pciercx_cfg490 {
5276        u32 u32;
5277        struct cvmx_pciercx_cfg490_s {
5278                u32 reserved_26_31 : 6;
5279                u32 header_depth : 10;
5280                u32 reserved_14_15 : 2;
5281                u32 data_depth : 14;
5282        } s;
5283        struct cvmx_pciercx_cfg490_s cn52xx;
5284        struct cvmx_pciercx_cfg490_s cn52xxp1;
5285        struct cvmx_pciercx_cfg490_s cn56xx;
5286        struct cvmx_pciercx_cfg490_s cn56xxp1;
5287        struct cvmx_pciercx_cfg490_s cn61xx;
5288        struct cvmx_pciercx_cfg490_s cn63xx;
5289        struct cvmx_pciercx_cfg490_s cn63xxp1;
5290        struct cvmx_pciercx_cfg490_s cn66xx;
5291        struct cvmx_pciercx_cfg490_s cn68xx;
5292        struct cvmx_pciercx_cfg490_s cn68xxp1;
5293        struct cvmx_pciercx_cfg490_s cn70xx;
5294        struct cvmx_pciercx_cfg490_s cn70xxp1;
5295        struct cvmx_pciercx_cfg490_s cnf71xx;
5296};
5297
5298typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t;
5299
5300/**
5301 * cvmx_pcierc#_cfg491
5302 *
5303 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space
5304 * (VC0 Non-Posted Buffer Depth)
5305 */
5306union cvmx_pciercx_cfg491 {
5307        u32 u32;
5308        struct cvmx_pciercx_cfg491_s {
5309                u32 reserved_26_31 : 6;
5310                u32 header_depth : 10;
5311                u32 reserved_14_15 : 2;
5312                u32 data_depth : 14;
5313        } s;
5314        struct cvmx_pciercx_cfg491_s cn52xx;
5315        struct cvmx_pciercx_cfg491_s cn52xxp1;
5316        struct cvmx_pciercx_cfg491_s cn56xx;
5317        struct cvmx_pciercx_cfg491_s cn56xxp1;
5318        struct cvmx_pciercx_cfg491_s cn61xx;
5319        struct cvmx_pciercx_cfg491_s cn63xx;
5320        struct cvmx_pciercx_cfg491_s cn63xxp1;
5321        struct cvmx_pciercx_cfg491_s cn66xx;
5322        struct cvmx_pciercx_cfg491_s cn68xx;
5323        struct cvmx_pciercx_cfg491_s cn68xxp1;
5324        struct cvmx_pciercx_cfg491_s cn70xx;
5325        struct cvmx_pciercx_cfg491_s cn70xxp1;
5326        struct cvmx_pciercx_cfg491_s cnf71xx;
5327};
5328
5329typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t;
5330
5331/**
5332 * cvmx_pcierc#_cfg492
5333 *
5334 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space
5335 * (VC0 Completion Buffer Depth)
5336 */
5337union cvmx_pciercx_cfg492 {
5338        u32 u32;
5339        struct cvmx_pciercx_cfg492_s {
5340                u32 reserved_26_31 : 6;
5341                u32 header_depth : 10;
5342                u32 reserved_14_15 : 2;
5343                u32 data_depth : 14;
5344        } s;
5345        struct cvmx_pciercx_cfg492_s cn52xx;
5346        struct cvmx_pciercx_cfg492_s cn52xxp1;
5347        struct cvmx_pciercx_cfg492_s cn56xx;
5348        struct cvmx_pciercx_cfg492_s cn56xxp1;
5349        struct cvmx_pciercx_cfg492_s cn61xx;
5350        struct cvmx_pciercx_cfg492_s cn63xx;
5351        struct cvmx_pciercx_cfg492_s cn63xxp1;
5352        struct cvmx_pciercx_cfg492_s cn66xx;
5353        struct cvmx_pciercx_cfg492_s cn68xx;
5354        struct cvmx_pciercx_cfg492_s cn68xxp1;
5355        struct cvmx_pciercx_cfg492_s cn70xx;
5356        struct cvmx_pciercx_cfg492_s cn70xxp1;
5357        struct cvmx_pciercx_cfg492_s cnf71xx;
5358};
5359
5360typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t;
5361
5362/**
5363 * cvmx_pcierc#_cfg515
5364 *
5365 * This register contains the five hundred sixteenth 32-bits of PCIe type 1 configuration space.
5366 *
5367 */
5368union cvmx_pciercx_cfg515 {
5369        u32 u32;
5370        struct cvmx_pciercx_cfg515_s {
5371                u32 reserved_21_31 : 11;
5372                u32 s_d_e : 1;
5373                u32 ctcrb : 1;
5374                u32 cpyts : 1;
5375                u32 dsc : 1;
5376                u32 reserved_8_16 : 9;
5377                u32 n_fts : 8;
5378        } s;
5379        struct cvmx_pciercx_cfg515_cn61xx {
5380                u32 reserved_21_31 : 11;
5381                u32 s_d_e : 1;
5382                u32 ctcrb : 1;
5383                u32 cpyts : 1;
5384                u32 dsc : 1;
5385                u32 le : 9;
5386                u32 n_fts : 8;
5387        } cn61xx;
5388        struct cvmx_pciercx_cfg515_cn61xx cn63xx;
5389        struct cvmx_pciercx_cfg515_cn61xx cn63xxp1;
5390        struct cvmx_pciercx_cfg515_cn61xx cn66xx;
5391        struct cvmx_pciercx_cfg515_cn61xx cn68xx;
5392        struct cvmx_pciercx_cfg515_cn61xx cn68xxp1;
5393        struct cvmx_pciercx_cfg515_cn61xx cn70xx;
5394        struct cvmx_pciercx_cfg515_cn61xx cn70xxp1;
5395        struct cvmx_pciercx_cfg515_cn61xx cn73xx;
5396        struct cvmx_pciercx_cfg515_cn78xx {
5397                u32 reserved_21_31 : 11;
5398                u32 s_d_e : 1;
5399                u32 ctcrb : 1;
5400                u32 cpyts : 1;
5401                u32 dsc : 1;
5402                u32 alaneflip : 1;
5403                u32 pdetlane : 3;
5404                u32 nlanes : 5;
5405                u32 n_fts : 8;
5406        } cn78xx;
5407        struct cvmx_pciercx_cfg515_cn61xx cn78xxp1;
5408        struct cvmx_pciercx_cfg515_cn61xx cnf71xx;
5409        struct cvmx_pciercx_cfg515_cn78xx cnf75xx;
5410};
5411
5412typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t;
5413
5414/**
5415 * cvmx_pcierc#_cfg516
5416 *
5417 * This register contains the five hundred seventeenth 32-bits of PCIe type 1 configuration space.
5418 *
5419 */
5420union cvmx_pciercx_cfg516 {
5421        u32 u32;
5422        struct cvmx_pciercx_cfg516_s {
5423                u32 phy_stat : 32;
5424        } s;
5425        struct cvmx_pciercx_cfg516_s cn52xx;
5426        struct cvmx_pciercx_cfg516_s cn52xxp1;
5427        struct cvmx_pciercx_cfg516_s cn56xx;
5428        struct cvmx_pciercx_cfg516_s cn56xxp1;
5429        struct cvmx_pciercx_cfg516_s cn61xx;
5430        struct cvmx_pciercx_cfg516_s cn63xx;
5431        struct cvmx_pciercx_cfg516_s cn63xxp1;
5432        struct cvmx_pciercx_cfg516_s cn66xx;
5433        struct cvmx_pciercx_cfg516_s cn68xx;
5434        struct cvmx_pciercx_cfg516_s cn68xxp1;
5435        struct cvmx_pciercx_cfg516_s cn70xx;
5436        struct cvmx_pciercx_cfg516_s cn70xxp1;
5437        struct cvmx_pciercx_cfg516_s cn73xx;
5438        struct cvmx_pciercx_cfg516_s cn78xx;
5439        struct cvmx_pciercx_cfg516_s cn78xxp1;
5440        struct cvmx_pciercx_cfg516_s cnf71xx;
5441        struct cvmx_pciercx_cfg516_s cnf75xx;
5442};
5443
5444typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t;
5445
5446/**
5447 * cvmx_pcierc#_cfg517
5448 *
5449 * This register contains the five hundred eighteenth 32-bits of PCIe type 1 configuration space.
5450 *
5451 */
5452union cvmx_pciercx_cfg517 {
5453        u32 u32;
5454        struct cvmx_pciercx_cfg517_s {
5455                u32 phy_ctrl : 32;
5456        } s;
5457        struct cvmx_pciercx_cfg517_s cn52xx;
5458        struct cvmx_pciercx_cfg517_s cn52xxp1;
5459        struct cvmx_pciercx_cfg517_s cn56xx;
5460        struct cvmx_pciercx_cfg517_s cn56xxp1;
5461        struct cvmx_pciercx_cfg517_s cn61xx;
5462        struct cvmx_pciercx_cfg517_s cn63xx;
5463        struct cvmx_pciercx_cfg517_s cn63xxp1;
5464        struct cvmx_pciercx_cfg517_s cn66xx;
5465        struct cvmx_pciercx_cfg517_s cn68xx;
5466        struct cvmx_pciercx_cfg517_s cn68xxp1;
5467        struct cvmx_pciercx_cfg517_s cn70xx;
5468        struct cvmx_pciercx_cfg517_s cn70xxp1;
5469        struct cvmx_pciercx_cfg517_s cn73xx;
5470        struct cvmx_pciercx_cfg517_s cn78xx;
5471        struct cvmx_pciercx_cfg517_s cn78xxp1;
5472        struct cvmx_pciercx_cfg517_s cnf71xx;
5473        struct cvmx_pciercx_cfg517_s cnf75xx;
5474};
5475
5476typedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t;
5477
5478/**
5479 * cvmx_pcierc#_cfg548
5480 *
5481 * This register contains the five hundred forty-ninth 32-bits of type 0 PCIe configuration space.
5482 *
5483 */
5484union cvmx_pciercx_cfg548 {
5485        u32 u32;
5486        struct cvmx_pciercx_cfg548_s {
5487                u32 reserved_26_31 : 6;
5488                u32 rss : 2;
5489                u32 eiedd : 1;
5490                u32 reserved_19_22 : 4;
5491                u32 dcbd : 1;
5492                u32 dtdd : 1;
5493                u32 ed : 1;
5494                u32 reserved_13_15 : 3;
5495                u32 rxeq_ph01_en : 1;
5496                u32 erd : 1;
5497                u32 ecrd : 1;
5498                u32 ep2p3d : 1;
5499                u32 dsg3 : 1;
5500                u32 reserved_1_7 : 7;
5501                u32 grizdnc : 1;
5502        } s;
5503        struct cvmx_pciercx_cfg548_s cn73xx;
5504        struct cvmx_pciercx_cfg548_s cn78xx;
5505        struct cvmx_pciercx_cfg548_s cn78xxp1;
5506        struct cvmx_pciercx_cfg548_s cnf75xx;
5507};
5508
5509typedef union cvmx_pciercx_cfg548 cvmx_pciercx_cfg548_t;
5510
5511/**
5512 * cvmx_pcierc#_cfg554
5513 *
5514 * This register contains the five hundred fifty-fifth 32-bits of type 0 PCIe configuration space.
5515 *
5516 */
5517union cvmx_pciercx_cfg554 {
5518        u32 u32;
5519        struct cvmx_pciercx_cfg554_s {
5520                u32 reserved_27_31 : 5;
5521                u32 scefpm : 1;
5522                u32 reserved_25_25 : 1;
5523                u32 iif : 1;
5524                u32 prv : 16;
5525                u32 reserved_6_7 : 2;
5526                u32 p23td : 1;
5527                u32 bt : 1;
5528                u32 fm : 4;
5529        } s;
5530        struct cvmx_pciercx_cfg554_cn73xx {
5531                u32 reserved_25_31 : 7;
5532                u32 iif : 1;
5533                u32 prv : 16;
5534                u32 reserved_6_7 : 2;
5535                u32 p23td : 1;
5536                u32 bt : 1;
5537                u32 fm : 4;
5538        } cn73xx;
5539        struct cvmx_pciercx_cfg554_s cn78xx;
5540        struct cvmx_pciercx_cfg554_s cn78xxp1;
5541        struct cvmx_pciercx_cfg554_s cnf75xx;
5542};
5543
5544typedef union cvmx_pciercx_cfg554 cvmx_pciercx_cfg554_t;
5545
5546/**
5547 * cvmx_pcierc#_cfg558
5548 *
5549 * This register contains the five hundred fifty-ninth 32-bits of type 0 PCIe configuration space.
5550 *
5551 */
5552union cvmx_pciercx_cfg558 {
5553        u32 u32;
5554        struct cvmx_pciercx_cfg558_s {
5555                u32 ple : 1;
5556                u32 rxstatus : 31;
5557        } s;
5558        struct cvmx_pciercx_cfg558_s cn73xx;
5559        struct cvmx_pciercx_cfg558_s cn78xx;
5560        struct cvmx_pciercx_cfg558_s cn78xxp1;
5561        struct cvmx_pciercx_cfg558_s cnf75xx;
5562};
5563
5564typedef union cvmx_pciercx_cfg558 cvmx_pciercx_cfg558_t;
5565
5566/**
5567 * cvmx_pcierc#_cfg559
5568 *
5569 * This register contains the five hundred sixtieth 32-bits of PCIe type 0 configuration space.
5570 *
5571 */
5572union cvmx_pciercx_cfg559 {
5573        u32 u32;
5574        struct cvmx_pciercx_cfg559_s {
5575                u32 reserved_1_31 : 31;
5576                u32 dbi_ro_wr_en : 1;
5577        } s;
5578        struct cvmx_pciercx_cfg559_s cn73xx;
5579        struct cvmx_pciercx_cfg559_s cn78xx;
5580        struct cvmx_pciercx_cfg559_s cn78xxp1;
5581        struct cvmx_pciercx_cfg559_s cnf75xx;
5582};
5583
5584typedef union cvmx_pciercx_cfg559 cvmx_pciercx_cfg559_t;
5585
5586#endif
5587