/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Configuration and status register (CSR) type definitions for
 * Octeon pko.
 */

#ifndef __CVMX_PKO_DEFS_H__
#define __CVMX_PKO_DEFS_H__

#define CVMX_PKO_CHANNEL_LEVEL                  (0x00015400000800F0ull)
#define CVMX_PKO_DPFI_ENA                       (0x0001540000C00018ull)
#define CVMX_PKO_DPFI_FLUSH                     (0x0001540000C00008ull)
#define CVMX_PKO_DPFI_FPA_AURA                  (0x0001540000C00010ull)
#define CVMX_PKO_DPFI_STATUS                    (0x0001540000C00000ull)
#define CVMX_PKO_DQX_BYTES(offset)              (0x00015400000000D8ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_CIR(offset)                (0x0001540000280018ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_DROPPED_BYTES(offset)      (0x00015400000000C8ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_DROPPED_PACKETS(offset)    (0x00015400000000C0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_FIFO(offset)               (0x0001540000300078ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_PACKETS(offset)            (0x00015400000000D0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_PICK(offset)               (0x0001540000300070ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_PIR(offset)                (0x0001540000280020ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_POINTERS(offset)           (0x0001540000280078ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_SCHEDULE(offset)           (0x0001540000280008ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_SCHED_STATE(offset)        (0x0001540000280028ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_SHAPE(offset)              (0x0001540000280010ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_SHAPE_STATE(offset)        (0x0001540000280030ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_SW_XOFF(offset)            (0x00015400002800E0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_TOPOLOGY(offset)           (0x0001540000300000ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_BUF_CNT(offset)         (0x00015400008000E8ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_BUF_CTL(offset)         (0x00015400008000F0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_BUF_CTL_W1C(offset)     (0x00015400008000F8ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_CNT(offset)             (0x0001540000000050ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_CTL(offset)             (0x0001540000000040ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQX_WM_CTL_W1C(offset)         (0x0001540000000048ull + ((offset) & 1023) * 512)
#define CVMX_PKO_DQ_CSR_BUS_DEBUG               (0x00015400003001F8ull)
#define CVMX_PKO_DQ_DEBUG                       (0x0001540000300128ull)
#define CVMX_PKO_DRAIN_IRQ                      (0x0001540000000140ull)
#define CVMX_PKO_ENABLE                         (0x0001540000D00008ull)
#define CVMX_PKO_FORMATX_CTL(offset)            (0x0001540000900800ull + ((offset) & 127) * 8)
#define CVMX_PKO_L1_SQA_DEBUG                   (0x0001540000080128ull)
#define CVMX_PKO_L1_SQB_DEBUG                   (0x0001540000080130ull)
#define CVMX_PKO_L1_SQX_CIR(offset)             (0x0001540000000018ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_DROPPED_BYTES(offset)   (0x0001540000000088ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_DROPPED_PACKETS(offset) (0x0001540000000080ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_GREEN(offset)           (0x0001540000080058ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_GREEN_BYTES(offset)     (0x00015400000000B8ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_GREEN_PACKETS(offset)   (0x00015400000000B0ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_LINK(offset)            (0x0001540000000038ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_PICK(offset)            (0x0001540000080070ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_RED(offset)             (0x0001540000080068ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_RED_BYTES(offset)       (0x0001540000000098ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_RED_PACKETS(offset)     (0x0001540000000090ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_SCHEDULE(offset)        (0x0001540000000008ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_SHAPE(offset)           (0x0001540000000010ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_SHAPE_STATE(offset)     (0x0001540000000030ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_SW_XOFF(offset)         (0x00015400000000E0ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_TOPOLOGY(offset)        (0x0001540000080000ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_YELLOW(offset)          (0x0001540000080060ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_YELLOW_BYTES(offset)    (0x00015400000000A8ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQX_YELLOW_PACKETS(offset)  (0x00015400000000A0ull + ((offset) & 31) * 512)
#define CVMX_PKO_L1_SQ_CSR_BUS_DEBUG            (0x00015400000801F8ull)
#define CVMX_PKO_L2_SQA_DEBUG                   (0x0001540000100128ull)
#define CVMX_PKO_L2_SQB_DEBUG                   (0x0001540000100130ull)
#define CVMX_PKO_L2_SQX_CIR(offset)             (0x0001540000080018ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_GREEN(offset)           (0x0001540000100058ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_PICK(offset)            (0x0001540000100070ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_PIR(offset)             (0x0001540000080020ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_POINTERS(offset)        (0x0001540000080078ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_RED(offset)             (0x0001540000100068ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_SCHEDULE(offset)        (0x0001540000080008ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_SCHED_STATE(offset)     (0x0001540000080028ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_SHAPE(offset)           (0x0001540000080010ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_SHAPE_STATE(offset)     (0x0001540000080030ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_SW_XOFF(offset)         (0x00015400000800E0ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_TOPOLOGY(offset)        (0x0001540000100000ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQX_YELLOW(offset)          (0x0001540000100060ull + ((offset) & 511) * 512)
#define CVMX_PKO_L2_SQ_CSR_BUS_DEBUG            (0x00015400001001F8ull)
#define CVMX_PKO_L3_L2_SQX_CHANNEL(offset)      (0x0001540000080038ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQA_DEBUG                   (0x0001540000180128ull)
#define CVMX_PKO_L3_SQB_DEBUG                   (0x0001540000180130ull)
#define CVMX_PKO_L3_SQX_CIR(offset)             (0x0001540000100018ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_GREEN(offset)           (0x0001540000180058ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_PICK(offset)            (0x0001540000180070ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_PIR(offset)             (0x0001540000100020ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_POINTERS(offset)        (0x0001540000100078ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_RED(offset)             (0x0001540000180068ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_SCHEDULE(offset)        (0x0001540000100008ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_SCHED_STATE(offset)     (0x0001540000100028ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_SHAPE(offset)           (0x0001540000100010ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_SHAPE_STATE(offset)     (0x0001540000100030ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_SW_XOFF(offset)         (0x00015400001000E0ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_TOPOLOGY(offset)        (0x0001540000180000ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQX_YELLOW(offset)          (0x0001540000180060ull + ((offset) & 511) * 512)
#define CVMX_PKO_L3_SQ_CSR_BUS_DEBUG            (0x00015400001801F8ull)
#define CVMX_PKO_L4_SQA_DEBUG                   (0x0001540000200128ull)
#define CVMX_PKO_L4_SQB_DEBUG                   (0x0001540000200130ull)
#define CVMX_PKO_L4_SQX_CIR(offset)             (0x0001540000180018ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_GREEN(offset)           (0x0001540000200058ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_PICK(offset)            (0x0001540000200070ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_PIR(offset)             (0x0001540000180020ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_POINTERS(offset)        (0x0001540000180078ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_RED(offset)             (0x0001540000200068ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_SCHEDULE(offset)        (0x0001540000180008ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_SCHED_STATE(offset)     (0x0001540000180028ull + ((offset) & 511) * 512)
#define CVMX_PKO_L4_SQX_SHAPE(offset)           (0x0001540000180010ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_SHAPE_STATE(offset)     (0x0001540000180030ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_SW_XOFF(offset)         (0x00015400001800E0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_TOPOLOGY(offset)        (0x0001540000200000ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQX_YELLOW(offset)          (0x0001540000200060ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L4_SQ_CSR_BUS_DEBUG            (0x00015400002001F8ull)
#define CVMX_PKO_L5_SQA_DEBUG                   (0x0001540000280128ull)
#define CVMX_PKO_L5_SQB_DEBUG                   (0x0001540000280130ull)
#define CVMX_PKO_L5_SQX_CIR(offset)             (0x0001540000200018ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_GREEN(offset)           (0x0001540000280058ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_PICK(offset)            (0x0001540000280070ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_PIR(offset)             (0x0001540000200020ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_POINTERS(offset)        (0x0001540000200078ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_RED(offset)             (0x0001540000280068ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_SCHEDULE(offset)        (0x0001540000200008ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_SCHED_STATE(offset)     (0x0001540000200028ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_SHAPE(offset)           (0x0001540000200010ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_SHAPE_STATE(offset)     (0x0001540000200030ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_SW_XOFF(offset)         (0x00015400002000E0ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_TOPOLOGY(offset)        (0x0001540000280000ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQX_YELLOW(offset)          (0x0001540000280060ull + ((offset) & 1023) * 512)
#define CVMX_PKO_L5_SQ_CSR_BUS_DEBUG            (0x00015400002801F8ull)
#define CVMX_PKO_LUTX(offset)                   (0x0001540000B00000ull + ((offset) & 1023) * 8)
#define CVMX_PKO_LUT_BIST_STATUS                (0x0001540000B02018ull)
#define CVMX_PKO_LUT_ECC_CTL0                   (0x0001540000BFFFD0ull)
#define CVMX_PKO_LUT_ECC_DBE_STS0               (0x0001540000BFFFF0ull)
#define CVMX_PKO_LUT_ECC_DBE_STS_CMB0           (0x0001540000BFFFD8ull)
#define CVMX_PKO_LUT_ECC_SBE_STS0               (0x0001540000BFFFF8ull)
#define CVMX_PKO_LUT_ECC_SBE_STS_CMB0           (0x0001540000BFFFE8ull)
#define CVMX_PKO_MACX_CFG(offset)               (0x0001540000900000ull + ((offset) & 31) * 8)
#define CVMX_PKO_MCI0_CRED_CNTX(offset)         (0x0001540000A40000ull + ((offset) & 31) * 8)
#define CVMX_PKO_MCI0_MAX_CREDX(offset)         (0x0001540000A00000ull + ((offset) & 31) * 8)
#define CVMX_PKO_MCI1_CRED_CNTX(offset)         (0x0001540000A80100ull + ((offset) & 31) * 8)
#define CVMX_PKO_MCI1_MAX_CREDX(offset)         (0x0001540000A80000ull + ((offset) & 31) * 8)
#define CVMX_PKO_MEM_COUNT0                     (0x0001180050001080ull)
#define CVMX_PKO_MEM_COUNT1                     (0x0001180050001088ull)
#define CVMX_PKO_MEM_DEBUG0                     (0x0001180050001100ull)
#define CVMX_PKO_MEM_DEBUG1                     (0x0001180050001108ull)
#define CVMX_PKO_MEM_DEBUG10                    (0x0001180050001150ull)
#define CVMX_PKO_MEM_DEBUG11                    (0x0001180050001158ull)
#define CVMX_PKO_MEM_DEBUG12                    (0x0001180050001160ull)
#define CVMX_PKO_MEM_DEBUG13                    (0x0001180050001168ull)
#define CVMX_PKO_MEM_DEBUG14                    (0x0001180050001170ull)
#define CVMX_PKO_MEM_DEBUG2                     (0x0001180050001110ull)
#define CVMX_PKO_MEM_DEBUG3                     (0x0001180050001118ull)
#define CVMX_PKO_MEM_DEBUG4                     (0x0001180050001120ull)
#define CVMX_PKO_MEM_DEBUG5                     (0x0001180050001128ull)
#define CVMX_PKO_MEM_DEBUG6                     (0x0001180050001130ull)
#define CVMX_PKO_MEM_DEBUG7                     (0x0001180050001138ull)
#define CVMX_PKO_MEM_DEBUG8                     (0x0001180050001140ull)
#define CVMX_PKO_MEM_DEBUG9                     (0x0001180050001148ull)
#define CVMX_PKO_MEM_IPORT_PTRS                 (0x0001180050001030ull)
#define CVMX_PKO_MEM_IPORT_QOS                  (0x0001180050001038ull)
#define CVMX_PKO_MEM_IQUEUE_PTRS                (0x0001180050001040ull)
#define CVMX_PKO_MEM_IQUEUE_QOS                 (0x0001180050001048ull)
#define CVMX_PKO_MEM_PORT_PTRS                  (0x0001180050001010ull)
#define CVMX_PKO_MEM_PORT_QOS                   (0x0001180050001018ull)
#define CVMX_PKO_MEM_PORT_RATE0                 (0x0001180050001020ull)
#define CVMX_PKO_MEM_PORT_RATE1                 (0x0001180050001028ull)
#define CVMX_PKO_MEM_QUEUE_PTRS                 (0x0001180050001000ull)
#define CVMX_PKO_MEM_QUEUE_QOS                  (0x0001180050001008ull)
#define CVMX_PKO_MEM_THROTTLE_INT               (0x0001180050001058ull)
#define CVMX_PKO_MEM_THROTTLE_PIPE              (0x0001180050001050ull)
#define CVMX_PKO_NCB_BIST_STATUS                (0x0001540000EFFF00ull)
#define CVMX_PKO_NCB_ECC_CTL0                   (0x0001540000EFFFD0ull)
#define CVMX_PKO_NCB_ECC_DBE_STS0               (0x0001540000EFFFF0ull)
#define CVMX_PKO_NCB_ECC_DBE_STS_CMB0           (0x0001540000EFFFD8ull)
#define CVMX_PKO_NCB_ECC_SBE_STS0               (0x0001540000EFFFF8ull)
#define CVMX_PKO_NCB_ECC_SBE_STS_CMB0           (0x0001540000EFFFE8ull)
#define CVMX_PKO_NCB_INT                        (0x0001540000E00010ull)
#define CVMX_PKO_NCB_TX_ERR_INFO                (0x0001540000E00008ull)
#define CVMX_PKO_NCB_TX_ERR_WORD                (0x0001540000E00000ull)
#define CVMX_PKO_PDM_BIST_STATUS                (0x00015400008FFF00ull)
#define CVMX_PKO_PDM_CFG                        (0x0001540000800000ull)
#define CVMX_PKO_PDM_CFG_DBG                    (0x0001540000800FF8ull)
#define CVMX_PKO_PDM_CP_DBG                     (0x0001540000800190ull)
#define CVMX_PKO_PDM_DQX_MINPAD(offset)         (0x00015400008F0000ull + ((offset) & 1023) * 8)
#define CVMX_PKO_PDM_DRPBUF_DBG                 (0x00015400008000B0ull)
#define CVMX_PKO_PDM_DWPBUF_DBG                 (0x00015400008000A8ull)
#define CVMX_PKO_PDM_ECC_CTL0                   (0x00015400008FFFD0ull)
#define CVMX_PKO_PDM_ECC_CTL1                   (0x00015400008FFFD8ull)
#define CVMX_PKO_PDM_ECC_DBE_STS0               (0x00015400008FFFF0ull)
#define CVMX_PKO_PDM_ECC_DBE_STS_CMB0           (0x00015400008FFFE0ull)
#define CVMX_PKO_PDM_ECC_SBE_STS0               (0x00015400008FFFF8ull)
#define CVMX_PKO_PDM_ECC_SBE_STS_CMB0           (0x00015400008FFFE8ull)
#define CVMX_PKO_PDM_FILLB_DBG0                 (0x00015400008002A0ull)
#define CVMX_PKO_PDM_FILLB_DBG1                 (0x00015400008002A8ull)
#define CVMX_PKO_PDM_FILLB_DBG2                 (0x00015400008002B0ull)
#define CVMX_PKO_PDM_FLSHB_DBG0                 (0x00015400008002B8ull)
#define CVMX_PKO_PDM_FLSHB_DBG1                 (0x00015400008002C0ull)
#define CVMX_PKO_PDM_INTF_DBG_RD                (0x0001540000900F20ull)
#define CVMX_PKO_PDM_ISRD_DBG                   (0x0001540000800090ull)
#define CVMX_PKO_PDM_ISRD_DBG_DQ                (0x0001540000800290ull)
#define CVMX_PKO_PDM_ISRM_DBG                   (0x0001540000800098ull)
#define CVMX_PKO_PDM_ISRM_DBG_DQ                (0x0001540000800298ull)
#define CVMX_PKO_PDM_MEM_ADDR                   (0x0001540000800018ull)
#define CVMX_PKO_PDM_MEM_DATA                   (0x0001540000800010ull)
#define CVMX_PKO_PDM_MEM_RW_CTL                 (0x0001540000800020ull)
#define CVMX_PKO_PDM_MEM_RW_STS                 (0x0001540000800028ull)
#define CVMX_PKO_PDM_MWPBUF_DBG                 (0x00015400008000A0ull)
#define CVMX_PKO_PDM_STS                        (0x0001540000800008ull)
#define CVMX_PKO_PEB_BIST_STATUS                (0x0001540000900D00ull)
#define CVMX_PKO_PEB_ECC_CTL0                   (0x00015400009FFFD0ull)
#define CVMX_PKO_PEB_ECC_CTL1                   (0x00015400009FFFA8ull)
#define CVMX_PKO_PEB_ECC_DBE_STS0               (0x00015400009FFFF0ull)
#define CVMX_PKO_PEB_ECC_DBE_STS_CMB0           (0x00015400009FFFD8ull)
#define CVMX_PKO_PEB_ECC_SBE_STS0               (0x00015400009FFFF8ull)
#define CVMX_PKO_PEB_ECC_SBE_STS_CMB0           (0x00015400009FFFE8ull)
#define CVMX_PKO_PEB_ECO                        (0x0001540000901000ull)
#define CVMX_PKO_PEB_ERR_INT                    (0x0001540000900C00ull)
#define CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO       (0x0001540000900C08ull)
#define CVMX_PKO_PEB_FCS_SOP_ERR_INFO           (0x0001540000900C18ull)
#define CVMX_PKO_PEB_JUMP_DEF_ERR_INFO          (0x0001540000900C10ull)
#define CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO       (0x0001540000900C50ull)
#define CVMX_PKO_PEB_MAX_LINK_ERR_INFO          (0x0001540000900C48ull)
#define CVMX_PKO_PEB_NCB_CFG                    (0x0001540000900308ull)
#define CVMX_PKO_PEB_PAD_ERR_INFO               (0x0001540000900C28ull)
#define CVMX_PKO_PEB_PSE_FIFO_ERR_INFO          (0x0001540000900C20ull)
#define CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO         (0x0001540000900C38ull)
#define CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO         (0x0001540000900C40ull)
#define CVMX_PKO_PEB_TRUNC_ERR_INFO             (0x0001540000900C30ull)
#define CVMX_PKO_PEB_TSO_CFG                    (0x0001540000900310ull)
#define CVMX_PKO_PQA_DEBUG                      (0x0001540000000128ull)
#define CVMX_PKO_PQB_DEBUG                      (0x0001540000000130ull)
#define CVMX_PKO_PQ_CSR_BUS_DEBUG               (0x00015400000001F8ull)
#define CVMX_PKO_PQ_DEBUG_GREEN                 (0x0001540000000058ull)
#define CVMX_PKO_PQ_DEBUG_LINKS                 (0x0001540000000068ull)
#define CVMX_PKO_PQ_DEBUG_YELLOW                (0x0001540000000060ull)
#define CVMX_PKO_PSE_DQ_BIST_STATUS             (0x0001540000300138ull)
#define CVMX_PKO_PSE_DQ_ECC_CTL0                (0x0001540000300100ull)
#define CVMX_PKO_PSE_DQ_ECC_DBE_STS0            (0x0001540000300118ull)
#define CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0        (0x0001540000300120ull)
#define CVMX_PKO_PSE_DQ_ECC_SBE_STS0            (0x0001540000300108ull)
#define CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0        (0x0001540000300110ull)
#define CVMX_PKO_PSE_PQ_BIST_STATUS             (0x0001540000000138ull)
#define CVMX_PKO_PSE_PQ_ECC_CTL0                (0x0001540000000100ull)
#define CVMX_PKO_PSE_PQ_ECC_DBE_STS0            (0x0001540000000118ull)
#define CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0        (0x0001540000000120ull)
#define CVMX_PKO_PSE_PQ_ECC_SBE_STS0            (0x0001540000000108ull)
#define CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0        (0x0001540000000110ull)
#define CVMX_PKO_PSE_SQ1_BIST_STATUS            (0x0001540000080138ull)
#define CVMX_PKO_PSE_SQ1_ECC_CTL0               (0x0001540000080100ull)
#define CVMX_PKO_PSE_SQ1_ECC_DBE_STS0           (0x0001540000080118ull)
#define CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0       (0x0001540000080120ull)
#define CVMX_PKO_PSE_SQ1_ECC_SBE_STS0           (0x0001540000080108ull)
#define CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0       (0x0001540000080110ull)
#define CVMX_PKO_PSE_SQ2_BIST_STATUS            (0x0001540000100138ull)
#define CVMX_PKO_PSE_SQ2_ECC_CTL0               (0x0001540000100100ull)
#define CVMX_PKO_PSE_SQ2_ECC_DBE_STS0           (0x0001540000100118ull)
#define CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0       (0x0001540000100120ull)
#define CVMX_PKO_PSE_SQ2_ECC_SBE_STS0           (0x0001540000100108ull)
#define CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0       (0x0001540000100110ull)
#define CVMX_PKO_PSE_SQ3_BIST_STATUS            (0x0001540000180138ull)
#define CVMX_PKO_PSE_SQ3_ECC_CTL0               (0x0001540000180100ull)
#define CVMX_PKO_PSE_SQ3_ECC_DBE_STS0           (0x0001540000180118ull)
#define CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0       (0x0001540000180120ull)
#define CVMX_PKO_PSE_SQ3_ECC_SBE_STS0           (0x0001540000180108ull)
#define CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0       (0x0001540000180110ull)
#define CVMX_PKO_PSE_SQ4_BIST_STATUS            (0x0001540000200138ull)
#define CVMX_PKO_PSE_SQ4_ECC_CTL0               (0x0001540000200100ull)
#define CVMX_PKO_PSE_SQ4_ECC_DBE_STS0           (0x0001540000200118ull)
#define CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0       (0x0001540000200120ull)
#define CVMX_PKO_PSE_SQ4_ECC_SBE_STS0           (0x0001540000200108ull)
#define CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0       (0x0001540000200110ull)
#define CVMX_PKO_PSE_SQ5_BIST_STATUS            (0x0001540000280138ull)
#define CVMX_PKO_PSE_SQ5_ECC_CTL0               (0x0001540000280100ull)
#define CVMX_PKO_PSE_SQ5_ECC_DBE_STS0           (0x0001540000280118ull)
#define CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0       (0x0001540000280120ull)
#define CVMX_PKO_PSE_SQ5_ECC_SBE_STS0           (0x0001540000280108ull)
#define CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0       (0x0001540000280110ull)
#define CVMX_PKO_PTFX_STATUS(offset)            (0x0001540000900100ull + ((offset) & 31) * 8)
#define CVMX_PKO_PTF_IOBP_CFG                   (0x0001540000900300ull)
#define CVMX_PKO_PTGFX_CFG(offset)              (0x0001540000900200ull + ((offset) & 7) * 8)
#define CVMX_PKO_REG_BIST_RESULT                (0x0001180050000080ull)
#define CVMX_PKO_REG_CMD_BUF                    (0x0001180050000010ull)
#define CVMX_PKO_REG_CRC_CTLX(offset)           (0x0001180050000028ull + ((offset) & 1) * 8)
#define CVMX_PKO_REG_CRC_ENABLE                 (0x0001180050000020ull)
#define CVMX_PKO_REG_CRC_IVX(offset)            (0x0001180050000038ull + ((offset) & 1) * 8)
#define CVMX_PKO_REG_DEBUG0                     (0x0001180050000098ull)
#define CVMX_PKO_REG_DEBUG1                     (0x00011800500000A0ull)
#define CVMX_PKO_REG_DEBUG2                     (0x00011800500000A8ull)
#define CVMX_PKO_REG_DEBUG3                     (0x00011800500000B0ull)
#define CVMX_PKO_REG_DEBUG4                     (0x00011800500000B8ull)
#define CVMX_PKO_REG_ENGINE_INFLIGHT            (0x0001180050000050ull)
#define CVMX_PKO_REG_ENGINE_INFLIGHT1           (0x0001180050000318ull)
#define CVMX_PKO_REG_ENGINE_STORAGEX(offset)    (0x0001180050000300ull + ((offset) & 1) * 8)
#define CVMX_PKO_REG_ENGINE_THRESH              (0x0001180050000058ull)
#define CVMX_PKO_REG_ERROR                      (0x0001180050000088ull)
#define CVMX_PKO_REG_FLAGS                      (0x0001180050000000ull)
#define CVMX_PKO_REG_GMX_PORT_MODE              (0x0001180050000018ull)
#define CVMX_PKO_REG_INT_MASK                   (0x0001180050000090ull)
#define CVMX_PKO_REG_LOOPBACK_BPID              (0x0001180050000118ull)
#define CVMX_PKO_REG_LOOPBACK_PKIND             (0x0001180050000068ull)
#define CVMX_PKO_REG_MIN_PKT                    (0x0001180050000070ull)
#define CVMX_PKO_REG_PREEMPT                    (0x0001180050000110ull)
#define CVMX_PKO_REG_QUEUE_MODE                 (0x0001180050000048ull)
#define CVMX_PKO_REG_QUEUE_PREEMPT              (0x0001180050000108ull)
#define CVMX_PKO_REG_QUEUE_PTRS1                (0x0001180050000100ull)
#define CVMX_PKO_REG_READ_IDX                   (0x0001180050000008ull)
#define CVMX_PKO_REG_THROTTLE                   (0x0001180050000078ull)
#define CVMX_PKO_REG_TIMESTAMP                  (0x0001180050000060ull)
#define CVMX_PKO_SHAPER_CFG                     (0x00015400000800F8ull)
#define CVMX_PKO_STATE_UID_IN_USEX_RD(offset)   (0x0001540000900F00ull + ((offset) & 3) * 8)
#define CVMX_PKO_STATUS                         (0x0001540000D00000ull)
#define CVMX_PKO_TXFX_PKT_CNT_RD(offset)        (0x0001540000900E00ull + ((offset) & 31) * 8)

/**
 * cvmx_pko_channel_level
 */
union cvmx_pko_channel_level {
        u64 u64;
        struct cvmx_pko_channel_level_s {
                u64 reserved_1_63 : 63;
                u64 cc_level : 1;
        } s;
        struct cvmx_pko_channel_level_s cn73xx;
        struct cvmx_pko_channel_level_s cn78xx;
        struct cvmx_pko_channel_level_s cn78xxp1;
        struct cvmx_pko_channel_level_s cnf75xx;
};

typedef union cvmx_pko_channel_level cvmx_pko_channel_level_t;

/**
 * cvmx_pko_dpfi_ena
 */
union cvmx_pko_dpfi_ena {
        u64 u64;
        struct cvmx_pko_dpfi_ena_s {
                u64 reserved_1_63 : 63;
                u64 enable : 1;
        } s;
        struct cvmx_pko_dpfi_ena_s cn73xx;
        struct cvmx_pko_dpfi_ena_s cn78xx;
        struct cvmx_pko_dpfi_ena_s cn78xxp1;
        struct cvmx_pko_dpfi_ena_s cnf75xx;
};

typedef union cvmx_pko_dpfi_ena cvmx_pko_dpfi_ena_t;

/**
 * cvmx_pko_dpfi_flush
 */
union cvmx_pko_dpfi_flush {
        u64 u64;
        struct cvmx_pko_dpfi_flush_s {
                u64 reserved_1_63 : 63;
                u64 flush_en : 1;
        } s;
        struct cvmx_pko_dpfi_flush_s cn73xx;
        struct cvmx_pko_dpfi_flush_s cn78xx;
        struct cvmx_pko_dpfi_flush_s cn78xxp1;
        struct cvmx_pko_dpfi_flush_s cnf75xx;
};

typedef union cvmx_pko_dpfi_flush cvmx_pko_dpfi_flush_t;

/**
 * cvmx_pko_dpfi_fpa_aura
 */
union cvmx_pko_dpfi_fpa_aura {
        u64 u64;
        struct cvmx_pko_dpfi_fpa_aura_s {
                u64 reserved_12_63 : 52;
                u64 node : 2;
                u64 laura : 10;
        } s;
        struct cvmx_pko_dpfi_fpa_aura_s cn73xx;
        struct cvmx_pko_dpfi_fpa_aura_s cn78xx;
        struct cvmx_pko_dpfi_fpa_aura_s cn78xxp1;
        struct cvmx_pko_dpfi_fpa_aura_s cnf75xx;
};

typedef union cvmx_pko_dpfi_fpa_aura cvmx_pko_dpfi_fpa_aura_t;

/**
 * cvmx_pko_dpfi_status
 */
union cvmx_pko_dpfi_status {
        u64 u64;
        struct cvmx_pko_dpfi_status_s {
                u64 ptr_cnt : 32;
                u64 reserved_27_31 : 5;
                u64 xpd_fif_cnt : 4;
                u64 dalc_fif_cnt : 4;
                u64 alc_fif_cnt : 5;
                u64 reserved_13_13 : 1;
                u64 isrd_ptr1_rtn_full : 1;
                u64 isrd_ptr0_rtn_full : 1;
                u64 isrm_ptr1_rtn_full : 1;
                u64 isrm_ptr0_rtn_full : 1;
                u64 isrd_ptr1_val : 1;
                u64 isrd_ptr0_val : 1;
                u64 isrm_ptr1_val : 1;
                u64 isrm_ptr0_val : 1;
                u64 ptr_req_pend : 1;
                u64 ptr_rtn_pend : 1;
                u64 fpa_empty : 1;
                u64 dpfi_empty : 1;
                u64 cache_flushed : 1;
        } s;
        struct cvmx_pko_dpfi_status_s cn73xx;
        struct cvmx_pko_dpfi_status_s cn78xx;
        struct cvmx_pko_dpfi_status_cn78xxp1 {
                u64 ptr_cnt : 32;
                u64 reserved_13_31 : 19;
                u64 isrd_ptr1_rtn_full : 1;
                u64 isrd_ptr0_rtn_full : 1;
                u64 isrm_ptr1_rtn_full : 1;
                u64 isrm_ptr0_rtn_full : 1;
                u64 isrd_ptr1_val : 1;
                u64 isrd_ptr0_val : 1;
                u64 isrm_ptr1_val : 1;
                u64 isrm_ptr0_val : 1;
                u64 ptr_req_pend : 1;
                u64 ptr_rtn_pend : 1;
                u64 fpa_empty : 1;
                u64 dpfi_empty : 1;
                u64 cache_flushed : 1;
        } cn78xxp1;
        struct cvmx_pko_dpfi_status_s cnf75xx;
};

typedef union cvmx_pko_dpfi_status cvmx_pko_dpfi_status_t;

/**
 * cvmx_pko_dq#_bytes
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES.
 *
 */
union cvmx_pko_dqx_bytes {
        u64 u64;
        struct cvmx_pko_dqx_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_dqx_bytes_s cn73xx;
        struct cvmx_pko_dqx_bytes_s cn78xx;
        struct cvmx_pko_dqx_bytes_s cn78xxp1;
        struct cvmx_pko_dqx_bytes_s cnf75xx;
};

typedef union cvmx_pko_dqx_bytes cvmx_pko_dqx_bytes_t;

/**
 * cvmx_pko_dq#_cir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_dqx_cir {
        u64 u64;
        struct cvmx_pko_dqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_dqx_cir_s cn73xx;
        struct cvmx_pko_dqx_cir_s cn78xx;
        struct cvmx_pko_dqx_cir_s cn78xxp1;
        struct cvmx_pko_dqx_cir_s cnf75xx;
};

typedef union cvmx_pko_dqx_cir cvmx_pko_dqx_cir_t;

/**
 * cvmx_pko_dq#_dropped_bytes
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES.
 *
 */
union cvmx_pko_dqx_dropped_bytes {
        u64 u64;
        struct cvmx_pko_dqx_dropped_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_dqx_dropped_bytes_s cn73xx;
        struct cvmx_pko_dqx_dropped_bytes_s cn78xx;
        struct cvmx_pko_dqx_dropped_bytes_s cn78xxp1;
        struct cvmx_pko_dqx_dropped_bytes_s cnf75xx;
};

typedef union cvmx_pko_dqx_dropped_bytes cvmx_pko_dqx_dropped_bytes_t;

/**
 * cvmx_pko_dq#_dropped_packets
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS.
 *
 */
union cvmx_pko_dqx_dropped_packets {
        u64 u64;
        struct cvmx_pko_dqx_dropped_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_dqx_dropped_packets_s cn73xx;
        struct cvmx_pko_dqx_dropped_packets_s cn78xx;
        struct cvmx_pko_dqx_dropped_packets_s cn78xxp1;
        struct cvmx_pko_dqx_dropped_packets_s cnf75xx;
};

typedef union cvmx_pko_dqx_dropped_packets cvmx_pko_dqx_dropped_packets_t;

/**
 * cvmx_pko_dq#_fifo
 */
union cvmx_pko_dqx_fifo {
        u64 u64;
        struct cvmx_pko_dqx_fifo_s {
                u64 reserved_15_63 : 49;
                u64 p_con : 1;
                u64 head : 7;
                u64 tail : 7;
        } s;
        struct cvmx_pko_dqx_fifo_s cn73xx;
        struct cvmx_pko_dqx_fifo_s cn78xx;
        struct cvmx_pko_dqx_fifo_s cn78xxp1;
        struct cvmx_pko_dqx_fifo_s cnf75xx;
};

typedef union cvmx_pko_dqx_fifo cvmx_pko_dqx_fifo_t;

/**
 * cvmx_pko_dq#_packets
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS.
 *
 */
union cvmx_pko_dqx_packets {
        u64 u64;
        struct cvmx_pko_dqx_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_dqx_packets_s cn73xx;
        struct cvmx_pko_dqx_packets_s cn78xx;
        struct cvmx_pko_dqx_packets_s cn78xxp1;
        struct cvmx_pko_dqx_packets_s cnf75xx;
};

typedef union cvmx_pko_dqx_packets cvmx_pko_dqx_packets_t;

/**
 * cvmx_pko_dq#_pick
 *
 * This CSR contains the meta for the DQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_dqx_pick {
        u64 u64;
        struct cvmx_pko_dqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_dqx_pick_s cn73xx;
        struct cvmx_pko_dqx_pick_s cn78xx;
        struct cvmx_pko_dqx_pick_s cn78xxp1;
        struct cvmx_pko_dqx_pick_s cnf75xx;
};

typedef union cvmx_pko_dqx_pick cvmx_pko_dqx_pick_t;

/**
 * cvmx_pko_dq#_pir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_dqx_pir {
        u64 u64;
        struct cvmx_pko_dqx_pir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_dqx_pir_s cn73xx;
        struct cvmx_pko_dqx_pir_s cn78xx;
        struct cvmx_pko_dqx_pir_s cn78xxp1;
        struct cvmx_pko_dqx_pir_s cnf75xx;
};

typedef union cvmx_pko_dqx_pir cvmx_pko_dqx_pir_t;

/**
 * cvmx_pko_dq#_pointers
 *
 * This register has the same bit fields as PKO_L3_SQ(0..255)_POINTERS.
 *
 */
union cvmx_pko_dqx_pointers {
        u64 u64;
        struct cvmx_pko_dqx_pointers_s {
                u64 reserved_26_63 : 38;
                u64 prev : 10;
                u64 reserved_10_15 : 6;
                u64 next : 10;
        } s;
        struct cvmx_pko_dqx_pointers_cn73xx {
                u64 reserved_24_63 : 40;
                u64 prev : 8;
                u64 reserved_8_15 : 8;
                u64 next : 8;
        } cn73xx;
        struct cvmx_pko_dqx_pointers_s cn78xx;
        struct cvmx_pko_dqx_pointers_s cn78xxp1;
        struct cvmx_pko_dqx_pointers_cn73xx cnf75xx;
};

typedef union cvmx_pko_dqx_pointers cvmx_pko_dqx_pointers_t;

/**
 * cvmx_pko_dq#_sched_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE.
 *
 */
union cvmx_pko_dqx_sched_state {
        u64 u64;
        struct cvmx_pko_dqx_sched_state_s {
                u64 reserved_25_63 : 39;
                u64 rr_count : 25;
        } s;
        struct cvmx_pko_dqx_sched_state_s cn73xx;
        struct cvmx_pko_dqx_sched_state_s cn78xx;
        struct cvmx_pko_dqx_sched_state_s cn78xxp1;
        struct cvmx_pko_dqx_sched_state_s cnf75xx;
};

typedef union cvmx_pko_dqx_sched_state cvmx_pko_dqx_sched_state_t;

/**
 * cvmx_pko_dq#_schedule
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE.
 *
 */
union cvmx_pko_dqx_schedule {
        u64 u64;
        struct cvmx_pko_dqx_schedule_s {
                u64 reserved_28_63 : 36;
                u64 prio : 4;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_dqx_schedule_s cn73xx;
        struct cvmx_pko_dqx_schedule_s cn78xx;
        struct cvmx_pko_dqx_schedule_s cn78xxp1;
        struct cvmx_pko_dqx_schedule_s cnf75xx;
};

typedef union cvmx_pko_dqx_schedule cvmx_pko_dqx_schedule_t;

/**
 * cvmx_pko_dq#_shape
 *
 * This register has the same bit fields as PKO_L3_SQ()_SHAPE.
 *
 */
union cvmx_pko_dqx_shape {
        u64 u64;
        struct cvmx_pko_dqx_shape_s {
                u64 reserved_27_63 : 37;
                u64 schedule_list : 2;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_dqx_shape_s cn73xx;
        struct cvmx_pko_dqx_shape_cn78xx {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } cn78xx;
        struct cvmx_pko_dqx_shape_cn78xx cn78xxp1;
        struct cvmx_pko_dqx_shape_s cnf75xx;
};

typedef union cvmx_pko_dqx_shape cvmx_pko_dqx_shape_t;

/**
 * cvmx_pko_dq#_shape_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE.
 * This register must not be written during normal operation.
 */
union cvmx_pko_dqx_shape_state {
        u64 u64;
        struct cvmx_pko_dqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color : 2;
                u64 pir_accum : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_dqx_shape_state_s cn73xx;
        struct cvmx_pko_dqx_shape_state_s cn78xx;
        struct cvmx_pko_dqx_shape_state_s cn78xxp1;
        struct cvmx_pko_dqx_shape_state_s cnf75xx;
};

typedef union cvmx_pko_dqx_shape_state cvmx_pko_dqx_shape_state_t;

/**
 * cvmx_pko_dq#_sw_xoff
 *
 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF.
 *
 */
union cvmx_pko_dqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_dqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_dqx_sw_xoff_s cn73xx;
        struct cvmx_pko_dqx_sw_xoff_s cn78xx;
        struct cvmx_pko_dqx_sw_xoff_s cn78xxp1;
        struct cvmx_pko_dqx_sw_xoff_s cnf75xx;
};

typedef union cvmx_pko_dqx_sw_xoff cvmx_pko_dqx_sw_xoff_t;

/**
 * cvmx_pko_dq#_topology
 */
union cvmx_pko_dqx_topology {
        u64 u64;
        struct cvmx_pko_dqx_topology_s {
                u64 reserved_26_63 : 38;
                u64 parent : 10;
                u64 reserved_0_15 : 16;
        } s;
        struct cvmx_pko_dqx_topology_cn73xx {
                u64 reserved_24_63 : 40;
                u64 parent : 8;
                u64 reserved_0_15 : 16;
        } cn73xx;
        struct cvmx_pko_dqx_topology_s cn78xx;
        struct cvmx_pko_dqx_topology_s cn78xxp1;
        struct cvmx_pko_dqx_topology_cn73xx cnf75xx;
};

typedef union cvmx_pko_dqx_topology cvmx_pko_dqx_topology_t;

/**
 * cvmx_pko_dq#_wm_buf_cnt
 */
union cvmx_pko_dqx_wm_buf_cnt {
        u64 u64;
        struct cvmx_pko_dqx_wm_buf_cnt_s {
                u64 reserved_36_63 : 28;
                u64 count : 36;
        } s;
        struct cvmx_pko_dqx_wm_buf_cnt_s cn73xx;
        struct cvmx_pko_dqx_wm_buf_cnt_s cn78xx;
        struct cvmx_pko_dqx_wm_buf_cnt_s cn78xxp1;
        struct cvmx_pko_dqx_wm_buf_cnt_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_buf_cnt cvmx_pko_dqx_wm_buf_cnt_t;

/**
 * cvmx_pko_dq#_wm_buf_ctl
 */
union cvmx_pko_dqx_wm_buf_ctl {
        u64 u64;
        struct cvmx_pko_dqx_wm_buf_ctl_s {
                u64 reserved_51_63 : 13;
                u64 enable : 1;
                u64 reserved_49_49 : 1;
                u64 intr : 1;
                u64 reserved_36_47 : 12;
                u64 threshold : 36;
        } s;
        struct cvmx_pko_dqx_wm_buf_ctl_s cn73xx;
        struct cvmx_pko_dqx_wm_buf_ctl_s cn78xx;
        struct cvmx_pko_dqx_wm_buf_ctl_s cn78xxp1;
        struct cvmx_pko_dqx_wm_buf_ctl_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_buf_ctl cvmx_pko_dqx_wm_buf_ctl_t;

/**
 * cvmx_pko_dq#_wm_buf_ctl_w1c
 */
union cvmx_pko_dqx_wm_buf_ctl_w1c {
        u64 u64;
        struct cvmx_pko_dqx_wm_buf_ctl_w1c_s {
                u64 reserved_49_63 : 15;
                u64 intr : 1;
                u64 reserved_0_47 : 48;
        } s;
        struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn73xx;
        struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xx;
        struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xxp1;
        struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_buf_ctl_w1c cvmx_pko_dqx_wm_buf_ctl_w1c_t;

/**
 * cvmx_pko_dq#_wm_cnt
 */
union cvmx_pko_dqx_wm_cnt {
        u64 u64;
        struct cvmx_pko_dqx_wm_cnt_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_dqx_wm_cnt_s cn73xx;
        struct cvmx_pko_dqx_wm_cnt_s cn78xx;
        struct cvmx_pko_dqx_wm_cnt_s cn78xxp1;
        struct cvmx_pko_dqx_wm_cnt_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_cnt cvmx_pko_dqx_wm_cnt_t;

/**
 * cvmx_pko_dq#_wm_ctl
 */
union cvmx_pko_dqx_wm_ctl {
        u64 u64;
        struct cvmx_pko_dqx_wm_ctl_s {
                u64 reserved_52_63 : 12;
                u64 ncb_query_rsp : 1;
                u64 enable : 1;
                u64 kind : 1;
                u64 intr : 1;
                u64 threshold : 48;
        } s;
        struct cvmx_pko_dqx_wm_ctl_s cn73xx;
        struct cvmx_pko_dqx_wm_ctl_s cn78xx;
        struct cvmx_pko_dqx_wm_ctl_s cn78xxp1;
        struct cvmx_pko_dqx_wm_ctl_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_ctl cvmx_pko_dqx_wm_ctl_t;

/**
 * cvmx_pko_dq#_wm_ctl_w1c
 */
union cvmx_pko_dqx_wm_ctl_w1c {
        u64 u64;
        struct cvmx_pko_dqx_wm_ctl_w1c_s {
                u64 reserved_49_63 : 15;
                u64 intr : 1;
                u64 reserved_0_47 : 48;
        } s;
        struct cvmx_pko_dqx_wm_ctl_w1c_s cn73xx;
        struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xx;
        struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xxp1;
        struct cvmx_pko_dqx_wm_ctl_w1c_s cnf75xx;
};

typedef union cvmx_pko_dqx_wm_ctl_w1c cvmx_pko_dqx_wm_ctl_w1c_t;

/**
 * cvmx_pko_dq_csr_bus_debug
 */
union cvmx_pko_dq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_dq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_dq_csr_bus_debug_s cn73xx;
        struct cvmx_pko_dq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_dq_csr_bus_debug_s cn78xxp1;
        struct cvmx_pko_dq_csr_bus_debug_s cnf75xx;
};

typedef union cvmx_pko_dq_csr_bus_debug cvmx_pko_dq_csr_bus_debug_t;

/**
 * cvmx_pko_dq_debug
 */
union cvmx_pko_dq_debug {
        u64 u64;
        struct cvmx_pko_dq_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_dq_debug_s cn73xx;
        struct cvmx_pko_dq_debug_s cn78xx;
        struct cvmx_pko_dq_debug_s cn78xxp1;
        struct cvmx_pko_dq_debug_s cnf75xx;
};

typedef union cvmx_pko_dq_debug cvmx_pko_dq_debug_t;

/**
 * cvmx_pko_drain_irq
 */
union cvmx_pko_drain_irq {
        u64 u64;
        struct cvmx_pko_drain_irq_s {
                u64 reserved_1_63 : 63;
                u64 intr : 1;
        } s;
        struct cvmx_pko_drain_irq_s cn73xx;
        struct cvmx_pko_drain_irq_s cn78xx;
        struct cvmx_pko_drain_irq_s cn78xxp1;
        struct cvmx_pko_drain_irq_s cnf75xx;
};

typedef union cvmx_pko_drain_irq cvmx_pko_drain_irq_t;

/**
 * cvmx_pko_enable
 */
union cvmx_pko_enable {
        u64 u64;
        struct cvmx_pko_enable_s {
                u64 reserved_1_63 : 63;
                u64 enable : 1;
        } s;
        struct cvmx_pko_enable_s cn73xx;
        struct cvmx_pko_enable_s cn78xx;
        struct cvmx_pko_enable_s cn78xxp1;
        struct cvmx_pko_enable_s cnf75xx;
};

typedef union cvmx_pko_enable cvmx_pko_enable_t;

/**
 * cvmx_pko_format#_ctl
 *
 * Describes packet marking calculations for YELLOW and for RED_SEND packets.
 * PKO_SEND_HDR_S[FORMAT] selects the CSR used for the packet descriptor.
 *
 * All the packet marking calculations assume big-endian bits within a byte.
 *
 * For example, if MARKPTR is 3 and [OFFSET] is 5 and the packet is YELLOW,
 * the PKO marking hardware would do this:
 *
 * _  byte[3]<2:0> |=   Y_VAL<3:1>
 * _  byte[3]<2:0> &= ~Y_MASK<3:1>
 * _  byte[4]<7>   |=   Y_VAL<0>
 * _  byte[4]<7>   &= ~Y_MASK<0>
 *
 * where byte[3] is the 3rd byte in the packet, and byte[4] the 4th.
 *
 * For another example, if MARKPTR is 3 and [OFFSET] is 0 and the packet is RED_SEND,
 *
 * _   byte[3]<7:4> |=   R_VAL<3:0>
 * _   byte[3]<7:4> &= ~R_MASK<3:0>
 */
union cvmx_pko_formatx_ctl {
        u64 u64;
        struct cvmx_pko_formatx_ctl_s {
                u64 reserved_27_63 : 37;
                u64 offset : 11;
                u64 y_mask : 4;
                u64 y_val : 4;
                u64 r_mask : 4;
                u64 r_val : 4;
        } s;
        struct cvmx_pko_formatx_ctl_s cn73xx;
        struct cvmx_pko_formatx_ctl_s cn78xx;
        struct cvmx_pko_formatx_ctl_s cn78xxp1;

        struct cvmx_pko_formatx_ctl_s cnf75xx;
};

typedef union cvmx_pko_formatx_ctl cvmx_pko_formatx_ctl_t;

/**
 * cvmx_pko_l1_sq#_cir
 */
union cvmx_pko_l1_sqx_cir {
        u64 u64;
        struct cvmx_pko_l1_sqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l1_sqx_cir_s cn73xx;
        struct cvmx_pko_l1_sqx_cir_s cn78xx;
        struct cvmx_pko_l1_sqx_cir_s cn78xxp1;
        struct cvmx_pko_l1_sqx_cir_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_cir cvmx_pko_l1_sqx_cir_t;

/**
 * cvmx_pko_l1_sq#_dropped_bytes
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES.
 *
 */
union cvmx_pko_l1_sqx_dropped_bytes {
        u64 u64;
        struct cvmx_pko_l1_sqx_dropped_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_l1_sqx_dropped_bytes_s cn73xx;
        struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xx;
        struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xxp1;
        struct cvmx_pko_l1_sqx_dropped_bytes_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_dropped_bytes cvmx_pko_l1_sqx_dropped_bytes_t;

/**
 * cvmx_pko_l1_sq#_dropped_packets
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS.
 *
 */
union cvmx_pko_l1_sqx_dropped_packets {
        u64 u64;
        struct cvmx_pko_l1_sqx_dropped_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_l1_sqx_dropped_packets_s cn73xx;
        struct cvmx_pko_l1_sqx_dropped_packets_s cn78xx;
        struct cvmx_pko_l1_sqx_dropped_packets_s cn78xxp1;
        struct cvmx_pko_l1_sqx_dropped_packets_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_dropped_packets cvmx_pko_l1_sqx_dropped_packets_t;

/**
 * cvmx_pko_l1_sq#_green
 */
union cvmx_pko_l1_sqx_green {
        u64 u64;
        struct cvmx_pko_l1_sqx_green_s {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 reserved_19_19 : 1;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l1_sqx_green_s cn73xx;
        struct cvmx_pko_l1_sqx_green_s cn78xx;
        struct cvmx_pko_l1_sqx_green_s cn78xxp1;
        struct cvmx_pko_l1_sqx_green_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_green cvmx_pko_l1_sqx_green_t;

/**
 * cvmx_pko_l1_sq#_green_bytes
 */
union cvmx_pko_l1_sqx_green_bytes {
        u64 u64;
        struct cvmx_pko_l1_sqx_green_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_l1_sqx_green_bytes_s cn73xx;
        struct cvmx_pko_l1_sqx_green_bytes_s cn78xx;
        struct cvmx_pko_l1_sqx_green_bytes_s cn78xxp1;
        struct cvmx_pko_l1_sqx_green_bytes_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_green_bytes cvmx_pko_l1_sqx_green_bytes_t;

/**
 * cvmx_pko_l1_sq#_green_packets
 */
union cvmx_pko_l1_sqx_green_packets {
        u64 u64;
        struct cvmx_pko_l1_sqx_green_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_l1_sqx_green_packets_s cn73xx;
        struct cvmx_pko_l1_sqx_green_packets_s cn78xx;
        struct cvmx_pko_l1_sqx_green_packets_s cn78xxp1;
        struct cvmx_pko_l1_sqx_green_packets_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_green_packets cvmx_pko_l1_sqx_green_packets_t;

/**
 * cvmx_pko_l1_sq#_link
 */
union cvmx_pko_l1_sqx_link {
        u64 u64;
        struct cvmx_pko_l1_sqx_link_s {
                u64 reserved_49_63 : 15;
                u64 link : 5;
                u64 reserved_32_43 : 12;
                u64 cc_word_cnt : 20;
                u64 cc_packet_cnt : 10;
                u64 cc_enable : 1;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l1_sqx_link_cn73xx {
                u64 reserved_48_63 : 16;
                u64 link : 4;
                u64 reserved_32_43 : 12;
                u64 cc_word_cnt : 20;
                u64 cc_packet_cnt : 10;
                u64 cc_enable : 1;
                u64 reserved_0_0 : 1;
        } cn73xx;
        struct cvmx_pko_l1_sqx_link_s cn78xx;
        struct cvmx_pko_l1_sqx_link_s cn78xxp1;
        struct cvmx_pko_l1_sqx_link_cn73xx cnf75xx;
};

typedef union cvmx_pko_l1_sqx_link cvmx_pko_l1_sqx_link_t;

/**
 * cvmx_pko_l1_sq#_pick
 *
 * This CSR contains the meta for the L1 SQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_l1_sqx_pick {
        u64 u64;
        struct cvmx_pko_l1_sqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_l1_sqx_pick_s cn73xx;
        struct cvmx_pko_l1_sqx_pick_s cn78xx;
        struct cvmx_pko_l1_sqx_pick_s cn78xxp1;
        struct cvmx_pko_l1_sqx_pick_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_pick cvmx_pko_l1_sqx_pick_t;

/**
 * cvmx_pko_l1_sq#_red
 *
 * This register has the same bit fields as PKO_L1_SQ()_YELLOW.
 *
 */
union cvmx_pko_l1_sqx_red {
        u64 u64;
        struct cvmx_pko_l1_sqx_red_s {
                u64 reserved_19_63 : 45;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l1_sqx_red_s cn73xx;
        struct cvmx_pko_l1_sqx_red_s cn78xx;
        struct cvmx_pko_l1_sqx_red_s cn78xxp1;
        struct cvmx_pko_l1_sqx_red_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_red cvmx_pko_l1_sqx_red_t;

/**
 * cvmx_pko_l1_sq#_red_bytes
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES.
 *
 */
union cvmx_pko_l1_sqx_red_bytes {
        u64 u64;
        struct cvmx_pko_l1_sqx_red_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_l1_sqx_red_bytes_s cn73xx;
        struct cvmx_pko_l1_sqx_red_bytes_s cn78xx;
        struct cvmx_pko_l1_sqx_red_bytes_s cn78xxp1;
        struct cvmx_pko_l1_sqx_red_bytes_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_red_bytes cvmx_pko_l1_sqx_red_bytes_t;

/**
 * cvmx_pko_l1_sq#_red_packets
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS.
 *
 */
union cvmx_pko_l1_sqx_red_packets {
        u64 u64;
        struct cvmx_pko_l1_sqx_red_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_l1_sqx_red_packets_s cn73xx;
        struct cvmx_pko_l1_sqx_red_packets_s cn78xx;
        struct cvmx_pko_l1_sqx_red_packets_s cn78xxp1;
        struct cvmx_pko_l1_sqx_red_packets_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_red_packets cvmx_pko_l1_sqx_red_packets_t;

/**
 * cvmx_pko_l1_sq#_schedule
 */
union cvmx_pko_l1_sqx_schedule {
        u64 u64;
        struct cvmx_pko_l1_sqx_schedule_s {
                u64 dummy : 40;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_l1_sqx_schedule_cn73xx {
                u64 reserved_24_63 : 40;
                u64 rr_quantum : 24;
        } cn73xx;
        struct cvmx_pko_l1_sqx_schedule_cn73xx cn78xx;
        struct cvmx_pko_l1_sqx_schedule_s cn78xxp1;
        struct cvmx_pko_l1_sqx_schedule_cn73xx cnf75xx;
};

typedef union cvmx_pko_l1_sqx_schedule cvmx_pko_l1_sqx_schedule_t;

/**
 * cvmx_pko_l1_sq#_shape
 */
union cvmx_pko_l1_sqx_shape {
        u64 u64;
        struct cvmx_pko_l1_sqx_shape_s {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_18_23 : 6;
                u64 link : 5;
                u64 reserved_9_12 : 4;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_l1_sqx_shape_cn73xx {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_17_23 : 7;
                u64 link : 4;
                u64 reserved_9_12 : 4;
                u64 adjust : 9;
        } cn73xx;
        struct cvmx_pko_l1_sqx_shape_s cn78xx;
        struct cvmx_pko_l1_sqx_shape_s cn78xxp1;
        struct cvmx_pko_l1_sqx_shape_cn73xx cnf75xx;
};

typedef union cvmx_pko_l1_sqx_shape cvmx_pko_l1_sqx_shape_t;

/**
 * cvmx_pko_l1_sq#_shape_state
 *
 * This register must not be written during normal operation.
 *
 */
union cvmx_pko_l1_sqx_shape_state {
        u64 u64;
        struct cvmx_pko_l1_sqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color2 : 1;
                u64 color : 1;
                u64 reserved_26_51 : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_l1_sqx_shape_state_cn73xx {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 reserved_53_53 : 1;
                u64 color : 1;
                u64 reserved_26_51 : 26;
                u64 cir_accum : 26;
        } cn73xx;
        struct cvmx_pko_l1_sqx_shape_state_cn73xx cn78xx;
        struct cvmx_pko_l1_sqx_shape_state_s cn78xxp1;
        struct cvmx_pko_l1_sqx_shape_state_cn73xx cnf75xx;
};

typedef union cvmx_pko_l1_sqx_shape_state cvmx_pko_l1_sqx_shape_state_t;

/**
 * cvmx_pko_l1_sq#_sw_xoff
 */
union cvmx_pko_l1_sqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_l1_sqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_l1_sqx_sw_xoff_s cn73xx;
        struct cvmx_pko_l1_sqx_sw_xoff_s cn78xx;
        struct cvmx_pko_l1_sqx_sw_xoff_s cn78xxp1;
        struct cvmx_pko_l1_sqx_sw_xoff_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_sw_xoff cvmx_pko_l1_sqx_sw_xoff_t;

/**
 * cvmx_pko_l1_sq#_topology
 */
union cvmx_pko_l1_sqx_topology {
        u64 u64;
        struct cvmx_pko_l1_sqx_topology_s {
                u64 reserved_41_63 : 23;
                u64 prio_anchor : 9;
                u64 reserved_21_31 : 11;
                u64 link : 5;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l1_sqx_topology_cn73xx {
                u64 reserved_40_63 : 24;
                u64 prio_anchor : 8;
                u64 reserved_20_31 : 12;
                u64 link : 4;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } cn73xx;
        struct cvmx_pko_l1_sqx_topology_s cn78xx;
        struct cvmx_pko_l1_sqx_topology_s cn78xxp1;
        struct cvmx_pko_l1_sqx_topology_cn73xx cnf75xx;
};

typedef union cvmx_pko_l1_sqx_topology cvmx_pko_l1_sqx_topology_t;

/**
 * cvmx_pko_l1_sq#_yellow
 */
union cvmx_pko_l1_sqx_yellow {
        u64 u64;
        struct cvmx_pko_l1_sqx_yellow_s {
                u64 reserved_19_63 : 45;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l1_sqx_yellow_s cn73xx;
        struct cvmx_pko_l1_sqx_yellow_s cn78xx;
        struct cvmx_pko_l1_sqx_yellow_s cn78xxp1;
        struct cvmx_pko_l1_sqx_yellow_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_yellow cvmx_pko_l1_sqx_yellow_t;

/**
 * cvmx_pko_l1_sq#_yellow_bytes
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES.
 *
 */
union cvmx_pko_l1_sqx_yellow_bytes {
        u64 u64;
        struct cvmx_pko_l1_sqx_yellow_bytes_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_l1_sqx_yellow_bytes_s cn73xx;
        struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xx;
        struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xxp1;
        struct cvmx_pko_l1_sqx_yellow_bytes_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_yellow_bytes cvmx_pko_l1_sqx_yellow_bytes_t;

/**
 * cvmx_pko_l1_sq#_yellow_packets
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS.
 *
 */
union cvmx_pko_l1_sqx_yellow_packets {
        u64 u64;
        struct cvmx_pko_l1_sqx_yellow_packets_s {
                u64 reserved_40_63 : 24;
                u64 count : 40;
        } s;
        struct cvmx_pko_l1_sqx_yellow_packets_s cn73xx;
        struct cvmx_pko_l1_sqx_yellow_packets_s cn78xx;
        struct cvmx_pko_l1_sqx_yellow_packets_s cn78xxp1;
        struct cvmx_pko_l1_sqx_yellow_packets_s cnf75xx;
};

typedef union cvmx_pko_l1_sqx_yellow_packets cvmx_pko_l1_sqx_yellow_packets_t;

/**
 * cvmx_pko_l1_sq_csr_bus_debug
 */
union cvmx_pko_l1_sq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_l1_sq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_l1_sq_csr_bus_debug_s cn73xx;
        struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xxp1;
        struct cvmx_pko_l1_sq_csr_bus_debug_s cnf75xx;
};

typedef union cvmx_pko_l1_sq_csr_bus_debug cvmx_pko_l1_sq_csr_bus_debug_t;

/**
 * cvmx_pko_l1_sqa_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l1_sqa_debug {
        u64 u64;
        struct cvmx_pko_l1_sqa_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l1_sqa_debug_s cn73xx;
        struct cvmx_pko_l1_sqa_debug_s cn78xx;
        struct cvmx_pko_l1_sqa_debug_s cn78xxp1;
        struct cvmx_pko_l1_sqa_debug_s cnf75xx;
};

typedef union cvmx_pko_l1_sqa_debug cvmx_pko_l1_sqa_debug_t;

/**
 * cvmx_pko_l1_sqb_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l1_sqb_debug {
        u64 u64;
        struct cvmx_pko_l1_sqb_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l1_sqb_debug_s cn73xx;
        struct cvmx_pko_l1_sqb_debug_s cn78xx;
        struct cvmx_pko_l1_sqb_debug_s cn78xxp1;
        struct cvmx_pko_l1_sqb_debug_s cnf75xx;
};

typedef union cvmx_pko_l1_sqb_debug cvmx_pko_l1_sqb_debug_t;

/**
 * cvmx_pko_l2_sq#_cir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l2_sqx_cir {
        u64 u64;
        struct cvmx_pko_l2_sqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l2_sqx_cir_s cn73xx;
        struct cvmx_pko_l2_sqx_cir_s cn78xx;
        struct cvmx_pko_l2_sqx_cir_s cn78xxp1;
        struct cvmx_pko_l2_sqx_cir_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_cir cvmx_pko_l2_sqx_cir_t;

/**
 * cvmx_pko_l2_sq#_green
 *
 * This register has the same bit fields as PKO_L1_SQ()_GREEN.
 *
 */
union cvmx_pko_l2_sqx_green {
        u64 u64;
        struct cvmx_pko_l2_sqx_green_s {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 reserved_19_19 : 1;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l2_sqx_green_s cn73xx;
        struct cvmx_pko_l2_sqx_green_s cn78xx;
        struct cvmx_pko_l2_sqx_green_s cn78xxp1;
        struct cvmx_pko_l2_sqx_green_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_green cvmx_pko_l2_sqx_green_t;

/**
 * cvmx_pko_l2_sq#_pick
 *
 * This CSR contains the meta for the L2 SQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_l2_sqx_pick {
        u64 u64;
        struct cvmx_pko_l2_sqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_l2_sqx_pick_s cn73xx;
        struct cvmx_pko_l2_sqx_pick_s cn78xx;
        struct cvmx_pko_l2_sqx_pick_s cn78xxp1;
        struct cvmx_pko_l2_sqx_pick_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_pick cvmx_pko_l2_sqx_pick_t;

/**
 * cvmx_pko_l2_sq#_pir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l2_sqx_pir {
        u64 u64;
        struct cvmx_pko_l2_sqx_pir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l2_sqx_pir_s cn73xx;
        struct cvmx_pko_l2_sqx_pir_s cn78xx;
        struct cvmx_pko_l2_sqx_pir_s cn78xxp1;
        struct cvmx_pko_l2_sqx_pir_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_pir cvmx_pko_l2_sqx_pir_t;

/**
 * cvmx_pko_l2_sq#_pointers
 */
union cvmx_pko_l2_sqx_pointers {
        u64 u64;
        struct cvmx_pko_l2_sqx_pointers_s {
                u64 reserved_25_63 : 39;
                u64 prev : 9;
                u64 reserved_9_15 : 7;
                u64 next : 9;
        } s;
        struct cvmx_pko_l2_sqx_pointers_cn73xx {
                u64 reserved_24_63 : 40;
                u64 prev : 8;
                u64 reserved_8_15 : 8;
                u64 next : 8;
        } cn73xx;
        struct cvmx_pko_l2_sqx_pointers_s cn78xx;
        struct cvmx_pko_l2_sqx_pointers_s cn78xxp1;
        struct cvmx_pko_l2_sqx_pointers_cn73xx cnf75xx;
};

typedef union cvmx_pko_l2_sqx_pointers cvmx_pko_l2_sqx_pointers_t;

/**
 * cvmx_pko_l2_sq#_red
 *
 * This register has the same bit fields as PKO_L1_SQ()_RED.
 *
 */
union cvmx_pko_l2_sqx_red {
        u64 u64;
        struct cvmx_pko_l2_sqx_red_s {
                u64 reserved_19_63 : 45;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l2_sqx_red_s cn73xx;
        struct cvmx_pko_l2_sqx_red_s cn78xx;
        struct cvmx_pko_l2_sqx_red_s cn78xxp1;
        struct cvmx_pko_l2_sqx_red_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_red cvmx_pko_l2_sqx_red_t;

/**
 * cvmx_pko_l2_sq#_sched_state
 */
union cvmx_pko_l2_sqx_sched_state {
        u64 u64;
        struct cvmx_pko_l2_sqx_sched_state_s {
                u64 reserved_25_63 : 39;
                u64 rr_count : 25;
        } s;
        struct cvmx_pko_l2_sqx_sched_state_s cn73xx;
        struct cvmx_pko_l2_sqx_sched_state_s cn78xx;
        struct cvmx_pko_l2_sqx_sched_state_s cn78xxp1;
        struct cvmx_pko_l2_sqx_sched_state_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_sched_state cvmx_pko_l2_sqx_sched_state_t;

/**
 * cvmx_pko_l2_sq#_schedule
 */
union cvmx_pko_l2_sqx_schedule {
        u64 u64;
        struct cvmx_pko_l2_sqx_schedule_s {
                u64 reserved_28_63 : 36;
                u64 prio : 4;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_l2_sqx_schedule_s cn73xx;
        struct cvmx_pko_l2_sqx_schedule_s cn78xx;
        struct cvmx_pko_l2_sqx_schedule_s cn78xxp1;
        struct cvmx_pko_l2_sqx_schedule_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_schedule cvmx_pko_l2_sqx_schedule_t;

/**
 * cvmx_pko_l2_sq#_shape
 */
union cvmx_pko_l2_sqx_shape {
        u64 u64;
        struct cvmx_pko_l2_sqx_shape_s {
                u64 reserved_27_63 : 37;
                u64 schedule_list : 2;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_l2_sqx_shape_s cn73xx;
        struct cvmx_pko_l2_sqx_shape_cn78xx {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } cn78xx;
        struct cvmx_pko_l2_sqx_shape_cn78xx cn78xxp1;
        struct cvmx_pko_l2_sqx_shape_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_shape cvmx_pko_l2_sqx_shape_t;

/**
 * cvmx_pko_l2_sq#_shape_state
 *
 * This register must not be written during normal operation.
 *
 */
union cvmx_pko_l2_sqx_shape_state {
        u64 u64;
        struct cvmx_pko_l2_sqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color : 2;
                u64 pir_accum : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_l2_sqx_shape_state_s cn73xx;
        struct cvmx_pko_l2_sqx_shape_state_s cn78xx;
        struct cvmx_pko_l2_sqx_shape_state_s cn78xxp1;
        struct cvmx_pko_l2_sqx_shape_state_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_shape_state cvmx_pko_l2_sqx_shape_state_t;

/**
 * cvmx_pko_l2_sq#_sw_xoff
 *
 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF.
 *
 */
union cvmx_pko_l2_sqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_l2_sqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_l2_sqx_sw_xoff_s cn73xx;
        struct cvmx_pko_l2_sqx_sw_xoff_s cn78xx;
        struct cvmx_pko_l2_sqx_sw_xoff_s cn78xxp1;
        struct cvmx_pko_l2_sqx_sw_xoff_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_sw_xoff cvmx_pko_l2_sqx_sw_xoff_t;

/**
 * cvmx_pko_l2_sq#_topology
 */
union cvmx_pko_l2_sqx_topology {
        u64 u64;
        struct cvmx_pko_l2_sqx_topology_s {
                u64 reserved_41_63 : 23;
                u64 prio_anchor : 9;
                u64 reserved_21_31 : 11;
                u64 parent : 5;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l2_sqx_topology_cn73xx {
                u64 reserved_40_63 : 24;
                u64 prio_anchor : 8;
                u64 reserved_20_31 : 12;
                u64 parent : 4;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } cn73xx;
        struct cvmx_pko_l2_sqx_topology_s cn78xx;
        struct cvmx_pko_l2_sqx_topology_s cn78xxp1;
        struct cvmx_pko_l2_sqx_topology_cn73xx cnf75xx;
};

typedef union cvmx_pko_l2_sqx_topology cvmx_pko_l2_sqx_topology_t;

/**
 * cvmx_pko_l2_sq#_yellow
 *
 * This register has the same bit fields as PKO_L1_SQ()_YELLOW.
 *
 */
union cvmx_pko_l2_sqx_yellow {
        u64 u64;
        struct cvmx_pko_l2_sqx_yellow_s {
                u64 reserved_19_63 : 45;
                u64 head : 9;
                u64 reserved_9_9 : 1;
                u64 tail : 9;
        } s;
        struct cvmx_pko_l2_sqx_yellow_s cn73xx;
        struct cvmx_pko_l2_sqx_yellow_s cn78xx;
        struct cvmx_pko_l2_sqx_yellow_s cn78xxp1;
        struct cvmx_pko_l2_sqx_yellow_s cnf75xx;
};

typedef union cvmx_pko_l2_sqx_yellow cvmx_pko_l2_sqx_yellow_t;

/**
 * cvmx_pko_l2_sq_csr_bus_debug
 */
union cvmx_pko_l2_sq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_l2_sq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_l2_sq_csr_bus_debug_s cn73xx;
        struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xxp1;
        struct cvmx_pko_l2_sq_csr_bus_debug_s cnf75xx;
};

typedef union cvmx_pko_l2_sq_csr_bus_debug cvmx_pko_l2_sq_csr_bus_debug_t;

/**
 * cvmx_pko_l2_sqa_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l2_sqa_debug {
        u64 u64;
        struct cvmx_pko_l2_sqa_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l2_sqa_debug_s cn73xx;
        struct cvmx_pko_l2_sqa_debug_s cn78xx;
        struct cvmx_pko_l2_sqa_debug_s cn78xxp1;
        struct cvmx_pko_l2_sqa_debug_s cnf75xx;
};

typedef union cvmx_pko_l2_sqa_debug cvmx_pko_l2_sqa_debug_t;

/**
 * cvmx_pko_l2_sqb_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l2_sqb_debug {
        u64 u64;
        struct cvmx_pko_l2_sqb_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l2_sqb_debug_s cn73xx;
        struct cvmx_pko_l2_sqb_debug_s cn78xx;
        struct cvmx_pko_l2_sqb_debug_s cn78xxp1;
        struct cvmx_pko_l2_sqb_debug_s cnf75xx;
};

typedef union cvmx_pko_l2_sqb_debug cvmx_pko_l2_sqb_debug_t;

/**
 * cvmx_pko_l3_l2_sq#_channel
 *
 * PKO_CHANNEL_LEVEL[CC_LEVEL] determines whether this CSR array is associated to
 * the L2 SQs or the L3 SQs.
 */
union cvmx_pko_l3_l2_sqx_channel {
        u64 u64;
        struct cvmx_pko_l3_l2_sqx_channel_s {
                u64 reserved_44_63 : 20;
                u64 cc_channel : 12;
                u64 cc_word_cnt : 20;
                u64 cc_packet_cnt : 10;
                u64 cc_enable : 1;
                u64 hw_xoff : 1;
        } s;
        struct cvmx_pko_l3_l2_sqx_channel_s cn73xx;
        struct cvmx_pko_l3_l2_sqx_channel_s cn78xx;
        struct cvmx_pko_l3_l2_sqx_channel_s cn78xxp1;
        struct cvmx_pko_l3_l2_sqx_channel_s cnf75xx;
};

typedef union cvmx_pko_l3_l2_sqx_channel cvmx_pko_l3_l2_sqx_channel_t;

/**
 * cvmx_pko_l3_sq#_cir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l3_sqx_cir {
        u64 u64;
        struct cvmx_pko_l3_sqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l3_sqx_cir_s cn73xx;
        struct cvmx_pko_l3_sqx_cir_s cn78xx;
        struct cvmx_pko_l3_sqx_cir_s cn78xxp1;
        struct cvmx_pko_l3_sqx_cir_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_cir cvmx_pko_l3_sqx_cir_t;

/**
 * cvmx_pko_l3_sq#_green
 */
union cvmx_pko_l3_sqx_green {
        u64 u64;
        struct cvmx_pko_l3_sqx_green_s {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l3_sqx_green_cn73xx {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 reserved_18_19 : 2;
                u64 head : 8;
                u64 reserved_8_9 : 2;
                u64 tail : 8;
        } cn73xx;
        struct cvmx_pko_l3_sqx_green_s cn78xx;
        struct cvmx_pko_l3_sqx_green_s cn78xxp1;
        struct cvmx_pko_l3_sqx_green_cn73xx cnf75xx;
};

typedef union cvmx_pko_l3_sqx_green cvmx_pko_l3_sqx_green_t;

/**
 * cvmx_pko_l3_sq#_pick
 *
 * This CSR contains the meta for the L3 SQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_l3_sqx_pick {
        u64 u64;
        struct cvmx_pko_l3_sqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_l3_sqx_pick_s cn73xx;
        struct cvmx_pko_l3_sqx_pick_s cn78xx;
        struct cvmx_pko_l3_sqx_pick_s cn78xxp1;
        struct cvmx_pko_l3_sqx_pick_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_pick cvmx_pko_l3_sqx_pick_t;

/**
 * cvmx_pko_l3_sq#_pir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l3_sqx_pir {
        u64 u64;
        struct cvmx_pko_l3_sqx_pir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l3_sqx_pir_s cn73xx;
        struct cvmx_pko_l3_sqx_pir_s cn78xx;
        struct cvmx_pko_l3_sqx_pir_s cn78xxp1;
        struct cvmx_pko_l3_sqx_pir_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_pir cvmx_pko_l3_sqx_pir_t;

/**
 * cvmx_pko_l3_sq#_pointers
 *
 * This register has the same bit fields as PKO_L2_SQ()_POINTERS.
 *
 */
union cvmx_pko_l3_sqx_pointers {
        u64 u64;
        struct cvmx_pko_l3_sqx_pointers_s {
                u64 reserved_25_63 : 39;
                u64 prev : 9;
                u64 reserved_9_15 : 7;
                u64 next : 9;
        } s;
        struct cvmx_pko_l3_sqx_pointers_cn73xx {
                u64 reserved_24_63 : 40;
                u64 prev : 8;
                u64 reserved_8_15 : 8;
                u64 next : 8;
        } cn73xx;
        struct cvmx_pko_l3_sqx_pointers_s cn78xx;
        struct cvmx_pko_l3_sqx_pointers_s cn78xxp1;
        struct cvmx_pko_l3_sqx_pointers_cn73xx cnf75xx;
};

typedef union cvmx_pko_l3_sqx_pointers cvmx_pko_l3_sqx_pointers_t;

/**
 * cvmx_pko_l3_sq#_red
 *
 * This register has the same bit fields as PKO_L3_SQ()_YELLOW.
 *
 */
union cvmx_pko_l3_sqx_red {
        u64 u64;
        struct cvmx_pko_l3_sqx_red_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l3_sqx_red_cn73xx {
                u64 reserved_18_63 : 46;
                u64 head : 8;
                u64 reserved_8_9 : 2;
                u64 tail : 8;
        } cn73xx;
        struct cvmx_pko_l3_sqx_red_s cn78xx;
        struct cvmx_pko_l3_sqx_red_s cn78xxp1;
        struct cvmx_pko_l3_sqx_red_cn73xx cnf75xx;
};

typedef union cvmx_pko_l3_sqx_red cvmx_pko_l3_sqx_red_t;

/**
 * cvmx_pko_l3_sq#_sched_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE.
 *
 */
union cvmx_pko_l3_sqx_sched_state {
        u64 u64;
        struct cvmx_pko_l3_sqx_sched_state_s {
                u64 reserved_25_63 : 39;
                u64 rr_count : 25;
        } s;
        struct cvmx_pko_l3_sqx_sched_state_s cn73xx;
        struct cvmx_pko_l3_sqx_sched_state_s cn78xx;
        struct cvmx_pko_l3_sqx_sched_state_s cn78xxp1;
        struct cvmx_pko_l3_sqx_sched_state_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_sched_state cvmx_pko_l3_sqx_sched_state_t;

/**
 * cvmx_pko_l3_sq#_schedule
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE.
 *
 */
union cvmx_pko_l3_sqx_schedule {
        u64 u64;
        struct cvmx_pko_l3_sqx_schedule_s {
                u64 reserved_28_63 : 36;
                u64 prio : 4;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_l3_sqx_schedule_s cn73xx;
        struct cvmx_pko_l3_sqx_schedule_s cn78xx;
        struct cvmx_pko_l3_sqx_schedule_s cn78xxp1;
        struct cvmx_pko_l3_sqx_schedule_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_schedule cvmx_pko_l3_sqx_schedule_t;

/**
 * cvmx_pko_l3_sq#_shape
 */
union cvmx_pko_l3_sqx_shape {
        u64 u64;
        struct cvmx_pko_l3_sqx_shape_s {
                u64 reserved_27_63 : 37;
                u64 schedule_list : 2;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_l3_sqx_shape_s cn73xx;
        struct cvmx_pko_l3_sqx_shape_cn78xx {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } cn78xx;
        struct cvmx_pko_l3_sqx_shape_cn78xx cn78xxp1;
        struct cvmx_pko_l3_sqx_shape_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_shape cvmx_pko_l3_sqx_shape_t;

/**
 * cvmx_pko_l3_sq#_shape_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE.
 * This register must not be written during normal operation.
 */
union cvmx_pko_l3_sqx_shape_state {
        u64 u64;
        struct cvmx_pko_l3_sqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color : 2;
                u64 pir_accum : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_l3_sqx_shape_state_s cn73xx;
        struct cvmx_pko_l3_sqx_shape_state_s cn78xx;
        struct cvmx_pko_l3_sqx_shape_state_s cn78xxp1;
        struct cvmx_pko_l3_sqx_shape_state_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_shape_state cvmx_pko_l3_sqx_shape_state_t;

/**
 * cvmx_pko_l3_sq#_sw_xoff
 *
 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF
 *
 */
union cvmx_pko_l3_sqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_l3_sqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_l3_sqx_sw_xoff_s cn73xx;
        struct cvmx_pko_l3_sqx_sw_xoff_s cn78xx;
        struct cvmx_pko_l3_sqx_sw_xoff_s cn78xxp1;
        struct cvmx_pko_l3_sqx_sw_xoff_s cnf75xx;
};

typedef union cvmx_pko_l3_sqx_sw_xoff cvmx_pko_l3_sqx_sw_xoff_t;

/**
 * cvmx_pko_l3_sq#_topology
 */
union cvmx_pko_l3_sqx_topology {
        u64 u64;
        struct cvmx_pko_l3_sqx_topology_s {
                u64 reserved_42_63 : 22;
                u64 prio_anchor : 10;
                u64 reserved_25_31 : 7;
                u64 parent : 9;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l3_sqx_topology_cn73xx {
                u64 reserved_40_63 : 24;
                u64 prio_anchor : 8;
                u64 reserved_24_31 : 8;
                u64 parent : 8;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } cn73xx;
        struct cvmx_pko_l3_sqx_topology_s cn78xx;
        struct cvmx_pko_l3_sqx_topology_s cn78xxp1;
        struct cvmx_pko_l3_sqx_topology_cn73xx cnf75xx;
};

typedef union cvmx_pko_l3_sqx_topology cvmx_pko_l3_sqx_topology_t;

/**
 * cvmx_pko_l3_sq#_yellow
 */
union cvmx_pko_l3_sqx_yellow {
        u64 u64;
        struct cvmx_pko_l3_sqx_yellow_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l3_sqx_yellow_cn73xx {
                u64 reserved_18_63 : 46;
                u64 head : 8;
                u64 reserved_8_9 : 2;
                u64 tail : 8;
        } cn73xx;
        struct cvmx_pko_l3_sqx_yellow_s cn78xx;
        struct cvmx_pko_l3_sqx_yellow_s cn78xxp1;
        struct cvmx_pko_l3_sqx_yellow_cn73xx cnf75xx;
};

typedef union cvmx_pko_l3_sqx_yellow cvmx_pko_l3_sqx_yellow_t;

/**
 * cvmx_pko_l3_sq_csr_bus_debug
 */
union cvmx_pko_l3_sq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_l3_sq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_l3_sq_csr_bus_debug_s cn73xx;
        struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xxp1;
        struct cvmx_pko_l3_sq_csr_bus_debug_s cnf75xx;
};

typedef union cvmx_pko_l3_sq_csr_bus_debug cvmx_pko_l3_sq_csr_bus_debug_t;

/**
 * cvmx_pko_l3_sqa_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l3_sqa_debug {
        u64 u64;
        struct cvmx_pko_l3_sqa_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l3_sqa_debug_s cn73xx;
        struct cvmx_pko_l3_sqa_debug_s cn78xx;
        struct cvmx_pko_l3_sqa_debug_s cn78xxp1;
        struct cvmx_pko_l3_sqa_debug_s cnf75xx;
};

typedef union cvmx_pko_l3_sqa_debug cvmx_pko_l3_sqa_debug_t;

/**
 * cvmx_pko_l3_sqb_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l3_sqb_debug {
        u64 u64;
        struct cvmx_pko_l3_sqb_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l3_sqb_debug_s cn73xx;
        struct cvmx_pko_l3_sqb_debug_s cn78xx;
        struct cvmx_pko_l3_sqb_debug_s cn78xxp1;
        struct cvmx_pko_l3_sqb_debug_s cnf75xx;
};

typedef union cvmx_pko_l3_sqb_debug cvmx_pko_l3_sqb_debug_t;

/**
 * cvmx_pko_l4_sq#_cir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l4_sqx_cir {
        u64 u64;
        struct cvmx_pko_l4_sqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l4_sqx_cir_s cn78xx;
        struct cvmx_pko_l4_sqx_cir_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_cir cvmx_pko_l4_sqx_cir_t;

/**
 * cvmx_pko_l4_sq#_green
 *
 * This register has the same bit fields as PKO_L3_SQ()_GREEN.
 *
 */
union cvmx_pko_l4_sqx_green {
        u64 u64;
        struct cvmx_pko_l4_sqx_green_s {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l4_sqx_green_s cn78xx;
        struct cvmx_pko_l4_sqx_green_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_green cvmx_pko_l4_sqx_green_t;

/**
 * cvmx_pko_l4_sq#_pick
 *
 * This CSR contains the meta for the L4 SQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_l4_sqx_pick {
        u64 u64;
        struct cvmx_pko_l4_sqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_l4_sqx_pick_s cn78xx;
        struct cvmx_pko_l4_sqx_pick_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_pick cvmx_pko_l4_sqx_pick_t;

/**
 * cvmx_pko_l4_sq#_pir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l4_sqx_pir {
        u64 u64;
        struct cvmx_pko_l4_sqx_pir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l4_sqx_pir_s cn78xx;
        struct cvmx_pko_l4_sqx_pir_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_pir cvmx_pko_l4_sqx_pir_t;

/**
 * cvmx_pko_l4_sq#_pointers
 */
union cvmx_pko_l4_sqx_pointers {
        u64 u64;
        struct cvmx_pko_l4_sqx_pointers_s {
                u64 reserved_26_63 : 38;
                u64 prev : 10;
                u64 reserved_10_15 : 6;
                u64 next : 10;
        } s;
        struct cvmx_pko_l4_sqx_pointers_s cn78xx;
        struct cvmx_pko_l4_sqx_pointers_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_pointers cvmx_pko_l4_sqx_pointers_t;

/**
 * cvmx_pko_l4_sq#_red
 *
 * This register has the same bit fields as PKO_L3_SQ()_YELLOW.
 *
 */
union cvmx_pko_l4_sqx_red {
        u64 u64;
        struct cvmx_pko_l4_sqx_red_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l4_sqx_red_s cn78xx;
        struct cvmx_pko_l4_sqx_red_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_red cvmx_pko_l4_sqx_red_t;

/**
 * cvmx_pko_l4_sq#_sched_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE.
 *
 */
union cvmx_pko_l4_sqx_sched_state {
        u64 u64;
        struct cvmx_pko_l4_sqx_sched_state_s {
                u64 reserved_25_63 : 39;
                u64 rr_count : 25;
        } s;
        struct cvmx_pko_l4_sqx_sched_state_s cn78xx;
        struct cvmx_pko_l4_sqx_sched_state_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_sched_state cvmx_pko_l4_sqx_sched_state_t;

/**
 * cvmx_pko_l4_sq#_schedule
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE.
 *
 */
union cvmx_pko_l4_sqx_schedule {
        u64 u64;
        struct cvmx_pko_l4_sqx_schedule_s {
                u64 reserved_28_63 : 36;
                u64 prio : 4;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_l4_sqx_schedule_s cn78xx;
        struct cvmx_pko_l4_sqx_schedule_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_schedule cvmx_pko_l4_sqx_schedule_t;

/**
 * cvmx_pko_l4_sq#_shape
 *
 * This register has the same bit fields as PKO_L3_SQ()_SHAPE.
 *
 */
union cvmx_pko_l4_sqx_shape {
        u64 u64;
        struct cvmx_pko_l4_sqx_shape_s {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_l4_sqx_shape_s cn78xx;
        struct cvmx_pko_l4_sqx_shape_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_shape cvmx_pko_l4_sqx_shape_t;

/**
 * cvmx_pko_l4_sq#_shape_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE.
 * This register must not be written during normal operation.
 */
union cvmx_pko_l4_sqx_shape_state {
        u64 u64;
        struct cvmx_pko_l4_sqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color : 2;
                u64 pir_accum : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_l4_sqx_shape_state_s cn78xx;
        struct cvmx_pko_l4_sqx_shape_state_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_shape_state cvmx_pko_l4_sqx_shape_state_t;

/**
 * cvmx_pko_l4_sq#_sw_xoff
 *
 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF.
 *
 */
union cvmx_pko_l4_sqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_l4_sqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_l4_sqx_sw_xoff_s cn78xx;
        struct cvmx_pko_l4_sqx_sw_xoff_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_sw_xoff cvmx_pko_l4_sqx_sw_xoff_t;

/**
 * cvmx_pko_l4_sq#_topology
 */
union cvmx_pko_l4_sqx_topology {
        u64 u64;
        struct cvmx_pko_l4_sqx_topology_s {
                u64 reserved_42_63 : 22;
                u64 prio_anchor : 10;
                u64 reserved_25_31 : 7;
                u64 parent : 9;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l4_sqx_topology_s cn78xx;
        struct cvmx_pko_l4_sqx_topology_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_topology cvmx_pko_l4_sqx_topology_t;

/**
 * cvmx_pko_l4_sq#_yellow
 *
 * This register has the same bit fields as PKO_L3_SQ()_YELLOW.
 *
 */
union cvmx_pko_l4_sqx_yellow {
        u64 u64;
        struct cvmx_pko_l4_sqx_yellow_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l4_sqx_yellow_s cn78xx;
        struct cvmx_pko_l4_sqx_yellow_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqx_yellow cvmx_pko_l4_sqx_yellow_t;

/**
 * cvmx_pko_l4_sq_csr_bus_debug
 */
union cvmx_pko_l4_sq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_l4_sq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xxp1;
};

typedef union cvmx_pko_l4_sq_csr_bus_debug cvmx_pko_l4_sq_csr_bus_debug_t;

/**
 * cvmx_pko_l4_sqa_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l4_sqa_debug {
        u64 u64;
        struct cvmx_pko_l4_sqa_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l4_sqa_debug_s cn78xx;
        struct cvmx_pko_l4_sqa_debug_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqa_debug cvmx_pko_l4_sqa_debug_t;

/**
 * cvmx_pko_l4_sqb_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l4_sqb_debug {
        u64 u64;
        struct cvmx_pko_l4_sqb_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l4_sqb_debug_s cn78xx;
        struct cvmx_pko_l4_sqb_debug_s cn78xxp1;
};

typedef union cvmx_pko_l4_sqb_debug cvmx_pko_l4_sqb_debug_t;

/**
 * cvmx_pko_l5_sq#_cir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l5_sqx_cir {
        u64 u64;
        struct cvmx_pko_l5_sqx_cir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l5_sqx_cir_s cn78xx;
        struct cvmx_pko_l5_sqx_cir_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_cir cvmx_pko_l5_sqx_cir_t;

/**
 * cvmx_pko_l5_sq#_green
 *
 * This register has the same bit fields as PKO_L3_SQ()_GREEN.
 *
 */
union cvmx_pko_l5_sqx_green {
        u64 u64;
        struct cvmx_pko_l5_sqx_green_s {
                u64 reserved_41_63 : 23;
                u64 rr_active : 1;
                u64 active_vec : 20;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l5_sqx_green_s cn78xx;
        struct cvmx_pko_l5_sqx_green_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_green cvmx_pko_l5_sqx_green_t;

/**
 * cvmx_pko_l5_sq#_pick
 *
 * This CSR contains the meta for the L5 SQ, and is for debug and reconfiguration
 * only and should never be written. See also PKO_META_DESC_S.
 */
union cvmx_pko_l5_sqx_pick {
        u64 u64;
        struct cvmx_pko_l5_sqx_pick_s {
                u64 dq : 10;
                u64 color : 2;
                u64 child : 10;
                u64 bubble : 1;
                u64 p_con : 1;
                u64 c_con : 1;
                u64 uid : 7;
                u64 jump : 1;
                u64 fpd : 1;
                u64 ds : 1;
                u64 adjust : 9;
                u64 pir_dis : 1;
                u64 cir_dis : 1;
                u64 red_algo_override : 2;
                u64 length : 16;
        } s;
        struct cvmx_pko_l5_sqx_pick_s cn78xx;
        struct cvmx_pko_l5_sqx_pick_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_pick cvmx_pko_l5_sqx_pick_t;

/**
 * cvmx_pko_l5_sq#_pir
 *
 * This register has the same bit fields as PKO_L1_SQ()_CIR.
 *
 */
union cvmx_pko_l5_sqx_pir {
        u64 u64;
        struct cvmx_pko_l5_sqx_pir_s {
                u64 reserved_41_63 : 23;
                u64 burst_exponent : 4;
                u64 burst_mantissa : 8;
                u64 reserved_17_28 : 12;
                u64 rate_divider_exponent : 4;
                u64 rate_exponent : 4;
                u64 rate_mantissa : 8;
                u64 enable : 1;
        } s;
        struct cvmx_pko_l5_sqx_pir_s cn78xx;
        struct cvmx_pko_l5_sqx_pir_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_pir cvmx_pko_l5_sqx_pir_t;

/**
 * cvmx_pko_l5_sq#_pointers
 *
 * This register has the same bit fields as PKO_L4_SQ()_POINTERS.
 *
 */
union cvmx_pko_l5_sqx_pointers {
        u64 u64;
        struct cvmx_pko_l5_sqx_pointers_s {
                u64 reserved_26_63 : 38;
                u64 prev : 10;
                u64 reserved_10_15 : 6;
                u64 next : 10;
        } s;
        struct cvmx_pko_l5_sqx_pointers_s cn78xx;
        struct cvmx_pko_l5_sqx_pointers_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_pointers cvmx_pko_l5_sqx_pointers_t;

/**
 * cvmx_pko_l5_sq#_red
 *
 * This register has the same bit fields as PKO_L3_SQ()_YELLOW.
 *
 */
union cvmx_pko_l5_sqx_red {
        u64 u64;
        struct cvmx_pko_l5_sqx_red_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l5_sqx_red_s cn78xx;
        struct cvmx_pko_l5_sqx_red_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_red cvmx_pko_l5_sqx_red_t;

/**
 * cvmx_pko_l5_sq#_sched_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE.
 *
 */
union cvmx_pko_l5_sqx_sched_state {
        u64 u64;
        struct cvmx_pko_l5_sqx_sched_state_s {
                u64 reserved_25_63 : 39;
                u64 rr_count : 25;
        } s;
        struct cvmx_pko_l5_sqx_sched_state_s cn78xx;
        struct cvmx_pko_l5_sqx_sched_state_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_sched_state cvmx_pko_l5_sqx_sched_state_t;

/**
 * cvmx_pko_l5_sq#_schedule
 *
 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE.
 *
 */
union cvmx_pko_l5_sqx_schedule {
        u64 u64;
        struct cvmx_pko_l5_sqx_schedule_s {
                u64 reserved_28_63 : 36;
                u64 prio : 4;
                u64 rr_quantum : 24;
        } s;
        struct cvmx_pko_l5_sqx_schedule_s cn78xx;
        struct cvmx_pko_l5_sqx_schedule_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_schedule cvmx_pko_l5_sqx_schedule_t;

/**
 * cvmx_pko_l5_sq#_shape
 */
union cvmx_pko_l5_sqx_shape {
        u64 u64;
        struct cvmx_pko_l5_sqx_shape_s {
                u64 reserved_25_63 : 39;
                u64 length_disable : 1;
                u64 reserved_13_23 : 11;
                u64 yellow_disable : 1;
                u64 red_disable : 1;
                u64 red_algo : 2;
                u64 adjust : 9;
        } s;
        struct cvmx_pko_l5_sqx_shape_s cn78xx;
        struct cvmx_pko_l5_sqx_shape_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_shape cvmx_pko_l5_sqx_shape_t;

/**
 * cvmx_pko_l5_sq#_shape_state
 *
 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE.
 * This register must not be written during normal operation.
 */
union cvmx_pko_l5_sqx_shape_state {
        u64 u64;
        struct cvmx_pko_l5_sqx_shape_state_s {
                u64 reserved_60_63 : 4;
                u64 tw_timestamp : 6;
                u64 color : 2;
                u64 pir_accum : 26;
                u64 cir_accum : 26;
        } s;
        struct cvmx_pko_l5_sqx_shape_state_s cn78xx;
        struct cvmx_pko_l5_sqx_shape_state_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_shape_state cvmx_pko_l5_sqx_shape_state_t;

/**
 * cvmx_pko_l5_sq#_sw_xoff
 *
 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF.
 *
 */
union cvmx_pko_l5_sqx_sw_xoff {
        u64 u64;
        struct cvmx_pko_l5_sqx_sw_xoff_s {
                u64 reserved_4_63 : 60;
                u64 drain_irq : 1;
                u64 drain_null_link : 1;
                u64 drain : 1;
                u64 xoff : 1;
        } s;
        struct cvmx_pko_l5_sqx_sw_xoff_s cn78xx;
        struct cvmx_pko_l5_sqx_sw_xoff_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_sw_xoff cvmx_pko_l5_sqx_sw_xoff_t;

/**
 * cvmx_pko_l5_sq#_topology
 */
union cvmx_pko_l5_sqx_topology {
        u64 u64;
        struct cvmx_pko_l5_sqx_topology_s {
                u64 reserved_42_63 : 22;
                u64 prio_anchor : 10;
                u64 reserved_26_31 : 6;
                u64 parent : 10;
                u64 reserved_5_15 : 11;
                u64 rr_prio : 4;
                u64 reserved_0_0 : 1;
        } s;
        struct cvmx_pko_l5_sqx_topology_s cn78xx;
        struct cvmx_pko_l5_sqx_topology_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_topology cvmx_pko_l5_sqx_topology_t;

/**
 * cvmx_pko_l5_sq#_yellow
 *
 * This register has the same bit fields as PKO_L3_SQ()_YELLOW.
 *
 */
union cvmx_pko_l5_sqx_yellow {
        u64 u64;
        struct cvmx_pko_l5_sqx_yellow_s {
                u64 reserved_20_63 : 44;
                u64 head : 10;
                u64 tail : 10;
        } s;
        struct cvmx_pko_l5_sqx_yellow_s cn78xx;
        struct cvmx_pko_l5_sqx_yellow_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqx_yellow cvmx_pko_l5_sqx_yellow_t;

/**
 * cvmx_pko_l5_sq_csr_bus_debug
 */
union cvmx_pko_l5_sq_csr_bus_debug {
        u64 u64;
        struct cvmx_pko_l5_sq_csr_bus_debug_s {
                u64 csr_bus_debug : 64;
        } s;
        struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xx;
        struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xxp1;
};

typedef union cvmx_pko_l5_sq_csr_bus_debug cvmx_pko_l5_sq_csr_bus_debug_t;

/**
 * cvmx_pko_l5_sqa_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l5_sqa_debug {
        u64 u64;
        struct cvmx_pko_l5_sqa_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l5_sqa_debug_s cn78xx;
        struct cvmx_pko_l5_sqa_debug_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqa_debug cvmx_pko_l5_sqa_debug_t;

/**
 * cvmx_pko_l5_sqb_debug
 *
 * This register has the same bit fields as PKO_PQA_DEBUG.
 *
 */
union cvmx_pko_l5_sqb_debug {
        u64 u64;
        struct cvmx_pko_l5_sqb_debug_s {
                u64 dbg_vec : 64;
        } s;
        struct cvmx_pko_l5_sqb_debug_s cn78xx;
        struct cvmx_pko_l5_sqb_debug_s cn78xxp1;
};

typedef union cvmx_pko_l5_sqb_debug cvmx_pko_l5_sqb_debug_t;

/**
 * cvmx_pko_lut#
 *
 * PKO_LUT has a location for each used PKI_CHAN_E. The following table
 * shows the mapping between LINK/MAC_NUM's, PKI_CHAN_E channels, and
 * PKO_LUT indices.
 *
 * <pre>
 *   LINK/   PKI_CHAN_E    Corresponding
 * MAC_NUM   Range         PKO_LUT index   Description
 * -------   -----------   -------------   -----------------
 *     0     0x000-0x03F   0x040-0x07F     LBK Loopback
 *     1     0x100-0x13F   0x080-0x0BF     DPI packet output
 *     2     0x800-0x80F   0x000-0x00F     BGX0 Logical MAC 0
 *     3     0x810-0x81F   0x010-0x01F     BGX0 Logical MAC 1
 *     4     0x820-0x82F   0x020-0x02F     BGX0 Logical MAC 2
 *     5     0x830-0x83F   0x030-0x03F     BGX0 Logical MAC 3
 * </pre>
 */
union cvmx_pko_lutx {
        u64 u64;
        struct cvmx_pko_lutx_s {
                u64 reserved_16_63 : 48;
                u64 valid : 1;
                u64 reserved_14_14 : 1;
                u64 pq_idx : 5;
                u64 queue_number : 9;
        } s;
        struct cvmx_pko_lutx_cn73xx {
                u64 reserved_16_63 : 48;
                u64 valid : 1;
                u64 reserved_13_14 : 2;
                u64 pq_idx : 4;
                u64 reserved_8_8 : 1;
                u64 queue_number : 8;
        } cn73xx;
        struct cvmx_pko_lutx_s cn78xx;
        struct cvmx_pko_lutx_s cn78xxp1;
        struct cvmx_pko_lutx_cn73xx cnf75xx;
};

typedef union cvmx_pko_lutx cvmx_pko_lutx_t;

/**
 * cvmx_pko_lut_bist_status
 */
union cvmx_pko_lut_bist_status {
        u64 u64;
        struct cvmx_pko_lut_bist_status_s {
                u64 reserved_1_63 : 63;
                u64 bist_status : 1;
        } s;
        struct cvmx_pko_lut_bist_status_s cn73xx;
        struct cvmx_pko_lut_bist_status_s cn78xx;
        struct cvmx_pko_lut_bist_status_s cn78xxp1;
        struct cvmx_pko_lut_bist_status_s cnf75xx;
};

typedef union cvmx_pko_lut_bist_status cvmx_pko_lut_bist_status_t;

/**
 * cvmx_pko_lut_ecc_ctl0
 */
union cvmx_pko_lut_ecc_ctl0 {
        u64 u64;
        struct cvmx_pko_lut_ecc_ctl0_s {
                u64 c2q_lut_ram_flip : 2;
                u64 c2q_lut_ram_cdis : 1;
                u64 reserved_0_60 : 61;
        } s;

        struct cvmx_pko_lut_ecc_ctl0_s cn73xx;
        struct cvmx_pko_lut_ecc_ctl0_s cn78xx;
        struct cvmx_pko_lut_ecc_ctl0_s cn78xxp1;
        struct cvmx_pko_lut_ecc_ctl0_s cnf75xx;
};

typedef union cvmx_pko_lut_ecc_ctl0 cvmx_pko_lut_ecc_ctl0_t;

/**
 * cvmx_pko_lut_ecc_dbe_sts0
 */
union cvmx_pko_lut_ecc_dbe_sts0 {
        u64 u64;
        struct cvmx_pko_lut_ecc_dbe_sts0_s {
                u64 c2q_lut_ram_dbe : 1;
                u64 reserved_0_62 : 63;
        } s;
        struct cvmx_pko_lut_ecc_dbe_sts0_s cn73xx;
        struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xx;
        struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xxp1;
        struct cvmx_pko_lut_ecc_dbe_sts0_s cnf75xx;
};

typedef union cvmx_pko_lut_ecc_dbe_sts0 cvmx_pko_lut_ecc_dbe_sts0_t;

/**
 * cvmx_pko_lut_ecc_dbe_sts_cmb0
 */
union cvmx_pko_lut_ecc_dbe_sts_cmb0 {
        u64 u64;
        struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s {
                u64 lut_dbe_cmb0 : 1;
                u64 reserved_0_62 : 63;
        } s;
        struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn73xx;
        struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xx;
        struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xxp1;
        struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cnf75xx;
};

typedef union cvmx_pko_lut_ecc_dbe_sts_cmb0 cvmx_pko_lut_ecc_dbe_sts_cmb0_t;

/**
 * cvmx_pko_lut_ecc_sbe_sts0
 */
union cvmx_pko_lut_ecc_sbe_sts0 {
        u64 u64;
        struct cvmx_pko_lut_ecc_sbe_sts0_s {
                u64 c2q_lut_ram_sbe : 1;
                u64 reserved_0_62 : 63;
        } s;
        struct cvmx_pko_lut_ecc_sbe_sts0_s cn73xx;
        struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xx;
        struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xxp1;
        struct cvmx_pko_lut_ecc_sbe_sts0_s cnf75xx;
};

typedef union cvmx_pko_lut_ecc_sbe_sts0 cvmx_pko_lut_ecc_sbe_sts0_t;

/**
 * cvmx_pko_lut_ecc_sbe_sts_cmb0
 */
union cvmx_pko_lut_ecc_sbe_sts_cmb0 {
        u64 u64;
        struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s {
                u64 lut_sbe_cmb0 : 1;
                u64 reserved_0_62 : 63;
        } s;
        struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn73xx;
        struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xx;
        struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xxp1;
        struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cnf75xx;
};

typedef union cvmx_pko_lut_ecc_sbe_sts_cmb0 cvmx_pko_lut_ecc_sbe_sts_cmb0_t;

/**
 * cvmx_pko_mac#_cfg
 *
 * These registers create the links between the MACs and the TxFIFO used to store the data,
 * and hold the per-MAC configuration bits.  These registers must be disabled (FIFO_NUM set
 * to 31) prior to reconfiguration of any of the other bits.
 *
 * <pre>
 *   CSR Name       Associated MAC
 *   ------------   -------------------
 *   PKO_MAC0_CFG   LBK loopback
 *   PKO_MAC1_CFG   DPI packet output
 *   PKO_MAC2_CFG   BGX0  logical MAC 0
 *   PKO_MAC3_CFG   BGX0  logical MAC 1
 *   PKO_MAC4_CFG   BGX0  logical MAC 2
 *   PKO_MAC5_CFG   BGX0  logical MAC 3
 *   PKO_MAC6_CFG   SRIO0 logical MAC 0
 *   PKO_MAC7_CFG   SRIO0 logical MAC 1
 *   PKO_MAC8_CFG   SRIO1 logical MAC 0
 *   PKO_MAC9_CFG   SRIO1 logical MAC 1
 * </pre>
 */
union cvmx_pko_macx_cfg {
        u64 u64;
        struct cvmx_pko_macx_cfg_s {
                u64 reserved_17_63 : 47;
                u64 min_pad_ena : 1;
                u64 fcs_ena : 1;
                u64 fcs_sop_off : 8;
                u64 skid_max_cnt : 2;
                u64 fifo_num : 5;
        } s;
        struct cvmx_pko_macx_cfg_s cn73xx;
        struct cvmx_pko_macx_cfg_s cn78xx;
        struct cvmx_pko_macx_cfg_s cn78xxp1;
        struct cvmx_pko_macx_cfg_s cnf75xx;
};

typedef union cvmx_pko_macx_cfg cvmx_pko_macx_cfg_t;

/**
 * cvmx_pko_mci0_cred_cnt#
 */
union cvmx_pko_mci0_cred_cntx {
        u64 u64;
        struct cvmx_pko_mci0_cred_cntx_s {
                u64 reserved_13_63 : 51;
                u64 cred_cnt : 13;
        } s;
        struct cvmx_pko_mci0_cred_cntx_s cn78xx;
        struct cvmx_pko_mci0_cred_cntx_s cn78xxp1;
};

typedef union cvmx_pko_mci0_cred_cntx cvmx_pko_mci0_cred_cntx_t;

/**
 * cvmx_pko_mci0_max_cred#
 */
union cvmx_pko_mci0_max_credx {
        u64 u64;
        struct cvmx_pko_mci0_max_credx_s {
                u64 reserved_12_63 : 52;
                u64 max_cred_lim : 12;
        } s;
        struct cvmx_pko_mci0_max_credx_s cn78xx;
        struct cvmx_pko_mci0_max_credx_s cn78xxp1;
};

typedef union cvmx_pko_mci0_max_credx cvmx_pko_mci0_max_credx_t;

/**
 * cvmx_pko_mci1_cred_cnt#
 */
union cvmx_pko_mci1_cred_cntx {
        u64 u64;
        struct cvmx_pko_mci1_cred_cntx_s {
                u64 reserved_13_63 : 51;
                u64 cred_cnt : 13;
        } s;
        struct cvmx_pko_mci1_cred_cntx_s cn73xx;
        struct cvmx_pko_mci1_cred_cntx_s cn78xx;
        struct cvmx_pko_mci1_cred_cntx_s cn78xxp1;
        struct cvmx_pko_mci1_cred_cntx_s cnf75xx;
};

typedef union cvmx_pko_mci1_cred_cntx cvmx_pko_mci1_cred_cntx_t;

/**
 * cvmx_pko_mci1_max_cred#
 */
union cvmx_pko_mci1_max_credx {
        u64 u64;
        struct cvmx_pko_mci1_max_credx_s {
                u64 reserved_12_63 : 52;
                u64 max_cred_lim : 12;
        } s;
        struct cvmx_pko_mci1_max_credx_s cn73xx;
        struct cvmx_pko_mci1_max_credx_s cn78xx;
        struct cvmx_pko_mci1_max_credx_s cn78xxp1;
        struct cvmx_pko_mci1_max_credx_s cnf75xx;
};

typedef union cvmx_pko_mci1_max_credx cvmx_pko_mci1_max_credx_t;

/**
 * cvmx_pko_mem_count0
 *
 * Notes:
 * Total number of packets seen by PKO, per port
 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_count0 {
        u64 u64;
        struct cvmx_pko_mem_count0_s {
                u64 reserved_32_63 : 32;
                u64 count : 32;
        } s;
        struct cvmx_pko_mem_count0_s cn30xx;
        struct cvmx_pko_mem_count0_s cn31xx;
        struct cvmx_pko_mem_count0_s cn38xx;
        struct cvmx_pko_mem_count0_s cn38xxp2;
        struct cvmx_pko_mem_count0_s cn50xx;
        struct cvmx_pko_mem_count0_s cn52xx;
        struct cvmx_pko_mem_count0_s cn52xxp1;
        struct cvmx_pko_mem_count0_s cn56xx;
        struct cvmx_pko_mem_count0_s cn56xxp1;
        struct cvmx_pko_mem_count0_s cn58xx;
        struct cvmx_pko_mem_count0_s cn58xxp1;
        struct cvmx_pko_mem_count0_s cn61xx;
        struct cvmx_pko_mem_count0_s cn63xx;
        struct cvmx_pko_mem_count0_s cn63xxp1;
        struct cvmx_pko_mem_count0_s cn66xx;
        struct cvmx_pko_mem_count0_s cn68xx;
        struct cvmx_pko_mem_count0_s cn68xxp1;
        struct cvmx_pko_mem_count0_s cn70xx;
        struct cvmx_pko_mem_count0_s cn70xxp1;
        struct cvmx_pko_mem_count0_s cnf71xx;
};

typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;

/**
 * cvmx_pko_mem_count1
 *
 * Notes:
 * Total number of bytes seen by PKO, per port
 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_count1 {
        u64 u64;
        struct cvmx_pko_mem_count1_s {
                u64 reserved_48_63 : 16;
                u64 count : 48;
        } s;
        struct cvmx_pko_mem_count1_s cn30xx;
        struct cvmx_pko_mem_count1_s cn31xx;
        struct cvmx_pko_mem_count1_s cn38xx;
        struct cvmx_pko_mem_count1_s cn38xxp2;
        struct cvmx_pko_mem_count1_s cn50xx;
        struct cvmx_pko_mem_count1_s cn52xx;
        struct cvmx_pko_mem_count1_s cn52xxp1;
        struct cvmx_pko_mem_count1_s cn56xx;
        struct cvmx_pko_mem_count1_s cn56xxp1;
        struct cvmx_pko_mem_count1_s cn58xx;
        struct cvmx_pko_mem_count1_s cn58xxp1;
        struct cvmx_pko_mem_count1_s cn61xx;
        struct cvmx_pko_mem_count1_s cn63xx;
        struct cvmx_pko_mem_count1_s cn63xxp1;
        struct cvmx_pko_mem_count1_s cn66xx;
        struct cvmx_pko_mem_count1_s cn68xx;
        struct cvmx_pko_mem_count1_s cn68xxp1;
        struct cvmx_pko_mem_count1_s cn70xx;
        struct cvmx_pko_mem_count1_s cn70xxp1;
        struct cvmx_pko_mem_count1_s cnf71xx;
};

typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;

/**
 * cvmx_pko_mem_debug0
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug0 {
        u64 u64;
        struct cvmx_pko_mem_debug0_s {
                u64 fau : 28;
                u64 cmd : 14;
                u64 segs : 6;
                u64 size : 16;
        } s;
        struct cvmx_pko_mem_debug0_s cn30xx;
        struct cvmx_pko_mem_debug0_s cn31xx;
        struct cvmx_pko_mem_debug0_s cn38xx;
        struct cvmx_pko_mem_debug0_s cn38xxp2;
        struct cvmx_pko_mem_debug0_s cn50xx;
        struct cvmx_pko_mem_debug0_s cn52xx;
        struct cvmx_pko_mem_debug0_s cn52xxp1;
        struct cvmx_pko_mem_debug0_s cn56xx;
        struct cvmx_pko_mem_debug0_s cn56xxp1;
        struct cvmx_pko_mem_debug0_s cn58xx;
        struct cvmx_pko_mem_debug0_s cn58xxp1;
        struct cvmx_pko_mem_debug0_s cn61xx;
        struct cvmx_pko_mem_debug0_s cn63xx;
        struct cvmx_pko_mem_debug0_s cn63xxp1;
        struct cvmx_pko_mem_debug0_s cn66xx;
        struct cvmx_pko_mem_debug0_s cn68xx;
        struct cvmx_pko_mem_debug0_s cn68xxp1;
        struct cvmx_pko_mem_debug0_s cn70xx;
        struct cvmx_pko_mem_debug0_s cn70xxp1;
        struct cvmx_pko_mem_debug0_s cnf71xx;
};

typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;

/**
 * cvmx_pko_mem_debug1
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug1 {
        u64 u64;
        struct cvmx_pko_mem_debug1_s {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 ptr : 40;
        } s;
        struct cvmx_pko_mem_debug1_s cn30xx;
        struct cvmx_pko_mem_debug1_s cn31xx;
        struct cvmx_pko_mem_debug1_s cn38xx;
        struct cvmx_pko_mem_debug1_s cn38xxp2;
        struct cvmx_pko_mem_debug1_s cn50xx;
        struct cvmx_pko_mem_debug1_s cn52xx;
        struct cvmx_pko_mem_debug1_s cn52xxp1;
        struct cvmx_pko_mem_debug1_s cn56xx;
        struct cvmx_pko_mem_debug1_s cn56xxp1;
        struct cvmx_pko_mem_debug1_s cn58xx;
        struct cvmx_pko_mem_debug1_s cn58xxp1;
        struct cvmx_pko_mem_debug1_s cn61xx;
        struct cvmx_pko_mem_debug1_s cn63xx;
        struct cvmx_pko_mem_debug1_s cn63xxp1;
        struct cvmx_pko_mem_debug1_s cn66xx;
        struct cvmx_pko_mem_debug1_s cn68xx;
        struct cvmx_pko_mem_debug1_s cn68xxp1;
        struct cvmx_pko_mem_debug1_s cn70xx;
        struct cvmx_pko_mem_debug1_s cn70xxp1;
        struct cvmx_pko_mem_debug1_s cnf71xx;
};

typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;

/**
 * cvmx_pko_mem_debug10
 *
 * Notes:
 * Internal per-engine state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
 * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug10 {
        u64 u64;
        struct cvmx_pko_mem_debug10_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug10_cn30xx {
                u64 fau : 28;
                u64 cmd : 14;
                u64 segs : 6;
                u64 size : 16;
        } cn30xx;
        struct cvmx_pko_mem_debug10_cn30xx cn31xx;
        struct cvmx_pko_mem_debug10_cn30xx cn38xx;
        struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug10_cn50xx {
                u64 reserved_49_63 : 15;
                u64 ptrs1 : 17;
                u64 reserved_17_31 : 15;
                u64 ptrs2 : 17;
        } cn50xx;
        struct cvmx_pko_mem_debug10_cn50xx cn52xx;
        struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cn56xx;
        struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cn58xx;
        struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cn61xx;
        struct cvmx_pko_mem_debug10_cn50xx cn63xx;
        struct cvmx_pko_mem_debug10_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cn66xx;
        struct cvmx_pko_mem_debug10_cn50xx cn68xx;
        struct cvmx_pko_mem_debug10_cn50xx cn68xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cn70xx;
        struct cvmx_pko_mem_debug10_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug10_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;

/**
 * cvmx_pko_mem_debug11
 *
 * Notes:
 * Internal per-engine state intended for debug use only - pko.out.sta.state[22:0]
 * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug11 {
        u64 u64;
        struct cvmx_pko_mem_debug11_s {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 reserved_0_39 : 40;
        } s;
        struct cvmx_pko_mem_debug11_cn30xx {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 ptr : 40;
        } cn30xx;
        struct cvmx_pko_mem_debug11_cn30xx cn31xx;
        struct cvmx_pko_mem_debug11_cn30xx cn38xx;
        struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug11_cn50xx {
                u64 reserved_23_63 : 41;
                u64 maj : 1;
                u64 uid : 3;
                u64 sop : 1;
                u64 len : 1;
                u64 chk : 1;
                u64 cnt : 13;
                u64 mod : 3;
        } cn50xx;
        struct cvmx_pko_mem_debug11_cn50xx cn52xx;
        struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cn56xx;
        struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cn58xx;
        struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cn61xx;
        struct cvmx_pko_mem_debug11_cn50xx cn63xx;
        struct cvmx_pko_mem_debug11_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cn66xx;
        struct cvmx_pko_mem_debug11_cn50xx cn68xx;
        struct cvmx_pko_mem_debug11_cn50xx cn68xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cn70xx;
        struct cvmx_pko_mem_debug11_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug11_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;

/**
 * cvmx_pko_mem_debug12
 *
 * Notes:
 * Internal per-engine x4 state intended for debug use only - pko.out.ctl.cmnd[63:0]
 * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug12 {
        u64 u64;
        struct cvmx_pko_mem_debug12_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug12_cn30xx {
                u64 data : 64;
        } cn30xx;
        struct cvmx_pko_mem_debug12_cn30xx cn31xx;
        struct cvmx_pko_mem_debug12_cn30xx cn38xx;
        struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug12_cn50xx {
                u64 fau : 28;
                u64 cmd : 14;
                u64 segs : 6;
                u64 size : 16;
        } cn50xx;
        struct cvmx_pko_mem_debug12_cn50xx cn52xx;
        struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cn56xx;
        struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cn58xx;
        struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cn61xx;
        struct cvmx_pko_mem_debug12_cn50xx cn63xx;
        struct cvmx_pko_mem_debug12_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cn66xx;
        struct cvmx_pko_mem_debug12_cn68xx {
                u64 state : 64;
        } cn68xx;
        struct cvmx_pko_mem_debug12_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cn70xx;
        struct cvmx_pko_mem_debug12_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug12_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;

/**
 * cvmx_pko_mem_debug13
 *
 * Notes:
 * Internal per-engine x4 state intended for debug use only - pko.out.ctl.head[63:0]
 * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug13 {
        u64 u64;
        struct cvmx_pko_mem_debug13_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug13_cn30xx {
                u64 reserved_51_63 : 13;
                u64 widx : 17;
                u64 ridx2 : 17;
                u64 widx2 : 17;
        } cn30xx;
        struct cvmx_pko_mem_debug13_cn30xx cn31xx;
        struct cvmx_pko_mem_debug13_cn30xx cn38xx;
        struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug13_cn50xx {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 ptr : 40;
        } cn50xx;
        struct cvmx_pko_mem_debug13_cn50xx cn52xx;
        struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cn56xx;
        struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cn58xx;
        struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cn61xx;
        struct cvmx_pko_mem_debug13_cn50xx cn63xx;
        struct cvmx_pko_mem_debug13_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cn66xx;
        struct cvmx_pko_mem_debug13_cn68xx {
                u64 state : 64;
        } cn68xx;
        struct cvmx_pko_mem_debug13_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cn70xx;
        struct cvmx_pko_mem_debug13_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug13_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;

/**
 * cvmx_pko_mem_debug14
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
 * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug14 {
        u64 u64;
        struct cvmx_pko_mem_debug14_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug14_cn30xx {
                u64 reserved_17_63 : 47;
                u64 ridx : 17;
        } cn30xx;
        struct cvmx_pko_mem_debug14_cn30xx cn31xx;
        struct cvmx_pko_mem_debug14_cn30xx cn38xx;
        struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug14_cn52xx {
                u64 data : 64;
        } cn52xx;
        struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
        struct cvmx_pko_mem_debug14_cn52xx cn56xx;
        struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
        struct cvmx_pko_mem_debug14_cn52xx cn61xx;
        struct cvmx_pko_mem_debug14_cn52xx cn63xx;
        struct cvmx_pko_mem_debug14_cn52xx cn63xxp1;
        struct cvmx_pko_mem_debug14_cn52xx cn66xx;
        struct cvmx_pko_mem_debug14_cn52xx cn70xx;
        struct cvmx_pko_mem_debug14_cn52xx cn70xxp1;
        struct cvmx_pko_mem_debug14_cn52xx cnf71xx;
};

typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;

/**
 * cvmx_pko_mem_debug2
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug2 {
        u64 u64;
        struct cvmx_pko_mem_debug2_s {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 ptr : 40;
        } s;
        struct cvmx_pko_mem_debug2_s cn30xx;
        struct cvmx_pko_mem_debug2_s cn31xx;
        struct cvmx_pko_mem_debug2_s cn38xx;
        struct cvmx_pko_mem_debug2_s cn38xxp2;
        struct cvmx_pko_mem_debug2_s cn50xx;
        struct cvmx_pko_mem_debug2_s cn52xx;
        struct cvmx_pko_mem_debug2_s cn52xxp1;
        struct cvmx_pko_mem_debug2_s cn56xx;
        struct cvmx_pko_mem_debug2_s cn56xxp1;
        struct cvmx_pko_mem_debug2_s cn58xx;
        struct cvmx_pko_mem_debug2_s cn58xxp1;
        struct cvmx_pko_mem_debug2_s cn61xx;
        struct cvmx_pko_mem_debug2_s cn63xx;
        struct cvmx_pko_mem_debug2_s cn63xxp1;
        struct cvmx_pko_mem_debug2_s cn66xx;
        struct cvmx_pko_mem_debug2_s cn68xx;
        struct cvmx_pko_mem_debug2_s cn68xxp1;
        struct cvmx_pko_mem_debug2_s cn70xx;
        struct cvmx_pko_mem_debug2_s cn70xxp1;
        struct cvmx_pko_mem_debug2_s cnf71xx;
};

typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;

/**
 * cvmx_pko_mem_debug3
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug3 {
        u64 u64;
        struct cvmx_pko_mem_debug3_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug3_cn30xx {
                u64 i : 1;
                u64 back : 4;
                u64 pool : 3;
                u64 size : 16;
                u64 ptr : 40;
        } cn30xx;
        struct cvmx_pko_mem_debug3_cn30xx cn31xx;
        struct cvmx_pko_mem_debug3_cn30xx cn38xx;
        struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug3_cn50xx {
                u64 data : 64;
        } cn50xx;
        struct cvmx_pko_mem_debug3_cn50xx cn52xx;
        struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cn56xx;
        struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cn58xx;
        struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cn61xx;
        struct cvmx_pko_mem_debug3_cn50xx cn63xx;
        struct cvmx_pko_mem_debug3_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cn66xx;
        struct cvmx_pko_mem_debug3_cn50xx cn68xx;
        struct cvmx_pko_mem_debug3_cn50xx cn68xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cn70xx;
        struct cvmx_pko_mem_debug3_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug3_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;

/**
 * cvmx_pko_mem_debug4
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug4 {
        u64 u64;
        struct cvmx_pko_mem_debug4_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug4_cn30xx {
                u64 data : 64;
        } cn30xx;
        struct cvmx_pko_mem_debug4_cn30xx cn31xx;
        struct cvmx_pko_mem_debug4_cn30xx cn38xx;
        struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug4_cn50xx {
                u64 cmnd_segs : 3;
                u64 cmnd_siz : 16;
                u64 cmnd_off : 6;
                u64 uid : 3;
                u64 dread_sop : 1;
                u64 init_dwrite : 1;
                u64 chk_once : 1;
                u64 chk_mode : 1;
                u64 active : 1;
                u64 static_p : 1;
                u64 qos : 3;
                u64 qcb_ridx : 5;
                u64 qid_off_max : 4;
                u64 qid_off : 4;
                u64 qid_base : 8;
                u64 wait : 1;
                u64 minor : 2;
                u64 major : 3;
        } cn50xx;
        struct cvmx_pko_mem_debug4_cn52xx {
                u64 curr_siz : 8;
                u64 curr_off : 16;
                u64 cmnd_segs : 6;
                u64 cmnd_siz : 16;
                u64 cmnd_off : 6;
                u64 uid : 2;
                u64 dread_sop : 1;
                u64 init_dwrite : 1;
                u64 chk_once : 1;
                u64 chk_mode : 1;
                u64 wait : 1;
                u64 minor : 2;
                u64 major : 3;
        } cn52xx;
        struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
        struct cvmx_pko_mem_debug4_cn52xx cn56xx;
        struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
        struct cvmx_pko_mem_debug4_cn50xx cn58xx;
        struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug4_cn52xx cn61xx;
        struct cvmx_pko_mem_debug4_cn52xx cn63xx;
        struct cvmx_pko_mem_debug4_cn52xx cn63xxp1;
        struct cvmx_pko_mem_debug4_cn52xx cn66xx;
        struct cvmx_pko_mem_debug4_cn68xx {
                u64 curr_siz : 9;
                u64 curr_off : 16;
                u64 cmnd_segs : 6;
                u64 cmnd_siz : 16;
                u64 cmnd_off : 6;
                u64 dread_sop : 1;
                u64 init_dwrite : 1;
                u64 chk_once : 1;
                u64 chk_mode : 1;
                u64 reserved_6_6 : 1;
                u64 minor : 2;
                u64 major : 4;
        } cn68xx;
        struct cvmx_pko_mem_debug4_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug4_cn52xx cn70xx;
        struct cvmx_pko_mem_debug4_cn52xx cn70xxp1;
        struct cvmx_pko_mem_debug4_cn52xx cnf71xx;
};

typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;

/**
 * cvmx_pko_mem_debug5
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug5 {
        u64 u64;
        struct cvmx_pko_mem_debug5_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug5_cn30xx {
                u64 dwri_mod : 1;
                u64 dwri_sop : 1;
                u64 dwri_len : 1;
                u64 dwri_cnt : 13;
                u64 cmnd_siz : 16;
                u64 uid : 1;
                u64 xfer_wor : 1;
                u64 xfer_dwr : 1;
                u64 cbuf_fre : 1;
                u64 reserved_27_27 : 1;
                u64 chk_mode : 1;
                u64 active : 1;
                u64 qos : 3;
                u64 qcb_ridx : 5;
                u64 qid_off : 3;
                u64 qid_base : 7;
                u64 wait : 1;
                u64 minor : 2;
                u64 major : 4;
        } cn30xx;
        struct cvmx_pko_mem_debug5_cn30xx cn31xx;
        struct cvmx_pko_mem_debug5_cn30xx cn38xx;
        struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug5_cn50xx {
                u64 curr_ptr : 29;
                u64 curr_siz : 16;
                u64 curr_off : 16;
                u64 cmnd_segs : 3;
        } cn50xx;
        struct cvmx_pko_mem_debug5_cn52xx {
                u64 reserved_54_63 : 10;
                u64 nxt_inflt : 6;
                u64 curr_ptr : 40;
                u64 curr_siz : 8;
        } cn52xx;
        struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
        struct cvmx_pko_mem_debug5_cn52xx cn56xx;
        struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
        struct cvmx_pko_mem_debug5_cn50xx cn58xx;
        struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug5_cn61xx {
                u64 reserved_56_63 : 8;
                u64 ptp : 1;
                u64 major_3 : 1;
                u64 nxt_inflt : 6;
                u64 curr_ptr : 40;
                u64 curr_siz : 8;
        } cn61xx;
        struct cvmx_pko_mem_debug5_cn61xx cn63xx;
        struct cvmx_pko_mem_debug5_cn61xx cn63xxp1;
        struct cvmx_pko_mem_debug5_cn61xx cn66xx;
        struct cvmx_pko_mem_debug5_cn68xx {
                u64 reserved_57_63 : 7;
                u64 uid : 3;
                u64 ptp : 1;
                u64 nxt_inflt : 6;
                u64 curr_ptr : 40;
                u64 curr_siz : 7;
        } cn68xx;
        struct cvmx_pko_mem_debug5_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug5_cn61xx cn70xx;
        struct cvmx_pko_mem_debug5_cn61xx cn70xxp1;
        struct cvmx_pko_mem_debug5_cn61xx cnf71xx;
};

typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;

/**
 * cvmx_pko_mem_debug6
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug6 {
        u64 u64;
        struct cvmx_pko_mem_debug6_s {
                u64 reserved_38_63 : 26;
                u64 qos_active : 1;
                u64 reserved_0_36 : 37;
        } s;
        struct cvmx_pko_mem_debug6_cn30xx {
                u64 reserved_11_63 : 53;
                u64 qid_offm : 3;
                u64 static_p : 1;
                u64 work_min : 3;
                u64 dwri_chk : 1;
                u64 dwri_uid : 1;
                u64 dwri_mod : 2;
        } cn30xx;
        struct cvmx_pko_mem_debug6_cn30xx cn31xx;
        struct cvmx_pko_mem_debug6_cn30xx cn38xx;
        struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug6_cn50xx {
                u64 reserved_11_63 : 53;
                u64 curr_ptr : 11;
        } cn50xx;
        struct cvmx_pko_mem_debug6_cn52xx {
                u64 reserved_37_63 : 27;
                u64 qid_offres : 4;
                u64 qid_offths : 4;
                u64 preempter : 1;
                u64 preemptee : 1;
                u64 preempted : 1;
                u64 active : 1;
                u64 statc : 1;
                u64 qos : 3;
                u64 qcb_ridx : 5;
                u64 qid_offmax : 4;
                u64 qid_off : 4;
                u64 qid_base : 8;
        } cn52xx;
        struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
        struct cvmx_pko_mem_debug6_cn52xx cn56xx;
        struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
        struct cvmx_pko_mem_debug6_cn50xx cn58xx;
        struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug6_cn52xx cn61xx;
        struct cvmx_pko_mem_debug6_cn52xx cn63xx;
        struct cvmx_pko_mem_debug6_cn52xx cn63xxp1;
        struct cvmx_pko_mem_debug6_cn52xx cn66xx;
        struct cvmx_pko_mem_debug6_cn68xx {
                u64 reserved_38_63 : 26;
                u64 qos_active : 1;
                u64 qid_offths : 5;
                u64 preempter : 1;
                u64 preemptee : 1;
                u64 active : 1;
                u64 static_p : 1;
                u64 qos : 3;
                u64 qcb_ridx : 7;
                u64 qid_offmax : 5;
                u64 qid_off : 5;
                u64 qid_base : 8;
        } cn68xx;
        struct cvmx_pko_mem_debug6_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug6_cn70xx {
                u64 reserved_63_37 : 27;
                u64 qid_offres : 4;
                u64 qid_offths : 4;
                u64 preempter : 1;
                u64 preemptee : 1;
                u64 preempted : 1;
                u64 active : 1;
                u64 staticb : 1;
                u64 qos : 3;
                u64 qcb_ridx : 5;
                u64 qid_offmax : 4;
                u64 qid_off : 4;
                u64 qid_base : 8;
        } cn70xx;
        struct cvmx_pko_mem_debug6_cn70xx cn70xxp1;
        struct cvmx_pko_mem_debug6_cn52xx cnf71xx;
};

typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;

/**
 * cvmx_pko_mem_debug7
 *
 * Notes:
 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug7 {
        u64 u64;
        struct cvmx_pko_mem_debug7_s {
                u64 reserved_0_63 : 64;
        } s;
        struct cvmx_pko_mem_debug7_cn30xx {
                u64 reserved_58_63 : 6;
                u64 dwb : 9;
                u64 start : 33;
                u64 size : 16;
        } cn30xx;
        struct cvmx_pko_mem_debug7_cn30xx cn31xx;
        struct cvmx_pko_mem_debug7_cn30xx cn38xx;
        struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
        struct cvmx_pko_mem_debug7_cn50xx {
                u64 qos : 5;
                u64 tail : 1;
                u64 buf_siz : 13;
                u64 buf_ptr : 33;
                u64 qcb_widx : 6;
                u64 qcb_ridx : 6;
        } cn50xx;
        struct cvmx_pko_mem_debug7_cn50xx cn52xx;
        struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cn56xx;
        struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cn58xx;
        struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cn61xx;
        struct cvmx_pko_mem_debug7_cn50xx cn63xx;
        struct cvmx_pko_mem_debug7_cn50xx cn63xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cn66xx;
        struct cvmx_pko_mem_debug7_cn68xx {
                u64 buf_siz : 11;
                u64 buf_ptr : 37;
                u64 qcb_widx : 8;
                u64 qcb_ridx : 8;
        } cn68xx;
        struct cvmx_pko_mem_debug7_cn68xx cn68xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cn70xx;
        struct cvmx_pko_mem_debug7_cn50xx cn70xxp1;
        struct cvmx_pko_mem_debug7_cn50xx cnf71xx;
};

typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;

/**
 * cvmx_pko_mem_debug8
 *
 * Notes:
 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug8 {
        u64 u64;
        struct cvmx_pko_mem_debug8_s {
                u64 reserved_59_63 : 5;
                u64 tail : 1;
                u64 reserved_0_57 : 58;
        } s;
        struct cvmx_pko_mem_debug8_cn30xx {
                u64 qos : 5;
                u64 tail : 1;
                u64 buf_siz : 13;
                u64 buf_ptr : 33;
                u64 qcb_widx : 6;
                u64 qcb_ridx : 6;
        } cn30xx;
        struct cvmx_pko_mem_debug8_cn30xx cn31xx;
        struct cvmx_pko_mem_debug8_cn30xx cn38xx;
        struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;