1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 */ 5 6#ifndef __CVMX_SATA_DEFS_H__ 7#define __CVMX_SATA_DEFS_H__ 8 9#define CVMX_SATA_UCTL_CTL (0x000118006C000000ull) 10#define CVMX_SATA_UCTL_SHIM_CFG (0x000118006C0000E8ull) 11#define CVMX_SATA_UCTL_BIST_STATUS (0x000118006C000008ull) 12 13#define CVMX_SATA_UAHC_GBL_PI (0x00016C000000000Cull) 14#define CVMX_SATA_UAHC_GBL_TIMER1MS (0x00016C00000000E0ull) 15#define CVMX_SATA_UAHC_GBL_CAP (0x00016C0000000000ull) 16 17#define CVMX_SATA_UAHC_PX_CMD(offset) (0x00016C0000000118ull + ((offset) & 1) * 128) 18#define CVMX_SATA_UAHC_PX_SCTL(offset) (0x00016C000000012Cull + ((offset) & 1) * 128) 19#define CVMX_SATA_UAHC_PX_SERR(offset) (0x00016C0000000130ull + ((offset) & 1) * 128) 20#define CVMX_SATA_UAHC_PX_IS(offset) (0x00016C0000000110ull + ((offset) & 1) * 128) 21#define CVMX_SATA_UAHC_PX_SSTS(offset) (0x00016C0000000128ull + ((offset) & 1) * 128) 22#define CVMX_SATA_UAHC_PX_TFD(offset) (0x00016C0000000120ull + ((offset) & 1) * 128) 23 24/** 25 * cvmx_sata_uctl_ctl 26 * 27 * This register controls clocks, resets, power, and BIST for the SATA. 28 * 29 * Accessible always. 30 * 31 * Reset by IOI reset. 32 */ 33union cvmx_sata_uctl_ctl { 34 u64 u64; 35 struct cvmx_sata_uctl_ctl_s { 36 u64 clear_bist : 1; 37 u64 start_bist : 1; 38 u64 reserved_31_61 : 31; 39 u64 a_clk_en : 1; 40 u64 a_clk_byp_sel : 1; 41 u64 a_clkdiv_rst : 1; 42 u64 reserved_27_27 : 1; 43 u64 a_clkdiv_sel : 3; 44 u64 reserved_5_23 : 19; 45 u64 csclk_en : 1; 46 u64 reserved_2_3 : 2; 47 u64 sata_uahc_rst : 1; 48 u64 sata_uctl_rst : 1; 49 } s; 50 struct cvmx_sata_uctl_ctl_s cn70xx; 51 struct cvmx_sata_uctl_ctl_s cn70xxp1; 52 struct cvmx_sata_uctl_ctl_s cn73xx; 53}; 54 55typedef union cvmx_sata_uctl_ctl cvmx_sata_uctl_ctl_t; 56 57/** 58 * cvmx_sata_uctl_bist_status 59 * 60 * Results from BIST runs of SATA's memories. 61 * Wait for NDONE==0, then look at defect indication. 62 * 63 * Accessible always. 64 * 65 * Reset by IOI reset. 66 */ 67union cvmx_sata_uctl_bist_status { 68 u64 u64; 69 struct cvmx_sata_uctl_bist_status_s { 70 u64 reserved_42_63 : 22; 71 u64 uctl_xm_r_bist_ndone : 1; 72 u64 uctl_xm_w_bist_ndone : 1; 73 u64 reserved_36_39 : 4; 74 u64 uahc_p0_rxram_bist_ndone : 1; 75 u64 uahc_p1_rxram_bist_ndone : 1; 76 u64 uahc_p0_txram_bist_ndone : 1; 77 u64 uahc_p1_txram_bist_ndone : 1; 78 u64 reserved_10_31 : 22; 79 u64 uctl_xm_r_bist_status : 1; 80 u64 uctl_xm_w_bist_status : 1; 81 u64 reserved_4_7 : 4; 82 u64 uahc_p0_rxram_bist_status : 1; 83 u64 uahc_p1_rxram_bist_status : 1; 84 u64 uahc_p0_txram_bist_status : 1; 85 u64 uahc_p1_txram_bist_status : 1; 86 } s; 87 struct cvmx_sata_uctl_bist_status_s cn70xx; 88 struct cvmx_sata_uctl_bist_status_s cn70xxp1; 89 struct cvmx_sata_uctl_bist_status_s cn73xx; 90}; 91 92typedef union cvmx_sata_uctl_bist_status cvmx_sata_uctl_bist_status_t; 93 94/** 95 * cvmx_sata_uctl_shim_cfg 96 * 97 * This register allows configuration of various shim (UCTL) features. 98 * 99 * Fields XS_NCB_OOB_* are captured when there are no outstanding OOB errors indicated in INTSTAT 100 * and a new OOB error arrives. 101 * 102 * Fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors indicated in INTSTAT 103 * and a new DMA error arrives. 104 * 105 * Accessible only when SATA_UCTL_CTL[A_CLK_EN]. 106 * 107 * Reset by IOI reset or SATA_UCTL_CTL[SATA_UCTL_RST]. 108 */ 109union cvmx_sata_uctl_shim_cfg { 110 u64 u64; 111 struct cvmx_sata_uctl_shim_cfg_s { 112 u64 xs_ncb_oob_wrn : 1; 113 u64 reserved_60_62 : 3; 114 u64 xs_ncb_oob_osrc : 12; 115 u64 xm_bad_dma_wrn : 1; 116 u64 reserved_44_46 : 3; 117 u64 xm_bad_dma_type : 4; 118 u64 reserved_14_39 : 26; 119 u64 dma_read_cmd : 2; 120 u64 reserved_11_11 : 1; 121 u64 dma_write_cmd : 1; 122 u64 dma_endian_mode : 2; 123 u64 reserved_2_7 : 6; 124 u64 csr_endian_mode : 2; 125 } s; 126 struct cvmx_sata_uctl_shim_cfg_cn70xx { 127 u64 xs_ncb_oob_wrn : 1; 128 u64 reserved_57_62 : 6; 129 u64 xs_ncb_oob_osrc : 9; 130 u64 xm_bad_dma_wrn : 1; 131 u64 reserved_44_46 : 3; 132 u64 xm_bad_dma_type : 4; 133 u64 reserved_13_39 : 27; 134 u64 dma_read_cmd : 1; 135 u64 reserved_10_11 : 2; 136 u64 dma_endian_mode : 2; 137 u64 reserved_2_7 : 6; 138 u64 csr_endian_mode : 2; 139 } cn70xx; 140 struct cvmx_sata_uctl_shim_cfg_cn70xx cn70xxp1; 141 struct cvmx_sata_uctl_shim_cfg_s cn73xx; 142}; 143 144typedef union cvmx_sata_uctl_shim_cfg cvmx_sata_uctl_shim_cfg_t; 145 146/** 147 * cvmx_sata_uahc_gbl_cap 148 * 149 * See AHCI specification v1.3 section 3.1 150 * 151 */ 152union cvmx_sata_uahc_gbl_cap { 153 u32 u32; 154 struct cvmx_sata_uahc_gbl_cap_s { 155 u32 s64a : 1; 156 u32 sncq : 1; 157 u32 ssntf : 1; 158 u32 smps : 1; 159 u32 sss : 1; 160 u32 salp : 1; 161 u32 sal : 1; 162 u32 sclo : 1; 163 u32 iss : 4; 164 u32 snzo : 1; 165 u32 sam : 1; 166 u32 spm : 1; 167 u32 fbss : 1; 168 u32 pmd : 1; 169 u32 ssc : 1; 170 u32 psc : 1; 171 u32 ncs : 5; 172 u32 cccs : 1; 173 u32 ems : 1; 174 u32 sxs : 1; 175 u32 np : 5; 176 } s; 177 struct cvmx_sata_uahc_gbl_cap_s cn70xx; 178 struct cvmx_sata_uahc_gbl_cap_s cn70xxp1; 179 struct cvmx_sata_uahc_gbl_cap_s cn73xx; 180}; 181 182typedef union cvmx_sata_uahc_gbl_cap cvmx_sata_uahc_gbl_cap_t; 183 184/** 185 * cvmx_sata_uahc_p#_sctl 186 */ 187union cvmx_sata_uahc_px_sctl { 188 u32 u32; 189 struct cvmx_sata_uahc_px_sctl_s { 190 u32 reserved_10_31 : 22; 191 u32 ipm : 2; 192 u32 reserved_6_7 : 2; 193 u32 spd : 2; 194 u32 reserved_3_3 : 1; 195 u32 det : 3; 196 } s; 197 struct cvmx_sata_uahc_px_sctl_s cn70xx; 198 struct cvmx_sata_uahc_px_sctl_s cn70xxp1; 199 struct cvmx_sata_uahc_px_sctl_s cn73xx; 200}; 201 202typedef union cvmx_sata_uahc_px_sctl cvmx_sata_uahc_px_sctl_t; 203 204/** 205 * cvmx_sata_uahc_p#_cmd 206 */ 207union cvmx_sata_uahc_px_cmd { 208 u32 u32; 209 struct cvmx_sata_uahc_px_cmd_s { 210 u32 icc : 4; 211 u32 asp : 1; 212 u32 alpe : 1; 213 u32 dlae : 1; 214 u32 atapi : 1; 215 u32 apste : 1; 216 u32 fbscp : 1; 217 u32 esp : 1; 218 u32 cpd : 1; 219 u32 mpsp : 1; 220 u32 hpcp : 1; 221 u32 pma : 1; 222 u32 cps : 1; 223 u32 cr : 1; 224 u32 fr : 1; 225 u32 mpss : 1; 226 u32 ccs : 5; 227 u32 reserved_5_7 : 3; 228 u32 fre : 1; 229 u32 clo : 1; 230 u32 pod : 1; 231 u32 sud : 1; 232 u32 st : 1; 233 } s; 234 struct cvmx_sata_uahc_px_cmd_s cn70xx; 235 struct cvmx_sata_uahc_px_cmd_s cn70xxp1; 236 struct cvmx_sata_uahc_px_cmd_s cn73xx; 237}; 238 239typedef union cvmx_sata_uahc_px_cmd cvmx_sata_uahc_px_cmd_t; 240 241/** 242 * cvmx_sata_uahc_gbl_pi 243 * 244 * See AHCI specification v1.3 section 3.1. 245 * 246 */ 247union cvmx_sata_uahc_gbl_pi { 248 u32 u32; 249 struct cvmx_sata_uahc_gbl_pi_s { 250 u32 reserved_2_31 : 30; 251 u32 pi : 2; 252 } s; 253 struct cvmx_sata_uahc_gbl_pi_s cn70xx; 254 struct cvmx_sata_uahc_gbl_pi_s cn70xxp1; 255 struct cvmx_sata_uahc_gbl_pi_s cn73xx; 256}; 257 258typedef union cvmx_sata_uahc_gbl_pi cvmx_sata_uahc_gbl_pi_t; 259 260/** 261 * cvmx_sata_uahc_p#_ssts 262 */ 263union cvmx_sata_uahc_px_ssts { 264 u32 u32; 265 struct cvmx_sata_uahc_px_ssts_s { 266 u32 reserved_12_31 : 20; 267 u32 ipm : 4; 268 u32 spd : 4; 269 u32 det : 4; 270 } s; 271 struct cvmx_sata_uahc_px_ssts_s cn70xx; 272 struct cvmx_sata_uahc_px_ssts_s cn70xxp1; 273 struct cvmx_sata_uahc_px_ssts_s cn73xx; 274}; 275 276typedef union cvmx_sata_uahc_px_ssts cvmx_sata_uahc_px_ssts_t; 277 278/** 279 * cvmx_sata_uahc_p#_tfd 280 */ 281union cvmx_sata_uahc_px_tfd { 282 u32 u32; 283 struct cvmx_sata_uahc_px_tfd_s { 284 u32 reserved_16_31 : 16; 285 u32 tferr : 8; 286 u32 sts : 8; 287 } s; 288 struct cvmx_sata_uahc_px_tfd_s cn70xx; 289 struct cvmx_sata_uahc_px_tfd_s cn70xxp1; 290 struct cvmx_sata_uahc_px_tfd_s cn73xx; 291}; 292 293typedef union cvmx_sata_uahc_px_tfd cvmx_sata_uahc_px_tfd_t; 294 295/** 296 * cvmx_sata_uahc_gbl_timer1ms 297 */ 298union cvmx_sata_uahc_gbl_timer1ms { 299 u32 u32; 300 struct cvmx_sata_uahc_gbl_timer1ms_s { 301 u32 reserved_20_31 : 12; 302 u32 timv : 20; 303 } s; 304 struct cvmx_sata_uahc_gbl_timer1ms_s cn70xx; 305 struct cvmx_sata_uahc_gbl_timer1ms_s cn70xxp1; 306 struct cvmx_sata_uahc_gbl_timer1ms_s cn73xx; 307}; 308 309typedef union cvmx_sata_uahc_gbl_timer1ms cvmx_sata_uahc_gbl_timer1ms_t; 310 311#endif 312