1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 */ 5 6#ifndef __CVMX_SRIOMAINTX_DEFS_H__ 7#define __CVMX_SRIOMAINTX_DEFS_H__ 8 9static inline u64 CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long offset) 10{ 11 switch (cvmx_get_octeon_family()) { 12 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 13 return 0x0000010000000154ull + (offset) * 0x100000000ull; 14 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 15 return 0x0000000000000154ull; 16 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 17 return 0x0000000000000154ull + (offset) * 0x100000000ull; 18 } 19 return 0x0000010000000154ull + (offset) * 0x100000000ull; 20} 21 22/** 23 * cvmx_sriomaint#_port_0_ctl2 24 * 25 * These registers are accessed when a local processor or an external 26 * device wishes to examine the port baudrate information. The automatic 27 * baud rate feature is not available on this device. The SUP_* and ENB_* 28 * fields are set directly by the SRIO()_STATUS_REG[SPD] bits as a 29 * reference but otherwise have no effect. 30 * 31 * WARNING!! Writes to this register will reinitialize the SRIO link. 32 */ 33union cvmx_sriomaintx_port_0_ctl2 { 34 u32 u32; 35 struct cvmx_sriomaintx_port_0_ctl2_s { 36 u32 sel_baud : 4; 37 u32 baud_sup : 1; 38 u32 baud_enb : 1; 39 u32 sup_125g : 1; 40 u32 enb_125g : 1; 41 u32 sup_250g : 1; 42 u32 enb_250g : 1; 43 u32 sup_312g : 1; 44 u32 enb_312g : 1; 45 u32 sub_500g : 1; 46 u32 enb_500g : 1; 47 u32 sup_625g : 1; 48 u32 enb_625g : 1; 49 u32 reserved_2_15 : 14; 50 u32 tx_emph : 1; 51 u32 emph_en : 1; 52 } s; 53 struct cvmx_sriomaintx_port_0_ctl2_s cn63xx; 54 struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1; 55 struct cvmx_sriomaintx_port_0_ctl2_s cn66xx; 56 struct cvmx_sriomaintx_port_0_ctl2_s cnf75xx; 57}; 58 59typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; 60 61#endif 62