LXR uboot/arch/mips/mach-octeon/include/mach/octeon

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 2020 Marvell International Ltd.
   4 */
   5
   6#ifndef __OCTEON_PCI_H__
   7#define __OCTEON_PCI_H__
   8
   9/**
  10 * EEPROM entry struct
  11 */
  12union octeon_pcie_eeprom {
  13        u64 u64;
  14        struct octeon_data_s {
  15                /**
  16                 * 0x9DA1 valid entry, 0x6A5D end of table, 0xffff invalid
  17                 * access
  18                 */
  19                u64 preamble : 16;
  20u64: 1; /** Reserved */
  21                /** Physical function number accessed by the write operation. */
  22                u64 pf : 2;
  23                /**
  24                 * Specifies bit<31> of the address written by hardware.
  25                 * 1 = configuration mask register, 0 = configuration register
  26                 */
  27                u64 cs2 : 1;
  28                /**
  29                 * Specifies bits<11:0> of the address written by hardware.
  30                 * Bits<30:12> of this address are all 0s.
  31                 */
  32                u64 address : 12;
  33                u64 data : 32;
  34        } s;
  35};
  36
  37void pci_dev_post_init(void);
  38
  39int octeon_pci_io_readb(unsigned int reg);
  40void octeon_pci_io_writeb(int value, unsigned int reg);
  41int octeon_pci_io_readw(unsigned int reg);
  42void octeon_pci_io_writew(int value, unsigned int reg);
  43int octeon_pci_io_readl(unsigned int reg);
  44void octeon_pci_io_writel(int value, unsigned int reg);
  45int octeon_pci_mem1_readb(unsigned int reg);
  46void octeon_pci_mem1_writeb(int value, unsigned int reg);
  47int octeon_pci_mem1_readw(unsigned int reg);
  48void octeon_pci_mem1_writew(int value, unsigned int reg);
  49int octeon_pci_mem1_readl(unsigned int reg);
  50void octeon_pci_mem1_writel(int value, unsigned int reg);
  51
  52/* In the TLB mapped case, these also work with virtual addresses,
  53** and do the required virt<->phys translations as well. */
  54u32 octeon_pci_phys_to_bus(u32 phys);
  55u32 octeon_pci_bus_to_phys(u32 bus);
  56
  57/**
  58 * Searches PCIe EEPROM for override data specified by address and pf.
  59 *
  60 * @param       address - PCIe config space address
  61 * @param       pf      - PCIe config space pf num
  62 * @param[out]  id      - override device and vendor ID
  63 *
  64 * @return      0 if override found, 1 if not found.
  65 */
  66int octeon_find_pcie_id_override(unsigned int address, unsigned int pf, u32 *id);
  67
  68#endif /* __OCTEON_PCI_H__ */
  69