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11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
14#include <asm/types.h>
15#include <asm/fsl_dma.h>
16#include <asm/fsl_i2c.h>
17#include <fsl_ifc.h>
18#include <fsl_sec.h>
19#include <fsl_sfp.h>
20#include <asm/fsl_lbc.h>
21#include <fsl_fman.h>
22#include <fsl_immap.h>
23
24typedef struct ccsr_local {
25 u32 ccsrbarh;
26 u32 ccsrbarl;
27 u32 ccsrar;
28#define CCSRAR_C 0x80000000
29 u8 res1[4];
30 u32 altcbarh;
31 u32 altcbarl;
32 u32 altcar;
33 u8 res2[4];
34 u32 bstrh;
35 u32 bstrl;
36 u32 bstrar;
37 u8 res3[0xbd4];
38 struct {
39 u32 lawbarh;
40 u32 lawbarl;
41 u32 lawar;
42 u8 res4[4];
43 } law[32];
44 u8 res35[0x204];
45} ccsr_local_t;
46
47
48typedef struct ccsr_local_ecm {
49 u32 ccsrbar;
50 u8 res1[4];
51 u32 altcbar;
52 u8 res2[4];
53 u32 altcar;
54 u8 res3[12];
55 u32 bptr;
56 u8 res4[3044];
57 u32 lawbar0;
58 u8 res5[4];
59 u32 lawar0;
60 u8 res6[20];
61 u32 lawbar1;
62 u8 res7[4];
63 u32 lawar1;
64 u8 res8[20];
65 u32 lawbar2;
66 u8 res9[4];
67 u32 lawar2;
68 u8 res10[20];
69 u32 lawbar3;
70 u8 res11[4];
71 u32 lawar3;
72 u8 res12[20];
73 u32 lawbar4;
74 u8 res13[4];
75 u32 lawar4;
76 u8 res14[20];
77 u32 lawbar5;
78 u8 res15[4];
79 u32 lawar5;
80 u8 res16[20];
81 u32 lawbar6;
82 u8 res17[4];
83 u32 lawar6;
84 u8 res18[20];
85 u32 lawbar7;
86 u8 res19[4];
87 u32 lawar7;
88 u8 res19_8a[20];
89 u32 lawbar8;
90 u8 res19_8b[4];
91 u32 lawar8;
92 u8 res19_9a[20];
93 u32 lawbar9;
94 u8 res19_9b[4];
95 u32 lawar9;
96 u8 res19_10a[20];
97 u32 lawbar10;
98 u8 res19_10b[4];
99 u32 lawar10;
100 u8 res19_11a[20];
101 u32 lawbar11;
102 u8 res19_11b[4];
103 u32 lawar11;
104 u8 res20[652];
105 u32 eebacr;
106 u8 res21[12];
107 u32 eebpcr;
108 u8 res22[3564];
109 u32 eedr;
110 u8 res23[4];
111 u32 eeer;
112 u32 eeatr;
113 u32 eeadr;
114 u8 res24[492];
115} ccsr_local_ecm_t;
116
117#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000
118#define DDR_EOR_ADDR_HASH_EN 0x40000000
119
120
121typedef struct ccsr_i2c {
122 struct fsl_i2c_base i2c[1];
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
124} ccsr_i2c_t;
125
126#if defined(CONFIG_ARCH_MPC8540) || \
127 defined(CONFIG_ARCH_MPC8548)
128
129typedef struct ccsr_duart {
130 u8 res1[1280];
131
132 u8 urbr1_uthr1_udlb1;
133
134 u8 uier1_udmb1;
135
136 u8 uiir1_ufcr1_uafr1;
137 u8 ulcr1;
138 u8 umcr1;
139 u8 ulsr1;
140 u8 umsr1;
141 u8 uscr1;
142 u8 res2[8];
143 u8 udsr1;
144 u8 res3[239];
145
146 u8 urbr2_uthr2_udlb2;
147
148 u8 uier2_udmb2;
149
150 u8 uiir2_ufcr2_uafr2;
151 u8 ulcr2;
152 u8 umcr2;
153 u8 ulsr2;
154 u8 umsr2;
155 u8 uscr2;
156 u8 res4[8];
157 u8 udsr2;
158 u8 res5[2543];
159} ccsr_duart_t;
160#else
161typedef struct ccsr_duart {
162 u8 res[4096];
163} ccsr_duart_t;
164#endif
165
166
167typedef struct ccsr_espi {
168 u32 mode;
169 u32 event;
170 u32 mask;
171 u32 com;
172 u32 tx;
173 u32 rx;
174 u8 res1[8];
175 u32 csmode[4];
176 u8 res2[4048];
177} ccsr_espi_t;
178
179
180typedef struct ccsr_pcix {
181 u32 cfg_addr;
182 u32 cfg_data;
183 u32 int_ack;
184 u8 res000c[52];
185 u32 liodn_base;
186 u8 res0044[2996];
187 u32 ipver1;
188 u32 ipver2;
189 u32 potar0;
190 u32 potear0;
191 u32 powbar0;
192 u32 powbear0;
193 u32 powar0;
194 u8 res2[12];
195 u32 potar1;
196 u32 potear1;
197 u32 powbar1;
198 u32 powbear1;
199 u32 powar1;
200 u8 res3[12];
201 u32 potar2;
202 u32 potear2;
203 u32 powbar2;
204 u32 powbear2;
205 u32 powar2;
206 u8 res4[12];
207 u32 potar3;
208 u32 potear3;
209 u32 powbar3;
210 u32 powbear3;
211 u32 powar3;
212 u8 res5[12];
213 u32 potar4;
214 u32 potear4;
215 u32 powbar4;
216 u32 powbear4;
217 u32 powar4;
218 u8 res6[268];
219 u32 pitar3;
220 u32 pitear3;
221 u32 piwbar3;
222 u32 piwbear3;
223 u32 piwar3;
224 u8 res7[12];
225 u32 pitar2;
226 u32 pitear2;
227 u32 piwbar2;
228 u32 piwbear2;
229 u32 piwar2;
230 u8 res8[12];
231 u32 pitar1;
232 u32 pitear1;
233 u32 piwbar1;
234 u8 res9[4];
235 u32 piwar1;
236 u8 res10[12];
237 u32 pedr;
238 u32 pecdr;
239 u32 peer;
240 u32 peattrcr;
241 u32 peaddrcr;
242 u32 peextaddrcr;
243 u32 pedlcr;
244 u32 pedhcr;
245 u32 gas_timr;
246 u8 res11[476];
247} ccsr_pcix_t;
248
249#define PCIX_COMMAND 0x62
250#define POWAR_EN 0x80000000
251#define POWAR_IO_READ 0x00080000
252#define POWAR_MEM_READ 0x00040000
253#define POWAR_IO_WRITE 0x00008000
254#define POWAR_MEM_WRITE 0x00004000
255#define POWAR_MEM_512M 0x0000001c
256#define POWAR_IO_1M 0x00000013
257
258#define PIWAR_EN 0x80000000
259#define PIWAR_PF 0x20000000
260#define PIWAR_LOCAL 0x00f00000
261#define PIWAR_READ_SNOOP 0x00050000
262#define PIWAR_WRITE_SNOOP 0x00005000
263#define PIWAR_MEM_2G 0x0000001e
264
265#ifndef CONFIG_MPC85XX_GPIO
266typedef struct ccsr_gpio {
267 u32 gpdir;
268 u32 gpodr;
269 u32 gpdat;
270 u32 gpier;
271 u32 gpimr;
272 u32 gpicr;
273 u32 gpibe;
274} ccsr_gpio_t;
275#endif
276
277
278typedef struct ccsr_l2cache {
279 u32 l2ctl;
280 u8 res1[12];
281 u32 l2cewar0;
282 u8 res2[4];
283 u32 l2cewcr0;
284 u8 res3[4];
285 u32 l2cewar1;
286 u8 res4[4];
287 u32 l2cewcr1;
288 u8 res5[4];
289 u32 l2cewar2;
290 u8 res6[4];
291 u32 l2cewcr2;
292 u8 res7[4];
293 u32 l2cewar3;
294 u8 res8[4];
295 u32 l2cewcr3;
296 u8 res9[180];
297 u32 l2srbar0;
298 u8 res10[4];
299 u32 l2srbar1;
300 u8 res11[3316];
301 u32 l2errinjhi;
302 u32 l2errinjlo;
303 u32 l2errinjctl;
304 u8 res12[20];
305 u32 l2captdatahi;
306 u32 l2captdatalo;
307 u32 l2captecc;
308 u8 res13[20];
309 u32 l2errdet;
310 u32 l2errdis;
311 u32 l2errinten;
312 u32 l2errattr;
313 u32 l2erraddr;
314 u8 res14[4];
315 u32 l2errctl;
316 u8 res15[420];
317} ccsr_l2cache_t;
318
319#define MPC85xx_L2CTL_L2E 0x80000000
320#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
321#define MPC85xx_L2ERRDIS_MBECC 0x00000008
322#define MPC85xx_L2ERRDIS_SBECC 0x00000004
323
324
325typedef struct ccsr_dma {
326 u8 res1[256];
327 struct fsl_dma dma[4];
328 u32 dgsr;
329 u8 res2[11516];
330} ccsr_dma_t;
331
332
333typedef struct ccsr_tsec {
334 u8 res1[16];
335 u32 ievent;
336 u32 imask;
337 u32 edis;
338 u8 res2[4];
339 u32 ecntrl;
340 u32 minflr;
341 u32 ptv;
342 u32 dmactrl;
343 u32 tbipa;
344 u8 res3[88];
345 u32 fifo_tx_thr;
346 u8 res4[8];
347 u32 fifo_tx_starve;
348 u32 fifo_tx_starve_shutoff;
349 u8 res5[96];
350 u32 tctrl;
351 u32 tstat;
352 u8 res6[4];
353 u32 tbdlen;
354 u8 res7[16];
355 u32 ctbptrh;
356 u32 ctbptr;
357 u8 res8[88];
358 u32 tbptrh;
359 u32 tbptr;
360 u8 res9[120];
361 u32 tbaseh;
362 u32 tbase;
363 u8 res10[168];
364 u32 ostbd;
365 u32 ostbdp;
366 u32 os32tbdp;
367 u32 os32iptrh;
368 u32 os32iptrl;
369 u32 os32tbdr;
370 u32 os32iil;
371 u8 res11[52];
372 u32 rctrl;
373 u32 rstat;
374 u8 res12[4];
375 u32 rbdlen;
376 u8 res13[16];
377 u32 crbptrh;
378 u32 crbptr;
379 u8 res14[24];
380 u32 mrblr;
381 u32 mrblr2r3;
382 u8 res15[56];
383 u32 rbptrh;
384 u32 rbptr;
385 u32 rbptrh1;
386 u32 rbptrl1;
387 u32 rbptrh2;
388 u32 rbptrl2;
389 u32 rbptrh3;
390 u32 rbptrl3;
391 u8 res16[96];
392 u32 rbaseh;
393 u32 rbase;
394 u32 rbaseh1;
395 u32 rbasel1;
396 u32 rbaseh2;
397 u32 rbasel2;
398 u32 rbaseh3;
399 u32 rbasel3;
400 u8 res17[224];
401 u32 maccfg1;
402 u32 maccfg2;
403 u32 ipgifg;
404 u32 hafdup;
405 u32 maxfrm;
406 u8 res18[12];
407 u32 miimcfg;
408 u32 miimcom;
409 u32 miimadd;
410 u32 miimcon;
411 u32 miimstat;
412 u32 miimind;
413 u8 res19[4];
414 u32 ifstat;
415 u32 macstnaddr1;
416 u32 macstnaddr2;
417 u8 res20[312];
418 u32 tr64;
419 u32 tr127;
420 u32 tr255;
421 u32 tr511;
422 u32 tr1k;
423 u32 trmax;
424 u32 trmgv;
425 u32 rbyt;
426 u32 rpkt;
427 u32 rfcs;
428 u32 rmca;
429 u32 rbca;
430 u32 rxcf;
431 u32 rxpf;
432 u32 rxuo;
433 u32 raln;
434 u32 rflr;
435 u32 rcde;
436 u32 rcse;
437 u32 rund;
438 u32 rovr;
439 u32 rfrg;
440 u32 rjbr;
441 u32 rdrp;
442 u32 tbyt;
443 u32 tpkt;
444 u32 tmca;
445 u32 tbca;
446 u32 txpf;
447 u32 tdfr;
448 u32 tedf;
449 u32 tscl;
450 u32 tmcl;
451 u32 tlcl;
452 u32 txcl;
453 u32 tncl;
454 u8 res21[4];
455 u32 tdrp;
456 u32 tjbr;
457 u32 tfcs;
458 u32 txcf;
459 u32 tovr;
460 u32 tund;
461 u32 tfrg;
462 u32 car1;
463 u32 car2;
464 u32 cam1;
465 u32 cam2;
466 u8 res22[192];
467 u32 iaddr0;
468 u32 iaddr1;
469 u32 iaddr2;
470 u32 iaddr3;
471 u32 iaddr4;
472 u32 iaddr5;
473 u32 iaddr6;
474 u32 iaddr7;
475 u8 res23[96];
476 u32 gaddr0;
477 u32 gaddr1;
478 u32 gaddr2;
479 u32 gaddr3;
480 u32 gaddr4;
481 u32 gaddr5;
482 u32 gaddr6;
483 u32 gaddr7;
484 u8 res24[96];
485 u32 pmd0;
486 u8 res25[4];
487 u32 pmask0;
488 u8 res26[4];
489 u32 pcntrl0;
490 u8 res27[4];
491 u32 pattrb0;
492 u32 pattrbeli0;
493 u32 pmd1;
494 u8 res28[4];
495 u32 pmask1;
496 u8 res29[4];
497 u32 pcntrl1;
498 u8 res30[4];
499 u32 pattrb1;
500 u32 pattrbeli1;
501 u32 pmd2;
502 u8 res31[4];
503 u32 pmask2;
504 u8 res32[4];
505 u32 pcntrl2;
506 u8 res33[4];
507 u32 pattrb2;
508 u32 pattrbeli2;
509 u32 pmd3;
510 u8 res34[4];
511 u32 pmask3;
512 u8 res35[4];
513 u32 pcntrl3;
514 u8 res36[4];
515 u32 pattrb3;
516 u32 pattrbeli3;
517 u32 pmd4;
518 u8 res37[4];
519 u32 pmask4;
520 u8 res38[4];
521 u32 pcntrl4;
522 u8 res39[4];
523 u32 pattrb4;
524 u32 pattrbeli4;
525 u32 pmd5;
526 u8 res40[4];
527 u32 pmask5;
528 u8 res41[4];
529 u32 pcntrl5;
530 u8 res42[4];
531 u32 pattrb5;
532 u32 pattrbeli5;
533 u32 pmd6;
534 u8 res43[4];
535 u32 pmask6;
536 u8 res44[4];
537 u32 pcntrl6;
538 u8 res45[4];
539 u32 pattrb6;
540 u32 pattrbeli6;
541 u32 pmd7;
542 u8 res46[4];
543 u32 pmask7;
544 u8 res47[4];
545 u32 pcntrl7;
546 u8 res48[4];
547 u32 pattrb7;
548 u32 pattrbeli7;
549 u32 pmd8;
550 u8 res49[4];
551 u32 pmask8;
552 u8 res50[4];
553 u32 pcntrl8;
554 u8 res51[4];
555 u32 pattrb8;
556 u32 pattrbeli8;
557 u32 pmd9;
558 u8 res52[4];
559 u32 pmask9;
560 u8 res53[4];
561 u32 pcntrl9;
562 u8 res54[4];
563 u32 pattrb9;
564 u32 pattrbeli9;
565 u32 pmd10;
566 u8 res55[4];
567 u32 pmask10;
568 u8 res56[4];
569 u32 pcntrl10;
570 u8 res57[4];
571 u32 pattrb10;
572 u32 pattrbeli10;
573 u32 pmd11;
574 u8 res58[4];
575 u32 pmask11;
576 u8 res59[4];
577 u32 pcntrl11;
578 u8 res60[4];
579 u32 pattrb11;
580 u32 pattrbeli11;
581 u32 pmd12;
582 u8 res61[4];
583 u32 pmask12;
584 u8 res62[4];
585 u32 pcntrl12;
586 u8 res63[4];
587 u32 pattrb12;
588 u32 pattrbeli12;
589 u32 pmd13;
590 u8 res64[4];
591 u32 pmask13;
592 u8 res65[4];
593 u32 pcntrl13;
594 u8 res66[4];
595 u32 pattrb13;
596 u32 pattrbeli13;
597 u32 pmd14;
598 u8 res67[4];
599 u32 pmask14;
600 u8 res68[4];
601 u32 pcntrl14;
602 u8 res69[4];
603 u32 pattrb14;
604 u32 pattrbeli14;
605 u32 pmd15;
606 u8 res70[4];
607 u32 pmask15;
608 u8 res71[4];
609 u32 pcntrl15;
610 u8 res72[4];
611 u32 pattrb15;
612 u32 pattrbeli15;
613 u8 res73[248];
614 u32 attr;
615 u32 attreli;
616 u8 res74[1024];
617} ccsr_tsec_t;
618
619
620typedef struct ccsr_pic {
621 u8 res1[64];
622 u32 ipidr0;
623 u8 res2[12];
624 u32 ipidr1;
625 u8 res3[12];
626 u32 ipidr2;
627 u8 res4[12];
628 u32 ipidr3;
629 u8 res5[12];
630 u32 ctpr;
631 u8 res6[12];
632 u32 whoami;
633 u8 res7[12];
634 u32 iack;
635 u8 res8[12];
636 u32 eoi;
637 u8 res9[3916];
638 u32 frr;
639 u8 res10[28];
640 u32 gcr;
641#define MPC85xx_PICGCR_RST 0x80000000
642#define MPC85xx_PICGCR_M 0x20000000
643 u8 res11[92];
644 u32 vir;
645 u8 res12[12];
646 u32 pir;
647 u8 res13[12];
648 u32 ipivpr0;
649 u8 res14[12];
650 u32 ipivpr1;
651 u8 res15[12];
652 u32 ipivpr2;
653 u8 res16[12];
654 u32 ipivpr3;
655 u8 res17[12];
656 u32 svr;
657 u8 res18[12];
658 u32 tfrr;
659 u8 res19[12];
660 u32 gtccr0;
661 u8 res20[12];
662 u32 gtbcr0;
663 u8 res21[12];
664 u32 gtvpr0;
665 u8 res22[12];
666 u32 gtdr0;
667 u8 res23[12];
668 u32 gtccr1;
669 u8 res24[12];
670 u32 gtbcr1;
671 u8 res25[12];
672 u32 gtvpr1;
673 u8 res26[12];
674 u32 gtdr1;
675 u8 res27[12];
676 u32 gtccr2;
677 u8 res28[12];
678 u32 gtbcr2;
679 u8 res29[12];
680 u32 gtvpr2;
681 u8 res30[12];
682 u32 gtdr2;
683 u8 res31[12];
684 u32 gtccr3;
685 u8 res32[12];
686 u32 gtbcr3;
687 u8 res33[12];
688 u32 gtvpr3;
689 u8 res34[12];
690 u32 gtdr3;
691 u8 res35[268];
692 u32 tcr;
693 u8 res36[12];
694 u32 irqsr0;
695 u8 res37[12];
696 u32 irqsr1;
697 u8 res38[12];
698 u32 cisr0;
699 u8 res39[12];
700 u32 cisr1;
701 u8 res40[188];
702 u32 msgr0;
703 u8 res41[12];
704 u32 msgr1;
705 u8 res42[12];
706 u32 msgr2;
707 u8 res43[12];
708 u32 msgr3;
709 u8 res44[204];
710 u32 mer;
711 u8 res45[12];
712 u32 msr;
713 u8 res46[60140];
714 u32 eivpr0;
715 u8 res47[12];
716 u32 eidr0;
717 u8 res48[12];
718 u32 eivpr1;
719 u8 res49[12];
720 u32 eidr1;
721 u8 res50[12];
722 u32 eivpr2;
723 u8 res51[12];
724 u32 eidr2;
725 u8 res52[12];
726 u32 eivpr3;
727 u8 res53[12];
728 u32 eidr3;
729 u8 res54[12];
730 u32 eivpr4;
731 u8 res55[12];
732 u32 eidr4;
733 u8 res56[12];
734 u32 eivpr5;
735 u8 res57[12];
736 u32 eidr5;
737 u8 res58[12];
738 u32 eivpr6;
739 u8 res59[12];
740 u32 eidr6;
741 u8 res60[12];
742 u32 eivpr7;
743 u8 res61[12];
744 u32 eidr7;
745 u8 res62[12];
746 u32 eivpr8;
747 u8 res63[12];
748 u32 eidr8;
749 u8 res64[12];
750 u32 eivpr9;
751 u8 res65[12];
752 u32 eidr9;
753 u8 res66[12];
754 u32 eivpr10;
755 u8 res67[12];
756 u32 eidr10;
757 u8 res68[12];
758 u32 eivpr11;
759 u8 res69[12];
760 u32 eidr11;
761 u8 res70[140];
762 u32 iivpr0;
763 u8 res71[12];
764 u32 iidr0;
765 u8 res72[12];
766 u32 iivpr1;
767 u8 res73[12];
768 u32 iidr1;
769 u8 res74[12];
770 u32 iivpr2;
771 u8 res75[12];
772 u32 iidr2;
773 u8 res76[12];
774 u32 iivpr3;
775 u8 res77[12];
776 u32 iidr3;
777 u8 res78[12];
778 u32 iivpr4;
779 u8 res79[12];
780 u32 iidr4;
781 u8 res80[12];
782 u32 iivpr5;
783 u8 res81[12];
784 u32 iidr5;
785 u8 res82[12];
786 u32 iivpr6;
787 u8 res83[12];
788 u32 iidr6;
789 u8 res84[12];
790 u32 iivpr7;
791 u8 res85[12];
792 u32 iidr7;
793 u8 res86[12];
794 u32 iivpr8;
795 u8 res87[12];
796 u32 iidr8;
797 u8 res88[12];
798 u32 iivpr9;
799 u8 res89[12];
800 u32 iidr9;
801 u8 res90[12];
802 u32 iivpr10;
803 u8 res91[12];
804 u32 iidr10;
805 u8 res92[12];
806 u32 iivpr11;
807 u8 res93[12];
808 u32 iidr11;
809 u8 res94[12];
810 u32 iivpr12;
811 u8 res95[12];
812 u32 iidr12;
813 u8 res96[12];
814 u32 iivpr13;
815 u8 res97[12];
816 u32 iidr13;
817 u8 res98[12];
818 u32 iivpr14;
819 u8 res99[12];
820 u32 iidr14;
821 u8 res100[12];
822 u32 iivpr15;
823 u8 res101[12];
824 u32 iidr15;
825 u8 res102[12];
826 u32 iivpr16;
827 u8 res103[12];
828 u32 iidr16;
829 u8 res104[12];
830 u32 iivpr17;
831 u8 res105[12];
832 u32 iidr17;
833 u8 res106[12];
834 u32 iivpr18;
835 u8 res107[12];
836 u32 iidr18;
837 u8 res108[12];
838 u32 iivpr19;
839 u8 res109[12];
840 u32 iidr19;
841 u8 res110[12];
842 u32 iivpr20;
843 u8 res111[12];
844 u32 iidr20;
845 u8 res112[12];
846 u32 iivpr21;
847 u8 res113[12];
848 u32 iidr21;
849 u8 res114[12];
850 u32 iivpr22;
851 u8 res115[12];
852 u32 iidr22;
853 u8 res116[12];
854 u32 iivpr23;
855 u8 res117[12];
856 u32 iidr23;
857 u8 res118[12];
858 u32 iivpr24;
859 u8 res119[12];
860 u32 iidr24;
861 u8 res120[12];
862 u32 iivpr25;
863 u8 res121[12];
864 u32 iidr25;
865 u8 res122[12];
866 u32 iivpr26;
867 u8 res123[12];
868 u32 iidr26;
869 u8 res124[12];
870 u32 iivpr27;
871 u8 res125[12];
872 u32 iidr27;
873 u8 res126[12];
874 u32 iivpr28;
875 u8 res127[12];
876 u32 iidr28;
877 u8 res128[12];
878 u32 iivpr29;
879 u8 res129[12];
880 u32 iidr29;
881 u8 res130[12];
882 u32 iivpr30;
883 u8 res131[12];
884 u32 iidr30;
885 u8 res132[12];
886 u32 iivpr31;
887 u8 res133[12];
888 u32 iidr31;
889 u8 res134[4108];
890 u32 mivpr0;
891 u8 res135[12];
892 u32 midr0;
893 u8 res136[12];
894 u32 mivpr1;
895 u8 res137[12];
896 u32 midr1;
897 u8 res138[12];
898 u32 mivpr2;
899 u8 res139[12];
900 u32 midr2;
901 u8 res140[12];
902 u32 mivpr3;
903 u8 res141[12];
904 u32 midr3;
905 u8 res142[59852];
906 u32 ipi0dr0;
907 u8 res143[12];
908 u32 ipi0dr1;
909 u8 res144[12];
910 u32 ipi0dr2;
911 u8 res145[12];
912 u32 ipi0dr3;
913 u8 res146[12];
914 u32 ctpr0;
915 u8 res147[12];
916 u32 whoami0;
917 u8 res148[12];
918 u32 iack0;
919 u8 res149[12];
920 u32 eoi0;
921 u8 res150[130892];
922} ccsr_pic_t;
923
924
925#ifndef CONFIG_CPM2
926typedef struct ccsr_cpm {
927 u8 res[262144];
928} ccsr_cpm_t;
929#else
930
931
932
933
934typedef struct ccsr_cpm_siu {
935 u8 res1[80];
936 u32 smaer;
937 u32 smser;
938 u32 smevr;
939 u8 res2[4];
940 u32 lmaer;
941 u32 lmser;
942 u32 lmevr;
943 u8 res3[2964];
944} ccsr_cpm_siu_t;
945
946
947typedef struct ccsr_cpm_intctl {
948 u16 sicr;
949 u8 res1[2];
950 u32 sivec;
951 u32 sipnrh;
952 u32 sipnrl;
953 u32 siprr;
954 u32 scprrh;
955 u32 scprrl;
956 u32 simrh;
957 u32 simrl;
958 u32 siexr;
959 u8 res2[88];
960 u32 sccr;
961 u8 res3[124];
962} ccsr_cpm_intctl_t;
963
964
965typedef struct ccsr_cpm_iop {
966 u32 pdira;
967 u32 ppara;
968 u32 psora;
969 u32 podra;
970 u32 pdata;
971 u8 res1[12];
972 u32 pdirb;
973 u32 pparb;
974 u32 psorb;
975 u32 podrb;
976 u32 pdatb;
977 u8 res2[12];
978 u32 pdirc;
979 u32 pparc;
980 u32 psorc;
981 u32 podrc;
982 u32 pdatc;
983 u8 res3[12];
984 u32 pdird;
985 u32 ppard;
986 u32 psord;
987 u32 podrd;
988 u32 pdatd;
989 u8 res4[12];
990} ccsr_cpm_iop_t;
991
992
993typedef struct ccsr_cpm_timer {
994 u8 tgcr1;
995 u8 res1[3];
996 u8 tgcr2;
997 u8 res2[11];
998 u16 tmr1;
999 u16 tmr2;
1000 u16 trr1;
1001 u16 trr2;
1002 u16 tcr1;
1003 u16 tcr2;
1004 u16 tcn1;
1005 u16 tcn2;
1006 u16 tmr3;
1007 u16 tmr4;
1008 u16 trr3;
1009 u16 trr4;
1010 u16 tcr3;
1011 u16 tcr4;
1012 u16 tcn3;
1013 u16 tcn4;
1014 u16 ter1;
1015 u16 ter2;
1016 u16 ter3;
1017 u16 ter4;
1018 u8 res3[608];
1019} ccsr_cpm_timer_t;
1020
1021
1022typedef struct ccsr_cpm_sdma {
1023 u8 sdsr;
1024 u8 res1[3];
1025 u8 sdmr;
1026 u8 res2[739];
1027} ccsr_cpm_sdma_t;
1028
1029
1030typedef struct ccsr_cpm_fcc1 {
1031 u32 gfmr;
1032 u32 fpsmr;
1033 u16 ftodr;
1034 u8 res1[2];
1035 u16 fdsr;
1036 u8 res2[2];
1037 u16 fcce;
1038 u8 res3[2];
1039 u16 fccm;
1040 u8 res4[2];
1041 u8 fccs;
1042 u8 res5[3];
1043 u8 ftirr_phy[4];
1044} ccsr_cpm_fcc1_t;
1045
1046
1047typedef struct ccsr_cpm_fcc2 {
1048 u32 gfmr;
1049 u32 fpsmr;
1050 u16 ftodr;
1051 u8 res1[2];
1052 u16 fdsr;
1053 u8 res2[2];
1054 u16 fcce;
1055 u8 res3[2];
1056 u16 fccm;
1057 u8 res4[2];
1058 u8 fccs;
1059 u8 res5[3];
1060 u8 ftirr_phy[4];
1061} ccsr_cpm_fcc2_t;
1062
1063
1064typedef struct ccsr_cpm_fcc3 {
1065 u32 gfmr;
1066 u32 fpsmr;
1067 u16 ftodr;
1068 u8 res1[2];
1069 u16 fdsr;
1070 u8 res2[2];
1071 u16 fcce;
1072 u8 res3[2];
1073 u16 fccm;
1074 u8 res4[2];
1075 u8 fccs;
1076 u8 res5[3];
1077 u8 res[36];
1078} ccsr_cpm_fcc3_t;
1079
1080
1081typedef struct ccsr_cpm_fcc1_ext {
1082 u32 firper;
1083 u32 firer;
1084 u32 firsr_h;
1085 u32 firsr_l;
1086 u8 gfemr;
1087 u8 res[15];
1088
1089} ccsr_cpm_fcc1_ext_t;
1090
1091
1092typedef struct ccsr_cpm_fcc2_ext {
1093 u32 firper;
1094 u32 firer;
1095 u32 firsr_h;
1096 u32 firsr_l;
1097 u8 gfemr;
1098 u8 res[31];
1099} ccsr_cpm_fcc2_ext_t;
1100
1101
1102typedef struct ccsr_cpm_fcc3_ext {
1103 u8 gfemr;
1104 u8 res[47];
1105} ccsr_cpm_fcc3_ext_t;
1106
1107
1108typedef struct ccsr_cpm_tmp1 {
1109 u8 res[496];
1110} ccsr_cpm_tmp1_t;
1111
1112
1113typedef struct ccsr_cpm_brg2 {
1114 u32 brgc5;
1115 u32 brgc6;
1116 u32 brgc7;
1117 u32 brgc8;
1118 u8 res[608];
1119} ccsr_cpm_brg2_t;
1120
1121
1122typedef struct ccsr_cpm_i2c {
1123 u8 i2mod;
1124 u8 res1[3];
1125 u8 i2add;
1126 u8 res2[3];
1127 u8 i2brg;
1128 u8 res3[3];
1129 u8 i2com;
1130 u8 res4[3];
1131 u8 i2cer;
1132 u8 res5[3];
1133 u8 i2cmr;
1134 u8 res6[331];
1135} ccsr_cpm_i2c_t;
1136
1137
1138typedef struct ccsr_cpm_cp {
1139 u32 cpcr;
1140 u32 rccr;
1141 u8 res1[14];
1142 u16 rter;
1143 u8 res2[2];
1144 u16 rtmr;
1145 u16 rtscr;
1146 u8 res3[2];
1147 u32 rtsr;
1148 u8 res4[12];
1149} ccsr_cpm_cp_t;
1150
1151
1152typedef struct ccsr_cpm_brg1 {
1153 u32 brgc1;
1154 u32 brgc2;
1155 u32 brgc3;
1156 u32 brgc4;
1157} ccsr_cpm_brg1_t;
1158
1159
1160typedef struct ccsr_cpm_scc {
1161 u32 gsmrl;
1162 u32 gsmrh;
1163 u16 psmr;
1164 u8 res1[2];
1165 u16 todr;
1166 u16 dsr;
1167 u16 scce;
1168 u8 res2[2];
1169 u16 sccm;
1170 u8 res3;
1171 u8 sccs;
1172 u8 res4[8];
1173} ccsr_cpm_scc_t;
1174
1175typedef struct ccsr_cpm_tmp2 {
1176 u8 res[32];
1177} ccsr_cpm_tmp2_t;
1178
1179
1180typedef struct ccsr_cpm_spi {
1181 u16 spmode;
1182 u8 res1[4];
1183 u8 spie;
1184 u8 res2[3];
1185 u8 spim;
1186 u8 res3[2];
1187 u8 spcom;
1188 u8 res4[82];
1189} ccsr_cpm_spi_t;
1190
1191
1192typedef struct ccsr_cpm_mux {
1193 u8 cmxsi1cr;
1194 u8 res1;
1195 u8 cmxsi2cr;
1196 u8 res2;
1197 u32 cmxfcr;
1198 u32 cmxscr;
1199 u8 res3[2];
1200 u16 cmxuar;
1201 u8 res4[16];
1202} ccsr_cpm_mux_t;
1203
1204
1205typedef struct ccsr_cpm_tmp3 {
1206 u8 res[58592];
1207} ccsr_cpm_tmp3_t;
1208
1209typedef struct ccsr_cpm_iram {
1210 u32 iram[8192];
1211 u8 res[98304];
1212} ccsr_cpm_iram_t;
1213
1214typedef struct ccsr_cpm {
1215
1216
1217
1218#define im_dprambase im_dpram1
1219 u8 im_dpram1[16*1024];
1220 u8 res1[16*1024];
1221 u8 im_dpram2[16*1024];
1222 u8 res2[16*1024];
1223 ccsr_cpm_siu_t im_cpm_siu;
1224 ccsr_cpm_intctl_t im_cpm_intctl;
1225 ccsr_cpm_iop_t im_cpm_iop;
1226 ccsr_cpm_timer_t im_cpm_timer;
1227 ccsr_cpm_sdma_t im_cpm_sdma;
1228 ccsr_cpm_fcc1_t im_cpm_fcc1;
1229 ccsr_cpm_fcc2_t im_cpm_fcc2;
1230 ccsr_cpm_fcc3_t im_cpm_fcc3;
1231 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1232 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1233 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1234 ccsr_cpm_tmp1_t im_cpm_tmp1;
1235 ccsr_cpm_brg2_t im_cpm_brg2;
1236 ccsr_cpm_i2c_t im_cpm_i2c;
1237 ccsr_cpm_cp_t im_cpm_cp;
1238 ccsr_cpm_brg1_t im_cpm_brg1;
1239 ccsr_cpm_scc_t im_cpm_scc[4];
1240 ccsr_cpm_tmp2_t im_cpm_tmp2;
1241 ccsr_cpm_spi_t im_cpm_spi;
1242 ccsr_cpm_mux_t im_cpm_mux;
1243 ccsr_cpm_tmp3_t im_cpm_tmp3;
1244 ccsr_cpm_iram_t im_cpm_iram;
1245} ccsr_cpm_t;
1246#endif
1247
1248#ifdef CONFIG_SYS_SRIO
1249
1250struct rio_arch {
1251 u32 didcar;
1252 u32 dicar;
1253 u32 aidcar;
1254 u32 aicar;
1255 u32 pefcar;
1256 u8 res0[4];
1257 u32 socar;
1258 u32 docar;
1259 u8 res1[32];
1260 u32 mcsr;
1261 u32 pwdcsr;
1262 u8 res2[4];
1263 u32 pellccsr;
1264 u8 res3[12];
1265 u32 lcsbacsr;
1266 u32 bdidcsr;
1267 u8 res4[4];
1268 u32 hbdidlcsr;
1269 u32 ctcsr;
1270};
1271
1272
1273struct rio_lp_serial_port {
1274 u32 plmreqcsr;
1275 u32 plmrespcsr;
1276 u32 plascsr;
1277 u8 res0[12];
1278 u32 pescsr;
1279 u32 pccsr;
1280};
1281
1282
1283struct rio_lp_serial {
1284 u32 pmbh0csr;
1285 u8 res0[28];
1286 u32 pltoccsr;
1287 u32 prtoccsr;
1288 u8 res1[20];
1289 u32 pgccsr;
1290 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1291};
1292
1293
1294struct rio_logical_err {
1295 u32 erbh;
1296 u8 res0[4];
1297 u32 ltledcsr;
1298 u32 ltleecsr;
1299 u8 res1[4];
1300 u32 ltlaccsr;
1301 u32 ltldidccsr;
1302 u32 ltlcccsr;
1303};
1304
1305
1306struct rio_phys_err_port {
1307 u32 edcsr;
1308 u32 erecsr;
1309 u32 ecacsr;
1310 u32 pcseccsr0;
1311 u32 peccsr[3];
1312 u8 res0[12];
1313 u32 ercsr;
1314 u32 ertcsr;
1315 u8 res1[16];
1316};
1317
1318
1319struct rio_phys_err {
1320 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1321};
1322
1323
1324struct rio_impl_common {
1325 u8 res0[4];
1326 u32 llcr;
1327 u8 res1[8];
1328 u32 epwisr;
1329 u8 res2[12];
1330 u32 lretcr;
1331 u8 res3[92];
1332 u32 pretcr;
1333 u8 res4[124];
1334};
1335
1336
1337struct rio_impl_port_spec {
1338 u32 adidcsr;
1339 u8 res0[28];
1340 u32 ptaacr;
1341 u32 lopttlcr;
1342 u8 res1[8];
1343 u32 iecsr;
1344 u8 res2[12];
1345 u32 pcr;
1346 u8 res3[20];
1347 u32 slcsr;
1348 u8 res4[4];
1349 u32 sleicr;
1350 u32 a0txcr;
1351 u32 a1txcr;
1352 u32 a2txcr;
1353 u32 mreqtxbacr[3];
1354 u32 mrspfctxbacr;
1355};
1356
1357
1358struct rio_implement {
1359 struct rio_impl_common com;
1360 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1361};
1362
1363
1364struct rio_rev_ctrl {
1365 u32 ipbrr[2];
1366};
1367
1368struct rio_atmu_row {
1369 u32 rowtar;
1370 u32 rowtear;
1371 u32 rowbar;
1372 u8 res0[4];
1373 u32 rowar;
1374 u32 rowsr[3];
1375};
1376
1377struct rio_atmu_riw {
1378 u32 riwtar;
1379 u8 res0[4];
1380 u32 riwbar;
1381 u8 res1[4];
1382 u32 riwar;
1383 u8 res2[12];
1384};
1385
1386
1387struct rio_atmu_win {
1388 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1389 u8 res0[64];
1390 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1391};
1392
1393struct rio_atmu {
1394 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1395};
1396
1397#ifdef CONFIG_SYS_FSL_RMU
1398struct rio_msg {
1399 u32 omr;
1400 u32 osr;
1401 u32 eodqdpar;
1402 u32 odqdpar;
1403 u32 eosar;
1404 u32 osar;
1405 u32 odpr;
1406 u32 odatr;
1407 u32 odcr;
1408 u32 eodqepar;
1409 u32 odqepar;
1410 u32 oretr;
1411 u32 omgr;
1412 u32 omlr;
1413 u8 res0[40];
1414 u32 imr;
1415 u32 isr;
1416 u32 eidqdpar;
1417 u32 idqdpar;
1418 u32 eifqepar;
1419 u32 ifqepar;
1420 u32 imirir;
1421 u8 res1[4];
1422 u32 eihqepar;
1423 u32 ihqepar;
1424 u8 res2[120];
1425};
1426
1427struct rio_dbell {
1428 u32 odmr;
1429 u32 odsr;
1430 u8 res0[16];
1431 u32 oddpr;
1432 u32 oddatr;
1433 u8 res1[12];
1434 u32 oddretr;
1435 u8 res2[48];
1436 u32 idmr;
1437 u32 idsr;
1438 u32 iedqdpar;
1439 u32 iqdpar;
1440 u32 iedqepar;
1441 u32 idqepar;
1442 u32 idmirir;
1443};
1444
1445struct rio_pw {
1446 u32 pwmr;
1447 u32 pwsr;
1448 u32 epwqbar;
1449 u32 pwqbar;
1450};
1451#endif
1452
1453#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1454struct rio_liodn {
1455 u32 plbr;
1456 u8 res0[28];
1457 u32 plaor;
1458 u8 res1[12];
1459 u32 pludr;
1460 u32 plldr;
1461 u8 res2[456];
1462};
1463#endif
1464
1465
1466struct ccsr_rio {
1467 struct rio_arch arch;
1468 u8 res0[144];
1469 struct rio_lp_serial lp_serial;
1470 u8 res1[1152];
1471 struct rio_logical_err logical_err;
1472 u8 res2[32];
1473 struct rio_phys_err phys_err;
1474 u8 res3[63808];
1475 struct rio_implement impl;
1476 u8 res4[2552];
1477 struct rio_rev_ctrl rev;
1478 struct rio_atmu atmu;
1479#ifdef CONFIG_SYS_FSL_RMU
1480 u8 res5[8192];
1481 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1482 u8 res6[512];
1483 struct rio_dbell dbell;
1484 u8 res7[100];
1485 struct rio_pw pw;
1486#endif
1487#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1488 u8 res5[8192];
1489 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1490#endif
1491};
1492#endif
1493
1494
1495typedef struct par_io {
1496 u32 cpodr;
1497 u32 cpdat;
1498 u32 cpdir1;
1499 u32 cpdir2;
1500 u32 cppar1;
1501 u32 cppar2;
1502 u8 res[8];
1503} par_io_t;
1504
1505#ifdef CONFIG_SYS_FSL_CPC
1506
1507
1508
1509
1510
1511
1512typedef struct cpc_corenet {
1513 u32 cpccsr0;
1514 u32 res1;
1515 u32 cpccfg0;
1516 u32 res2;
1517 u32 cpcewcr0;
1518 u32 cpcewabr0;
1519 u32 res3[2];
1520 u32 cpcewcr1;
1521 u32 cpcewabr1;
1522 u32 res4[54];
1523 u32 cpcsrcr1;
1524 u32 cpcsrcr0;
1525 u32 res5[62];
1526 struct {
1527 u32 id;
1528 u32 res;
1529 u32 alloc;
1530 u32 way;
1531 } partition_regs[16];
1532 u32 res6[704];
1533 u32 cpcerrinjhi;
1534 u32 cpcerrinjlo;
1535 u32 cpcerrinjctl;
1536 u32 res7[5];
1537 u32 cpccaptdatahi;
1538 u32 cpccaptdatalo;
1539 u32 cpcaptecc;
1540 u32 res8[5];
1541 u32 cpcerrdet;
1542 u32 cpcerrdis;
1543 u32 cpcerrinten;
1544 u32 cpcerrattr;
1545 u32 cpcerreaddr;
1546 u32 cpcerraddr;
1547 u32 cpcerrctl;
1548 u32 res9[41];
1549 u32 cpchdbcr0;
1550 u32 res10[63];
1551} cpc_corenet_t;
1552
1553#define CPC_CSR0_CE 0x80000000
1554#define CPC_CSR0_PE 0x40000000
1555#define CPC_CSR0_FI 0x00200000
1556#define CPC_CSR0_WT 0x00080000
1557#define CPC_CSR0_FL 0x00000800
1558#define CPC_CSR0_LFC 0x00000400
1559#define CPC_CFG0_SZ_MASK 0x00003fff
1560#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1561#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1562#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1563#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1564#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1565 & CPC_SRCR1_SRBARU_MASK)
1566#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1567#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1568#define CPC_SRCR0_INTLVEN 0x00000100
1569#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1570#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1571#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1572#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1573#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1574#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1575#define CPC_SRCR0_SRAMEN 0x00000001
1576#define CPC_ERRDIS_TMHITDIS 0x00000080
1577#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1578#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1579#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1580#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
1581#endif
1582
1583
1584#ifdef CONFIG_FSL_CORENET
1585typedef struct ccsr_gur {
1586 u32 porsr1;
1587 u32 porsr2;
1588#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1589#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1590#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1591#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1592#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1593#endif
1594 u8 res_008[0x20-0x8];
1595 u32 gpporcr1;
1596 u32 gpporcr2;
1597 u32 dcfg_fusesr;
1598#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1599#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1600#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1601#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1602 u8 res_02c[0x70-0x2c];
1603 u32 devdisr;
1604 u32 devdisr2;
1605 u32 devdisr3;
1606 u32 devdisr4;
1607#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1608 u32 devdisr5;
1609#define FSL_CORENET_DEVDISR_PBL 0x80000000
1610#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1611#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1612#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1613#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1614#define FSL_CORENET_DEVDISR_USB1 0x00080000
1615#define FSL_CORENET_DEVDISR_USB2 0x00040000
1616#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1617#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1618#define FSL_CORENET_DEVDISR_PME 0x00000800
1619#define FSL_CORENET_DEVDISR_SEC 0x00000200
1620#define FSL_CORENET_DEVDISR_RMU 0x00000080
1621#define FSL_CORENET_DEVDISR_DCE 0x00000040
1622#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1623#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1624#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1625#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1626#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1627#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1628#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1629#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1630#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
1631#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1632#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1633#else
1634#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1635#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1636#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1637#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1638#endif
1639#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1640#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1641#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1642#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1643#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1644#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1645#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1646#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1647#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1648#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1649#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1650#define FSL_CORENET_DEVDISR2_FM2 0x00000040
1651#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1652#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1653#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1654#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1655#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1656#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1657#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1658#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1659#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1660#define FSL_CORENET_DEVDISR3_LA1 0x00008000
1661#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1662#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1663#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1664#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1665#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1666#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1667#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1668#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1669#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1670#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1671#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1672#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1673#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1674#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1675#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1676#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1677#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1678#define FSL_CORENET_DEVDISR5_NAL 0x00100000
1679#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1680#define FSL_CORENET_NUM_DEVDISR 5
1681#else
1682#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1683#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1684#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1685#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1686#define FSL_CORENET_DEVDISR_RMU 0x08000000
1687#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1688#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1689#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1690#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1691#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1692#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1693#define FSL_CORENET_DEVDISR_DBG 0x00010000
1694#define FSL_CORENET_DEVDISR_NAL 0x00008000
1695#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1696#define FSL_CORENET_DEVDISR_SATA2 0x00002000
1697#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1698#define FSL_CORENET_DEVDISR_USB1 0x00000800
1699#define FSL_CORENET_DEVDISR_USB2 0x00000400
1700#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1701#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1702#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1703#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1704#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1705#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1706#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1707#define FSL_CORENET_DEVDISR2_PME 0x80000000
1708#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1709#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1710#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1711#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1712#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1713#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1714#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1715#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1716#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1717#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1718#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1719#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1720#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1721#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1722#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1723#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1724#define FSL_CORENET_NUM_DEVDISR 2
1725 u32 powmgtcsr;
1726#endif
1727 u8 res8[12];
1728 u32 coredisru;
1729 u32 coredisrl;
1730 u8 res9[8];
1731 u32 pvr;
1732 u32 svr;
1733 u8 res10[8];
1734 u32 rstcr;
1735 u32 rstrqpblsr;
1736 u8 res11[8];
1737 u32 rstrqmr1;
1738#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1739#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1740#endif
1741 u8 res12[4];
1742 u32 rstrqsr1;
1743 u8 res13[4];
1744 u8 res14[4];
1745 u32 rstrqwdtmrl;
1746 u8 res15[4];
1747 u32 rstrqwdtsrl;
1748 u8 res16[4];
1749 u32 brrl;
1750 u8 res17[24];
1751 u32 rcwsr[16];
1752#define RCW_SB_EN_REG_INDEX 7
1753#define RCW_SB_EN_MASK 0x00200000
1754
1755#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1756#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1757
1758#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
1759#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1760#if defined(CONFIG_ARCH_T4240)
1761#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1762#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1763#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1764#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1765#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1766#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1767#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1768#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1769#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1770#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
1771#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1772#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1773#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1774#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1775#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1776#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
1777#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1778#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1779#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1780#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1781#define FSL_CORENET_RCWSR13_EC1 0x30000000
1782#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1783#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1784#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1785#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1786#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1787#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
1788#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1789#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1790#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
1791#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1792#define PXCKEN_MASK 0x80000000
1793#define PXCK_MASK 0x00FF0000
1794#define PXCK_BITS_START 16
1795#elif defined(CONFIG_ARCH_T1024)
1796#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1797#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
1798#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1799#define FSL_CORENET_RCWSR13_EC1 0x30000000
1800#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1801#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1802#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1803#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
1804#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1805#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
1806#define PXCKEN_MASK 0x80000000
1807#define PXCK_MASK 0x00FF0000
1808#define PXCK_BITS_START 16
1809#elif defined(CONFIG_ARCH_T2080)
1810#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1811#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1812#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1813#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1814#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1815#endif
1816#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1817#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1818#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1819#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1820#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1821#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1822#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1823#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1824#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1825#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1826#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1827
1828#else
1829#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1830#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1831#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1832#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1833#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1834#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1835#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1836#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1837#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000
1838#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000
1839#endif
1840
1841#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1842#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1843#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1844#define FSL_CORENET_RCWSR11_EC1 0x00c00000
1845#ifdef CONFIG_ARCH_P4080
1846#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1847#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1848#define FSL_CORENET_RCWSR11_EC2 0x001c0000
1849#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1850#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1851#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1852#endif
1853#if defined(CONFIG_ARCH_P2041) || \
1854 defined(CONFIG_ARCH_P3041)
1855#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1856#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1857#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1858#define FSL_CORENET_RCWSR11_EC2 0x00180000
1859#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1860#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1861#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1862#endif
1863#if defined(CONFIG_ARCH_P5040)
1864#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1865#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1866#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1867#define FSL_CORENET_RCWSR11_EC2 0x00180000
1868#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1869#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1870#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1871#endif
1872#if defined(CONFIG_ARCH_T4240)
1873#define FSL_CORENET_RCWSR13_EC1 0x60000000
1874#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1875#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1876#define FSL_CORENET_RCWSR13_EC2 0x18000000
1877#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1878#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1879#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1880#endif
1881#if defined(CONFIG_ARCH_T2080)
1882#define FSL_CORENET_RCWSR13_EC1 0x60000000
1883#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1884#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1885#define FSL_CORENET_RCWSR13_EC2 0x18000000
1886#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1887#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1888#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1889#endif
1890 u8 res18[192];
1891 u32 scratchrw[4];
1892 u8 res19[240];
1893 u32 scratchw1r[4];
1894 u8 res20[240];
1895 u32 scrtsr[8];
1896 u8 res21[224];
1897 u32 pex1liodnr;
1898 u32 pex2liodnr;
1899 u32 pex3liodnr;
1900 u32 pex4liodnr;
1901 u32 rio1liodnr;
1902 u32 rio2liodnr;
1903 u32 rio3liodnr;
1904 u32 rio4liodnr;
1905 u32 usb1liodnr;
1906 u32 usb2liodnr;
1907 u32 usb3liodnr;
1908 u32 usb4liodnr;
1909 u32 sdmmc1liodnr;
1910 u32 sdmmc2liodnr;
1911 u32 sdmmc3liodnr;
1912 u32 sdmmc4liodnr;
1913 u32 rio1maintliodnr;
1914 u32 rio2maintliodnr;
1915 u32 rio3maintliodnr;
1916 u32 rio4maintliodnr;
1917 u32 sata1liodnr;
1918 u32 sata2liodnr;
1919 u32 sata3liodnr;
1920 u32 sata4liodnr;
1921 u8 res22[20];
1922 u32 tdmliodnr;
1923 u32 qeliodnr;
1924 u8 res_57c[4];
1925 u32 dma1liodnr;
1926 u32 dma2liodnr;
1927 u32 dma3liodnr;
1928 u32 dma4liodnr;
1929 u8 res23[48];
1930 u8 res24[64];
1931 u32 pblsr;
1932 u32 pamubypenr;
1933 u32 dmacr1;
1934 u8 res25[4];
1935 u32 gensr1;
1936 u8 res26[12];
1937 u32 gencr1;
1938 u8 res27[12];
1939 u8 res28[4];
1940 u32 cgensrl;
1941 u8 res29[8];
1942 u8 res30[4];
1943 u32 cgencrl;
1944 u8 res31[184];
1945 u32 sriopstecr;
1946 u32 dcsrcr;
1947 u8 res31a[56];
1948 u32 tp_ityp[64];
1949 struct {
1950 u32 upper;
1951 u32 lower;
1952 } tp_cluster[16];
1953 u8 res32[1344];
1954 u32 pmuxcr;
1955 u8 res33[60];
1956 u32 iovselsr;
1957 u8 res34[28];
1958 u32 ddrclkdr;
1959 u8 res35;
1960 u32 elbcclkdr;
1961 u8 res36[20];
1962 u32 sdhcpcr;
1963 u8 res37[380];
1964} ccsr_gur_t;
1965
1966#define TP_ITYP_AV 0x00000001
1967#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)
1968#define TP_ITYP_TYPE_OTHER 0x0
1969#define TP_ITYP_TYPE_PPC 0x1
1970#define TP_ITYP_TYPE_SC 0x2
1971#define TP_ITYP_TYPE_HA 0x3
1972#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)
1973#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5)
1974
1975#define TP_CLUSTER_EOC 0x80000000
1976#define TP_CLUSTER_INIT_MASK 0x0000003f
1977#define TP_INIT_PER_CLUSTER 4
1978
1979#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1980#define FSL_CORENET_DCSR_SZ_4M 0x0
1981#define FSL_CORENET_DCSR_SZ_1G 0x3
1982
1983
1984
1985
1986
1987#define rmuliodnr rio1maintliodnr
1988
1989typedef struct ccsr_clk {
1990 struct {
1991 u32 clkcncsr;
1992 u8 res_004[0x0c];
1993 u32 clkcgnhwacsr;
1994 u8 res_014[0x0c];
1995 } clkcsr[12];
1996 u8 res_100[0x680];
1997 struct {
1998 u32 pllcngsr;
1999 u8 res10[0x1c];
2000 } pllcgsr[12];
2001 u8 res21[0x280];
2002 u32 pllpgsr;
2003 u8 res16[0x1c];
2004 u32 plldgsr;
2005 u8 res17[0x3dc];
2006} ccsr_clk_t;
2007
2008#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2009typedef struct ccsr_rcpm {
2010 u8 res_00[12];
2011 u32 tph10sr0;
2012 u8 res_10[12];
2013 u32 tph10setr0;
2014 u8 res_20[12];
2015 u32 tph10clrr0;
2016 u8 res_30[12];
2017 u32 tph10psr0;
2018 u8 res_40[12];
2019 u32 twaitsr0;
2020 u8 res_50[96];
2021 u32 pcph15sr;
2022 u32 pcph15setr;
2023 u32 pcph15clrr;
2024 u32 pcph15psr;
2025 u8 res_c0[16];
2026 u32 pcph20sr;
2027 u32 pcph20setr;
2028 u32 pcph20clrr;
2029 u32 pcph20psr;
2030 u32 pcpw20sr;
2031 u8 res_e0[12];
2032 u32 pcph30sr;
2033 u32 pcph30setr;
2034 u32 pcph30clrr;
2035 u32 pcph30psr;
2036 u8 res_100[32];
2037 u32 ippwrgatecr;
2038 u8 res_124[12];
2039 u32 powmgtcsr;
2040 u8 res_134[12];
2041 u32 ippdexpcr[4];
2042 u8 res_150[12];
2043 u32 tpmimr0;
2044 u8 res_160[12];
2045 u32 tpmcimr0;
2046 u8 res_170[12];
2047 u32 tpmmcmr0;
2048 u8 res_180[12];
2049 u32 tpmnmimr0;
2050 u8 res_190[12];
2051 u32 tmcpmaskcr0;
2052 u32 pctbenr;
2053 u32 pctbclkselr;
2054 u32 tbclkdivr;
2055 u8 res_1ac[4];
2056 u32 ttbhltcr[4];
2057 u32 clpcl10sr;
2058 u32 clpcl10setr;
2059 u32 clpcl10clrr;
2060 u32 clpcl10psr;
2061 u32 cddslpsetr;
2062 u32 cddslpclrr;
2063 u32 cdpwroksetr;
2064 u32 cdpwrokclrr;
2065 u32 cdpwrensr;
2066 u32 cddslsr;
2067 u8 res_1e8[8];
2068 u32 dslpcntcr[8];
2069 u8 res_300[3568];
2070} ccsr_rcpm_t;
2071
2072#define ctbenrl pctbenr
2073
2074#else
2075typedef struct ccsr_rcpm {
2076 u8 res1[4];
2077 u32 cdozsrl;
2078 u8 res2[4];
2079 u32 cdozcrl;
2080 u8 res3[4];
2081 u32 cnapsrl;
2082 u8 res4[4];
2083 u32 cnapcrl;
2084 u8 res5[4];
2085 u32 cdozpsrl;
2086 u8 res6[4];
2087 u32 cdozpcrl;
2088 u8 res7[4];
2089 u32 cwaitsrl;
2090 u8 res8[8];
2091 u32 powmgtcsr;
2092 u8 res9[12];
2093 u32 ippdexpcr0;
2094 u8 res10[12];
2095 u8 res11[4];
2096 u32 cpmimrl;
2097 u8 res12[4];
2098 u32 cpmcimrl;
2099 u8 res13[4];
2100 u32 cpmmcimrl;
2101 u8 res14[4];
2102 u32 cpmnmimrl;
2103 u8 res15[4];
2104 u32 ctbenrl;
2105 u8 res16[4];
2106 u32 ctbclkselrl;
2107 u8 res17[4];
2108 u32 ctbhltcrl;
2109 u8 res18[0xf68];
2110} ccsr_rcpm_t;
2111#endif
2112
2113#else
2114typedef struct ccsr_gur {
2115 u32 porpllsr;
2116#ifdef CONFIG_ARCH_MPC8536
2117#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2118#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2119#elif defined(CONFIG_ARCH_C29X)
2120#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2121#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2122 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2123 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2124#else
2125#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2126#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2127#else
2128#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2129#endif
2130#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2131#endif
2132#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2133#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2134#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2135#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2136 u32 porbmsr;
2137#define MPC85xx_PORBMSR_HA 0x00070000
2138#define MPC85xx_PORBMSR_HA_SHIFT 16
2139#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2140#define PORBMSR_ROMLOC_SPI 0x6
2141#define PORBMSR_ROMLOC_SDHC 0x7
2142#define PORBMSR_ROMLOC_NAND_2K 0x9
2143#define PORBMSR_ROMLOC_NOR 0xf
2144 u32 porimpscr;
2145 u32 pordevsr;
2146#if defined(CONFIG_ARCH_P1023)
2147#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2148#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2149#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2150#else
2151#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2152#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2153#endif
2154#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2155#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2156#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2157#define MPC85xx_PORDEVSR_PCI1 0x00800000
2158#if defined(CONFIG_ARCH_P1023)
2159#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2160#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2161#else
2162#if defined(CONFIG_ARCH_P1010)
2163#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2164#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2165#elif defined(CONFIG_ARCH_BSC9132)
2166#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2167#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2168#elif defined(CONFIG_ARCH_C29X)
2169#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2170#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2171#else
2172#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2173#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2174#endif
2175#endif
2176#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2177#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2178#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2179#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2180#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2181#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2182#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2183#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2184 u32 pordbgmsr;
2185 u32 pordevsr2;
2186#if defined(CONFIG_ARCH_C29X)
2187#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2188#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2189#endif
2190#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
2191
2192#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2193 u8 res1[8];
2194 u32 gpporcr;
2195 u8 res2[12];
2196#if defined(CONFIG_ARCH_MPC8536)
2197 u32 gencfgr;
2198#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2199#else
2200 u32 gpiocr;
2201#endif
2202 u8 res3[12];
2203 u32 gpoutdr;
2204 u8 res4[12];
2205 u32 gpindr;
2206 u8 res5[12];
2207 u32 pmuxcr;
2208#if defined(CONFIG_ARCH_P1010)
2209#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2210#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2211#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2212#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2213#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2214#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2215#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2216#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2217#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2218#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2219#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2220#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2221#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2222#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2223#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2224#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2225#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2226#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2227#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2228#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2229#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2230#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2231#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2232#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2233#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2234#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2235#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2236#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2237#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2238#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2239#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2240#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2241#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2242#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2243#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2244#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2245#define MPC85xx_PMUXCR_SPI_RES 0x00000030
2246#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2247#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2248#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2249#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2250#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2251#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2252#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2253#endif
2254#if defined(CONFIG_ARCH_P1023)
2255#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2256#else
2257#define MPC85xx_PMUXCR_SD_DATA 0x80000000
2258#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2259#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2260#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2261#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2262#define MPC85xx_PMUXCR_QE0 0x00008000
2263#define MPC85xx_PMUXCR_QE1 0x00004000
2264#define MPC85xx_PMUXCR_QE2 0x00002000
2265#define MPC85xx_PMUXCR_QE3 0x00001000
2266#define MPC85xx_PMUXCR_QE4 0x00000800
2267#define MPC85xx_PMUXCR_QE5 0x00000400
2268#define MPC85xx_PMUXCR_QE6 0x00000200
2269#define MPC85xx_PMUXCR_QE7 0x00000100
2270#define MPC85xx_PMUXCR_QE8 0x00000080
2271#define MPC85xx_PMUXCR_QE9 0x00000040
2272#define MPC85xx_PMUXCR_QE10 0x00000020
2273#define MPC85xx_PMUXCR_QE11 0x00000010
2274#define MPC85xx_PMUXCR_QE12 0x00000008
2275#endif
2276#if defined(CONFIG_ARCH_BSC9131)
2277#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2278#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2279#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2280#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2281#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2282#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2283#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2284#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2285#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2286#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2287#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2288#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2289#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2290#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2291#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2292#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2293#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2294#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2295#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2296#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2297#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2298#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2299#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2300#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2301#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2302#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2303#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2304#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2305#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2306#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2307#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2308#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2309#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2310#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2311#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2312#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2313#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2314#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2315#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2316#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2317#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2318#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2319#endif
2320#ifdef CONFIG_ARCH_BSC9132
2321#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2322#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2323#endif
2324#if defined(CONFIG_ARCH_C29X)
2325#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2326#define MPC85xx_PMUXCR_SPI 0x00000000
2327#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2328#endif
2329 u32 pmuxcr2;
2330#if defined(CONFIG_ARCH_P1010)
2331#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2332#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2333#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2334#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2335#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2336#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2337#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2338#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2339#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2340#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2341#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2342#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2343#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2344#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2345#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2346#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2347#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2348#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2349#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2350#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2351#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2352#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2353#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2354#endif
2355#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2356#if defined(CONFIG_ARCH_BSC9131)
2357#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2358#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2359#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2360#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2361#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2362#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2363#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2364#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2365#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2366#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2367#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2368#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2369#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2370#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2371#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2372#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2373#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2374#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2375#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2376#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2377#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2378#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2379#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2380#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2381#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2382#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2383#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2384#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2385#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2386#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2387#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2388#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2389#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2390#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2391#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2392#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2393#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2394#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2395#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2396#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2397#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2398#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2399#endif
2400 u32 pmuxcr3;
2401#if defined(CONFIG_ARCH_BSC9131)
2402#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2403#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2404#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2405#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2406#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2407#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2408#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2409#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2410#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2411#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2412#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2413#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2414#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2415#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2416#endif
2417#ifdef CONFIG_ARCH_BSC9132
2418#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2419#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2420#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2421#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2422#endif
2423 u32 pmuxcr4;
2424#else
2425 u8 res6[8];
2426#endif
2427 u32 devdisr;
2428#define MPC85xx_DEVDISR_PCI1 0x80000000
2429#define MPC85xx_DEVDISR_PCI2 0x40000000
2430#define MPC85xx_DEVDISR_PCIE 0x20000000
2431#define MPC85xx_DEVDISR_LBC 0x08000000
2432#define MPC85xx_DEVDISR_PCIE2 0x04000000
2433#define MPC85xx_DEVDISR_PCIE3 0x02000000
2434#define MPC85xx_DEVDISR_SEC 0x01000000
2435#define MPC85xx_DEVDISR_SRIO 0x00080000
2436#define MPC85xx_DEVDISR_RMSG 0x00040000
2437#define MPC85xx_DEVDISR_DDR 0x00010000
2438#define MPC85xx_DEVDISR_CPU 0x00008000
2439#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2440#define MPC85xx_DEVDISR_TB 0x00004000
2441#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2442#define MPC85xx_DEVDISR_CPU1 0x00002000
2443#define MPC85xx_DEVDISR_TB1 0x00001000
2444#define MPC85xx_DEVDISR_DMA 0x00000400
2445#define MPC85xx_DEVDISR_TSEC1 0x00000080
2446#define MPC85xx_DEVDISR_TSEC2 0x00000040
2447#define MPC85xx_DEVDISR_TSEC3 0x00000020
2448#define MPC85xx_DEVDISR_TSEC4 0x00000010
2449#define MPC85xx_DEVDISR_I2C 0x00000004
2450#define MPC85xx_DEVDISR_DUART 0x00000002
2451 u8 res7[12];
2452 u32 powmgtcsr;
2453 u8 res8[12];
2454 u32 mcpsumr;
2455 u8 res9[12];
2456 u32 pvr;
2457 u32 svr;
2458 u8 res10[8];
2459 u32 rstcr;
2460#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
2461 u8 res11a[12];
2462 u32 iovselsr;
2463 u8 res11b[60];
2464 par_io_t qe_par_io[3];
2465 u8 res11c[1496];
2466#else
2467 u8 res11a[1868];
2468#endif
2469 u32 clkdvdr;
2470 u8 res12[1532];
2471 u32 clkocr;
2472 u8 res13[12];
2473 u32 ddrdllcr;
2474 u8 res14[12];
2475 u32 lbcdllcr;
2476#if defined(CONFIG_ARCH_BSC9131)
2477 u8 res15[12];
2478 u32 halt_req_mask;
2479#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2480 u8 res18[232];
2481#else
2482 u8 res15[248];
2483#endif
2484 u32 lbiuiplldcr0;
2485 u32 lbiuiplldcr1;
2486 u32 ddrioovcr;
2487 u32 tsec12ioovcr;
2488 u32 tsec34ioovcr;
2489 u8 res16[52];
2490 u32 sdhcdcr;
2491 u8 res17[61592];
2492} ccsr_gur_t;
2493#endif
2494
2495#define SDHCDCR_CD_INV 0x80000000
2496
2497#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2498#define MAX_SERDES 4
2499#if defined(CONFIG_ARCH_T1024)
2500#define SRDS_MAX_LANES 4
2501#else
2502#define SRDS_MAX_LANES 8
2503#endif
2504#define SRDS_MAX_BANK 2
2505typedef struct serdes_corenet {
2506 struct {
2507 u32 rstctl;
2508#define SRDS_RSTCTL_RST 0x80000000
2509#define SRDS_RSTCTL_RSTDONE 0x40000000
2510#define SRDS_RSTCTL_RSTERR 0x20000000
2511#define SRDS_RSTCTL_SWRST 0x10000000
2512#define SRDS_RSTCTL_SDEN 0x00000020
2513#define SRDS_RSTCTL_SDRST_B 0x00000040
2514#define SRDS_RSTCTL_PLLRST_B 0x00000080
2515#define SRDS_RSTCTL_RSTERR_SHIFT 29
2516 u32 pllcr0;
2517#define SRDS_PLLCR0_POFF 0x80000000
2518#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2519#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2520#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2521#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2522#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2523#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2524#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2525#define SRDS_PLLCR0_PLL_LCK 0x00800000
2526#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2527#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2528#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2529#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
2530#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2531#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2532#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2533#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2534#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2535#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
2536#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2537#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2538 u32 pllcr1;
2539#define SRDS_PLLCR1_BCAP_EN 0x20000000
2540#define SRDS_PLLCR1_BCAP_OVD 0x10000000
2541#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2542#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2543#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2544#define SRDS_PLLCR1_BYP_CAL 0x02000000
2545 u32 pllsr2;
2546#define SRDS_PLLSR2_BCAP_EN 0x00800000
2547#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2548#define SRDS_PLLSR2_FCAP 0x003F0000
2549#define SRDS_PLLSR2_FCAP_SHIFT 16
2550#define SRDS_PLLSR2_DCBIAS 0x000F0000
2551#define SRDS_PLLSR2_DCBIAS_SHIFT 16
2552 u32 pllcr3;
2553 u32 pllcr4;
2554 u8 res_18[0x20-0x18];
2555 } bank[2];
2556 u8 res_40[0x90-0x40];
2557 u32 srdstcalcr;
2558 u8 res_94[0xa0-0x94];
2559 u32 srdsrcalcr;
2560 u8 res_a4[0xb0-0xa4];
2561 u32 srdsgr0;
2562 u8 res_b4[0xe0-0xb4];
2563 u32 srdspccr0;
2564 u32 srdspccr1;
2565 u32 srdspccr2;
2566 u32 srdspccr3;
2567 u32 srdspccr4;
2568 u8 res_f4[0x100-0xf4];
2569 struct {
2570 u32 lnpssr;
2571 u8 res_104[0x120-0x104];
2572 } srdslnpssr[8];
2573 u8 res_200[0x800-0x200];
2574 struct {
2575 u32 gcr0;
2576 u32 gcr1;
2577 u32 gcr2;
2578 u32 res_80c;
2579 u32 recr0;
2580 u32 res_814;
2581 u32 tecr0;
2582 u32 res_81c;
2583 u32 ttlcr0;
2584 u8 res_824[0x840-0x824];
2585 } lane[8];
2586 u8 res_a00[0x1000-0xa00];
2587} serdes_corenet_t;
2588
2589#else
2590
2591#define SRDS_MAX_LANES 18
2592#define SRDS_MAX_BANK 3
2593typedef struct serdes_corenet {
2594 struct {
2595 u32 rstctl;
2596#define SRDS_RSTCTL_RST 0x80000000
2597#define SRDS_RSTCTL_RSTDONE 0x40000000
2598#define SRDS_RSTCTL_RSTERR 0x20000000
2599#define SRDS_RSTCTL_SDPD 0x00000020
2600 u32 pllcr0;
2601#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2602#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2603#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2604#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2605#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2606#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2607#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2608#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2609#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2610#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2611 u32 pllcr1;
2612#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2613 u32 res[5];
2614 } bank[3];
2615 u32 res1[12];
2616 u32 srdstcalcr;
2617 u32 res2[3];
2618 u32 srdsrcalcr;
2619 u32 res3[3];
2620 u32 srdsgr0;
2621 u32 res4[11];
2622 u32 srdspccr0;
2623 u32 srdspccr1;
2624 u32 srdspccr2;
2625#define SRDS_PCCR2_RST_XGMII1 0x00800000
2626#define SRDS_PCCR2_RST_XGMII2 0x00400000
2627 u32 res5[197];
2628 struct serdes_lane {
2629 u32 gcr0;
2630#define SRDS_GCR0_RRST 0x00400000
2631#define SRDS_GCR0_1STLANE 0x00010000
2632#define SRDS_GCR0_UOTHL 0x00100000
2633 u32 gcr1;
2634#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2635#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2636#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2637#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2638#define SRDS_GCR1_OPAD_CTL 0x04000000
2639 u32 res1[4];
2640 u32 tecr0;
2641#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2642#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2643 u32 res3;
2644 u32 ttlcr0;
2645#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2646#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2647#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2648#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2649#define SRDS_TTLCR0_PM_DIS 0x00004000
2650#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2651 u32 res4[7];
2652 } lane[24];
2653 u32 res6[384];
2654} serdes_corenet_t;
2655#endif
2656
2657enum {
2658 FSL_SRDS_B1_LANE_A = 0,
2659 FSL_SRDS_B1_LANE_B = 1,
2660 FSL_SRDS_B1_LANE_C = 2,
2661 FSL_SRDS_B1_LANE_D = 3,
2662 FSL_SRDS_B1_LANE_E = 4,
2663 FSL_SRDS_B1_LANE_F = 5,
2664 FSL_SRDS_B1_LANE_G = 6,
2665 FSL_SRDS_B1_LANE_H = 7,
2666 FSL_SRDS_B1_LANE_I = 8,
2667 FSL_SRDS_B1_LANE_J = 9,
2668 FSL_SRDS_B2_LANE_A = 16,
2669 FSL_SRDS_B2_LANE_B = 17,
2670 FSL_SRDS_B2_LANE_C = 18,
2671 FSL_SRDS_B2_LANE_D = 19,
2672 FSL_SRDS_B3_LANE_A = 20,
2673 FSL_SRDS_B3_LANE_B = 21,
2674 FSL_SRDS_B3_LANE_C = 22,
2675 FSL_SRDS_B3_LANE_D = 23,
2676};
2677
2678typedef struct ccsr_pme {
2679 u8 res0[0x804];
2680 u32 liodnbr;
2681 u8 res1[0x1f8];
2682 u32 srcidr;
2683 u8 res2[8];
2684 u32 liodnr;
2685 u8 res3[0x1e8];
2686 u32 pm_ip_rev_1;
2687 u32 pm_ip_rev_2;
2688 u8 res4[0x400];
2689} ccsr_pme_t;
2690
2691struct ccsr_pamu {
2692 u32 ppbah;
2693 u32 ppbal;
2694 u32 pplah;
2695 u32 pplal;
2696 u32 spbah;
2697 u32 spbal;
2698 u32 splah;
2699 u32 splal;
2700 u32 obah;
2701 u32 obal;
2702 u32 olah;
2703 u32 olal;
2704};
2705
2706#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2707struct ccsr_raide {
2708 u8 res0[0x543];
2709 u32 liodnbr;
2710 u8 res1[0xab8];
2711 struct {
2712 struct {
2713 u32 cfg0;
2714 u32 cfg1;
2715 u8 res1[0x3f8];
2716 } ring[2];
2717 u8 res[0x800];
2718 } jq[2];
2719};
2720#endif
2721
2722#ifdef CONFIG_SYS_DPAA_RMAN
2723struct ccsr_rman {
2724 u8 res0[0xf64];
2725 u32 mmliodnbr;
2726 u32 mmitar;
2727 u32 mmitdr;
2728 u8 res4[0x1f090];
2729};
2730#endif
2731
2732#ifdef CONFIG_SYS_PMAN
2733struct ccsr_pman {
2734 u8 res_00[0x40];
2735 u32 poes1;
2736 u32 poes2;
2737 u32 poeah;
2738 u32 poeal;
2739 u8 res_50[0x50];
2740 u32 pr1;
2741 u32 pr2;
2742 u8 res_a8[0x8];
2743 u32 pcap;
2744 u8 res_b4[0xc];
2745 u32 pc1;
2746 u32 pc2;
2747 u32 pc3;
2748 u32 pc4;
2749 u32 pc5;
2750 u32 pc6;
2751 u8 res_d8[0x8];
2752 u32 ppa1;
2753 u32 ppa2;
2754 u8 res_e8[0x8];
2755 u32 pics;
2756 u8 res_f4[0xf0c];
2757};
2758#endif
2759
2760#ifdef CONFIG_FSL_CORENET
2761#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2762#ifdef CONFIG_SYS_PMAN
2763#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2764#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2765#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2766#endif
2767#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2768#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2769#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2770#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2771#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2772#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2773
2774
2775#define CONFIG_SYS_OSPR_OFFSET 0x200
2776#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2777#else
2778#define CONFIG_SYS_SFP_OFFSET 0xE8000
2779#endif
2780#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2781#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2782#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2783#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2784#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2785#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2786#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
2787#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2788#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2789#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2790#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2791#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2792#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2793#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2794#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2795#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2796#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2797#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
2798#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2799#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
2800 !defined(CONFIG_ARCH_B4420)
2801#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2802#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2803#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2804#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2805#else
2806#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2807#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2808#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2809#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2810#endif
2811#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2812#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2813#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2814#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2815#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2816#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2817#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2818#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
2819#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
2820#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2821#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2822#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2823#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2824#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2825#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2826#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2827#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2828#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2829#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2830#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2831#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2832#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2833#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2834#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2835#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2836#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2837#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2838#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2839#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2840#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2841#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2842#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2843#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2844#else
2845#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2846#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2847#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2848#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2849#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2850#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2851#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2852#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2853#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2854#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2855#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2856#if defined(CONFIG_ARCH_P2020)
2857#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2858#else
2859#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2860#endif
2861#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2862#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2863#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2864#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2865#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2866#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2867#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2868#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2869#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2870#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
2871#ifdef CONFIG_TSECV2
2872#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2873#elif defined(CONFIG_TSECV2_1)
2874#define CONFIG_SYS_TSEC1_OFFSET 0x10000
2875#else
2876#define CONFIG_SYS_TSEC1_OFFSET 0x24000
2877#endif
2878#define CONFIG_SYS_MDIO1_OFFSET 0x24000
2879#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2880#if defined(CONFIG_ARCH_C29X)
2881#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2882#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
2883#else
2884#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2885#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
2886#endif
2887#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2888#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2889#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
2890#define CONFIG_SYS_SFP_OFFSET 0xE7000
2891#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2892#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2893#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2894#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2895#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2896#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2897#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2898#endif
2899
2900#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2901#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2902#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2903
2904#if defined(CONFIG_ARCH_BSC9132)
2905#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2906#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2907 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2908#endif
2909
2910#define CONFIG_SYS_FSL_CPC_ADDR \
2911 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2912#define CONFIG_SYS_FSL_SCFG_ADDR \
2913 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
2914#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
2915 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
2916#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
2917 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
2918#define CONFIG_SYS_FSL_QMAN_ADDR \
2919 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2920#define CONFIG_SYS_FSL_BMAN_ADDR \
2921 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2922#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2923 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2924#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
2925 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
2926#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
2927 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
2928#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2929 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2930#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2931 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2932#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2933 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2934#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2935 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2936#define CONFIG_SYS_MPC85xx_ECM_ADDR \
2937 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2938#define CONFIG_SYS_FSL_DDR_ADDR \
2939 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
2940#define CONFIG_SYS_FSL_DDR2_ADDR \
2941 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
2942#define CONFIG_SYS_FSL_DDR3_ADDR \
2943 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
2944#define CONFIG_SYS_LBC_ADDR \
2945 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2946#define CONFIG_SYS_IFC_ADDR \
2947 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
2948#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2949 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2950#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2951 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2952#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2953 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2954#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2955 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2956#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2957 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2958#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2959 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2960#define CONFIG_SYS_MPC85xx_L2_ADDR \
2961 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2962#define CONFIG_SYS_MPC85xx_DMA_ADDR \
2963 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2964#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2965 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
2966#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
2967 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
2968#define CONFIG_SYS_MPC85xx_CPM_ADDR \
2969 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
2970#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
2971 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
2972#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2973 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
2974#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
2975 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
2976#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
2977 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
2978#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
2979 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
2980#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
2981 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
2982#define CONFIG_SYS_MPC85xx_USB1_ADDR \
2983 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
2984#define CONFIG_SYS_MPC85xx_USB2_ADDR \
2985 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
2986#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
2987 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
2988#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
2989 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
2990#define CONFIG_SYS_FSL_SEC_ADDR \
2991 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
2992#define CONFIG_SYS_FSL_JR0_ADDR \
2993 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
2994#define CONFIG_SYS_FSL_FM1_ADDR \
2995 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
2996#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
2997 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
2998#define CONFIG_SYS_FSL_FM2_ADDR \
2999 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3000#define CONFIG_SYS_FSL_SRIO_ADDR \
3001 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3002#define CONFIG_SYS_PAMU_ADDR \
3003 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
3004
3005#define CONFIG_SYS_PCI1_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3007#define CONFIG_SYS_PCI2_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3009#define CONFIG_SYS_PCIE1_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3011#define CONFIG_SYS_PCIE2_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3013#define CONFIG_SYS_PCIE3_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3015#define CONFIG_SYS_PCIE4_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3017
3018#define CONFIG_SYS_SFP_ADDR \
3019 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
3020
3021#define CONFIG_SYS_SEC_MON_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
3023
3024#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3025#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3026
3027#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3028struct ccsr_cluster_l2 {
3029 u32 l2csr0;
3030 u32 l2csr1;
3031 u32 l2cfg0;
3032 u8 res_0c[500];
3033 u32 l2pir0;
3034 u8 res_204[4];
3035 u32 l2par0;
3036 u32 l2pwr0;
3037 u32 l2pir1;
3038 u8 res_214[4];
3039 u32 l2par1;
3040 u32 l2pwr1;
3041 u32 u2pir2;
3042 u8 res_224[4];
3043 u32 l2par2;
3044 u32 l2pwr2;
3045 u32 l2pir3;
3046 u8 res_234[4];
3047 u32 l2par3;
3048 u32 l2pwr3;
3049 u32 l2pir4;
3050 u8 res244[4];
3051 u32 l2par4;
3052 u32 l2pwr4;
3053 u32 l2pir5;
3054 u8 res_254[4];
3055 u32 l2par5;
3056 u32 l2pwr5;
3057 u32 l2pir6;
3058 u8 res_264[4];
3059 u32 l2par6;
3060 u32 l2pwr6;
3061 u32 l2pir7;
3062 u8 res274[4];
3063 u32 l2par7;
3064 u32 l2pwr7;
3065 u8 res_280[0xb80];
3066 u32 l2errinjhi;
3067 u32 l2errinjlo;
3068 u32 l2errinjctl;
3069 u8 res_e0c[20];
3070 u32 l2captdatahi;
3071 u32 l2captdatalo;
3072 u32 l2captecc;
3073 u8 res_e2c[20];
3074 u32 l2errdet;
3075 u32 l2errdis;
3076 u32 l2errinten;
3077 u32 l2errattr;
3078 u32 l2erreaddr;
3079 u32 l2erraddr;
3080 u32 l2errctl;
3081};
3082#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3083 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3084#endif
3085
3086#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3087struct dcsr_dcfg_regs {
3088 u8 res_0[0x520];
3089 u32 ecccr1;
3090#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3091#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3092 u8 res_524[0x1000 - 0x524];
3093};
3094
3095#define CONFIG_SYS_MPC85xx_SCFG \
3096 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
3097#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3098
3099struct ccsr_scfg {
3100 u32 dpslpcr;
3101 u32 usb1dpslpcsr;
3102 u32 usb2dpslpcsr;
3103 u32 fmclkdpslpcr;
3104 u32 res1[4];
3105 u32 esgmiiselcr;
3106 u32 res2;
3107 u32 pixclkcr;
3108 u32 res3[245];
3109 u32 qeioclkcr;
3110 u32 emiiocr;
3111 u32 sdhciovselcr;
3112 u32 qmifrstcr;
3113 u32 res4[60];
3114 u32 sparecr[8];
3115};
3116#endif
3117