1menu "RISC-V architecture"
2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
13
14config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
16
17config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
19
20config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
22
23config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
25 select SYS_CACHE_SHIFT_6
26
27config TARGET_SIPEED_MAIX
28 bool "Support Sipeed Maix Board"
29 select SYS_CACHE_SHIFT_6
30
31config TARGET_OPENPITON_RISCV64
32 bool "Support RISC-V cores on OpenPiton SoC"
33
34endchoice
35
36config SYS_ICACHE_OFF
37 bool "Do not enable icache"
38 help
39 Do not enable instruction cache in U-Boot.
40
41config SPL_SYS_ICACHE_OFF
42 bool "Do not enable icache in SPL"
43 depends on SPL
44 default SYS_ICACHE_OFF
45 help
46 Do not enable instruction cache in SPL.
47
48config SYS_DCACHE_OFF
49 bool "Do not enable dcache"
50 help
51 Do not enable data cache in U-Boot.
52
53config SPL_SYS_DCACHE_OFF
54 bool "Do not enable dcache in SPL"
55 depends on SPL
56 default SYS_DCACHE_OFF
57 help
58 Do not enable data cache in SPL.
59
60
61source "board/AndesTech/ax25-ae350/Kconfig"
62source "board/emulation/qemu-riscv/Kconfig"
63source "board/microchip/mpfs_icicle/Kconfig"
64source "board/sifive/unleashed/Kconfig"
65source "board/sifive/unmatched/Kconfig"
66source "board/openpiton/riscv64/Kconfig"
67source "board/sipeed/maix/Kconfig"
68
69
70source "arch/riscv/cpu/ax25/Kconfig"
71source "arch/riscv/cpu/fu540/Kconfig"
72source "arch/riscv/cpu/fu740/Kconfig"
73source "arch/riscv/cpu/generic/Kconfig"
74
75
76
77choice
78 prompt "Base ISA"
79 default ARCH_RV32I
80
81config ARCH_RV32I
82 bool "RV32I"
83 select 32BIT
84 help
85 Choose this option to target the RV32I base integer instruction set.
86
87config ARCH_RV64I
88 bool "RV64I"
89 select 64BIT
90 select PHYS_64BIT
91 help
92 Choose this option to target the RV64I base integer instruction set.
93
94endchoice
95
96choice
97 prompt "Code Model"
98 default CMODEL_MEDLOW
99
100config CMODEL_MEDLOW
101 bool "medium low code model"
102 help
103 U-Boot and its statically defined symbols must lie within a single 2 GiB
104 address range and must lie between absolute addresses -2 GiB and +2 GiB.
105
106config CMODEL_MEDANY
107 bool "medium any code model"
108 help
109 U-Boot and its statically defined symbols must be within any single 2 GiB
110 address range.
111
112endchoice
113
114choice
115 prompt "Run Mode"
116 default RISCV_MMODE
117
118config RISCV_MMODE
119 bool "Machine"
120 help
121 Choose this option to build U-Boot for RISC-V M-Mode.
122
123config RISCV_SMODE
124 bool "Supervisor"
125 help
126 Choose this option to build U-Boot for RISC-V S-Mode.
127
128endchoice
129
130choice
131 prompt "SPL Run Mode"
132 default SPL_RISCV_MMODE
133 depends on SPL
134
135config SPL_RISCV_MMODE
136 bool "Machine"
137 help
138 Choose this option to build U-Boot SPL for RISC-V M-Mode.
139
140config SPL_RISCV_SMODE
141 bool "Supervisor"
142 help
143 Choose this option to build U-Boot SPL for RISC-V S-Mode.
144
145endchoice
146
147config RISCV_ISA_C
148 bool "Emit compressed instructions"
149 default y
150 help
151 Adds "C" to the ISA subsets that the toolchain is allowed to emit
152 when building U-Boot, which results in compressed instructions in the
153 U-Boot binary.
154
155config RISCV_ISA_A
156 def_bool y
157
158config 32BIT
159 bool
160
161config 64BIT
162 bool
163
164config DMA_ADDR_T_64BIT
165 bool
166 default y if 64BIT
167
168config SIFIVE_CLINT
169 bool
170 depends on RISCV_MMODE
171 help
172 The SiFive CLINT block holds memory-mapped control and status registers
173 associated with software and timer interrupts.
174
175config SPL_SIFIVE_CLINT
176 bool
177 depends on SPL_RISCV_MMODE
178 help
179 The SiFive CLINT block holds memory-mapped control and status registers
180 associated with software and timer interrupts.
181
182config SIFIVE_CACHE
183 bool
184 help
185 This enables the operations to configure SiFive cache
186
187config ANDES_PLIC
188 bool
189 depends on RISCV_MMODE || SPL_RISCV_MMODE
190 select REGMAP
191 select SYSCON
192 select SPL_REGMAP if SPL
193 select SPL_SYSCON if SPL
194 help
195 The Andes PLIC block holds memory-mapped claim and pending registers
196 associated with software interrupt.
197
198config SYS_MALLOC_F_LEN
199 default 0x1000
200
201config SMP
202 bool "Symmetric Multi-Processing"
203 depends on SBI_V01 || !RISCV_SMODE
204 help
205 This enables support for systems with more than one CPU. If
206 you say N here, U-Boot will run on single and multiprocessor
207 machines, but will use only one CPU of a multiprocessor
208 machine. If you say Y here, U-Boot will run on many, but not
209 all, single processor machines.
210
211config SPL_SMP
212 bool "Symmetric Multi-Processing in SPL"
213 depends on SPL && SPL_RISCV_MMODE
214 default y
215 help
216 This enables support for systems with more than one CPU in SPL.
217 If you say N here, U-Boot SPL will run on single and multiprocessor
218 machines, but will use only one CPU of a multiprocessor
219 machine. If you say Y here, U-Boot SPL will run on many, but not
220 all, single processor machines.
221
222config NR_CPUS
223 int "Maximum number of CPUs (2-32)"
224 range 2 32
225 depends on SMP || SPL_SMP
226 default 8
227 help
228 On multiprocessor machines, U-Boot sets up a stack for each CPU.
229 Stack memory is pre-allocated. U-Boot must therefore know the
230 maximum number of CPUs that may be present.
231
232config SBI
233 bool
234 default y if RISCV_SMODE || SPL_RISCV_SMODE
235
236choice
237 prompt "SBI support"
238 default SBI_V02
239
240config SBI_V01
241 bool "SBI v0.1 support"
242 depends on SBI
243 help
244 This config allows kernel to use SBI v0.1 APIs. This will be
245 deprecated in future once legacy M-mode software are no longer in use.
246
247config SBI_V02
248 bool "SBI v0.2 support"
249 depends on SBI
250 help
251 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
252 scalable and extendable to handle future needs for RISC-V supervisor
253 interfaces. For example, with SBI v0.2 HSM extension, only a single
254 hart need to boot and enter operating system. The booting hart can
255 bring up secondary harts one by one afterwards.
256
257 Choose this option if OpenSBI v0.7 or above release is used together
258 with U-Boot.
259
260endchoice
261
262config SBI_IPI
263 bool
264 depends on SBI
265 default y if RISCV_SMODE || SPL_RISCV_SMODE
266 depends on SMP
267
268config XIP
269 bool "XIP mode"
270 help
271 XIP (eXecute In Place) is a method for executing code directly
272 from a NOR flash memory without copying the code to ram.
273 Say yes here if U-Boot boots from flash directly.
274
275config SHOW_REGS
276 bool "Show registers on unhandled exception"
277
278config RISCV_PRIV_1_9
279 bool "Use version 1.9 of the RISC-V priviledged specification"
280 help
281 Older versions of the RISC-V priviledged specification had
282 separate counter enable CSRs for each privilege mode. Writing
283 to the unified mcounteren CSR on a processor implementing the
284 old specification will result in an illegal instruction
285 exception. In addition to counter CSR changes, the way virtual
286 memory is configured was also changed.
287
288config STACK_SIZE_SHIFT
289 int
290 default 14
291
292config OF_BOARD_FIXUP
293 default y if OF_SEPARATE && RISCV_SMODE
294
295menu "Use assembly optimized implementation of memory routines"
296
297config USE_ARCH_MEMCPY
298 bool "Use an assembly optimized implementation of memcpy"
299 default y
300 help
301 Enable the generation of an optimized version of memcpy.
302 Such an implementation may be faster under some conditions
303 but may increase the binary size.
304
305config SPL_USE_ARCH_MEMCPY
306 bool "Use an assembly optimized implementation of memcpy for SPL"
307 default y if USE_ARCH_MEMCPY
308 depends on SPL
309 help
310 Enable the generation of an optimized version of memcpy.
311 Such an implementation may be faster under some conditions
312 but may increase the binary size.
313
314config TPL_USE_ARCH_MEMCPY
315 bool "Use an assembly optimized implementation of memcpy for TPL"
316 default y if USE_ARCH_MEMCPY
317 depends on TPL
318 help
319 Enable the generation of an optimized version of memcpy.
320 Such an implementation may be faster under some conditions
321 but may increase the binary size.
322
323config USE_ARCH_MEMMOVE
324 bool "Use an assembly optimized implementation of memmove"
325 default y
326 help
327 Enable the generation of an optimized version of memmove.
328 Such an implementation may be faster under some conditions
329 but may increase the binary size.
330
331config SPL_USE_ARCH_MEMMOVE
332 bool "Use an assembly optimized implementation of memmove for SPL"
333 default y if USE_ARCH_MEMCPY
334 depends on SPL
335 help
336 Enable the generation of an optimized version of memmove.
337 Such an implementation may be faster under some conditions
338 but may increase the binary size.
339
340config TPL_USE_ARCH_MEMMOVE
341 bool "Use an assembly optimized implementation of memmove for TPL"
342 default y if USE_ARCH_MEMCPY
343 depends on TPL
344 help
345 Enable the generation of an optimized version of memmove.
346 Such an implementation may be faster under some conditions
347 but may increase the binary size.
348
349config USE_ARCH_MEMSET
350 bool "Use an assembly optimized implementation of memset"
351 default y
352 help
353 Enable the generation of an optimized version of memset.
354 Such an implementation may be faster under some conditions
355 but may increase the binary size.
356
357config SPL_USE_ARCH_MEMSET
358 bool "Use an assembly optimized implementation of memset for SPL"
359 default y if USE_ARCH_MEMSET
360 depends on SPL
361 help
362 Enable the generation of an optimized version of memset.
363 Such an implementation may be faster under some conditions
364 but may increase the binary size.
365
366config TPL_USE_ARCH_MEMSET
367 bool "Use an assembly optimized implementation of memset for TPL"
368 default y if USE_ARCH_MEMSET
369 depends on TPL
370 help
371 Enable the generation of an optimized version of memset.
372 Such an implementation may be faster under some conditions
373 but may increase the binary size.
374
375endmenu
376
377endmenu
378
