LXR uboot/arch/riscv/lib/sifive

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
   4 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
   5 *
   6 * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
   7 * The CLINT block holds memory-mapped control and status registers
   8 * associated with software and timer interrupts.
   9 */
  10
  11#include <common.h>
  12#include <dm.h>
  13#include <asm/global_data.h>
  14#include <asm/io.h>
  15#include <asm/smp.h>
  16#include <linux/err.h>
  17
  18/* MSIP registers */
  19#define MSIP_REG(base, hart)            ((ulong)(base) + (hart) * 4)
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23int riscv_init_ipi(void)
  24{
  25        int ret;
  26        struct udevice *dev;
  27
  28        ret = uclass_get_device_by_driver(UCLASS_TIMER,
  29                                          DM_DRIVER_GET(sifive_clint), &dev);
  30        if (ret)
  31                return ret;
  32
  33        gd->arch.clint = dev_read_addr_ptr(dev);
  34        if (!gd->arch.clint)
  35                return -EINVAL;
  36
  37        return 0;
  38}
  39
  40int riscv_send_ipi(int hart)
  41{
  42        writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
  43
  44        return 0;
  45}
  46
  47int riscv_clear_ipi(int hart)
  48{
  49        writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
  50
  51        return 0;
  52}
  53
  54int riscv_get_ipi(int hart, int *pending)
  55{
  56        *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
  57
  58        return 0;
  59}
  60