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8#ifndef _ASM_CPU_SH7734_H_
9#define _ASM_CPU_SH7734_H_
10
11#define CCR 0xFF00001C
12
13#define CACHE_OC_NUM_WAYS 4
14#define CCR_CACHE_INIT 0x0000090d
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16
17#define SCIF0_BASE 0xFFE40000
18#define SCIF1_BASE 0xFFE41000
19#define SCIF2_BASE 0xFFE42000
20#define SCIF3_BASE 0xFFE43000
21#define SCIF4_BASE 0xFFE44000
22#define SCIF5_BASE 0xFFE45000
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24
25#define TMU_BASE 0xFFD80000
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27
28#define PMMR (0xFFFC0000)
29#define MODESEL0 (0xFFFC004C)
30#define MODESEL2 (MODESEL0 + 0x4)
31#define MODESEL2_INIT (0x00003000)
32
33#define IPSR0 (0xFFFC001C)
34#define IPSR1 (IPSR0 + 0x4)
35#define IPSR2 (IPSR0 + 0x8)
36#define IPSR3 (IPSR0 + 0xC)
37#define IPSR4 (IPSR0 + 0x10)
38#define IPSR5 (IPSR0 + 0x14)
39#define IPSR6 (IPSR0 + 0x18)
40#define IPSR7 (IPSR0 + 0x1C)
41#define IPSR8 (IPSR0 + 0x20)
42#define IPSR9 (IPSR0 + 0x24)
43#define IPSR10 (IPSR0 + 0x28)
44#define IPSR11 (IPSR0 + 0x2C)
45
46#define GPSR0 (0xFFFC0004)
47#define GPSR1 (GPSR0 + 0x4)
48#define GPSR2 (GPSR0 + 0x8)
49#define GPSR3 (GPSR0 + 0xC)
50#define GPSR4 (GPSR0 + 0x10)
51#define GPSR5 (GPSR0 + 0x14)
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53
54#endif
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