LXR uboot/arch/x86/cpu/intel

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Special driver to handle of-platdata
   4 *
   5 * Copyright 2019 Google LLC
   6 *
   7 * Some code from coreboot lpss.c
   8 */
   9
  10#include <common.h>
  11#include <dm.h>
  12#include <pci.h>
  13#include <asm/io.h>
  14#include <asm/lpss.h>
  15
  16enum {
  17        LPSS_RESET_CTL_REG      = 0x204,
  18
  19        /*
  20         * Bit 1:0 controls LPSS controller reset.
  21         *
  22         * 00 ->LPSS Host Controller is in reset (Reset Asserted)
  23         * 01/10 ->Reserved
  24         * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
  25         */
  26        LPSS_CNT_RST_RELEASE    = 3,
  27
  28        /* Power management control and status register */
  29        PME_CTRL_STATUS         = 0x84,
  30
  31        /* Bit 1:0 Powerstate, controls D0 and D3 state */
  32        POWER_STATE_MASK        = 3,
  33};
  34
  35/* Take controller out of reset */
  36void lpss_reset_release(void *regs)
  37{
  38        writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
  39}
  40
  41void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state)
  42{
  43        dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
  44}
  45