1/* SPDX-License-Identifier: Intel */ 2/* 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * Copyright 2019 Google LLC 5 */ 6 7#ifndef __ASM_ARCH_FSP_M_UDP_H 8#define __ASM_ARCH_FSP_M_UDP_H 9 10#ifndef __ASSEMBLY__ 11#include <asm/fsp2/fsp_api.h> 12 13#define FSP_DRAM_CHANNELS 4 14 15struct __packed fspm_arch_upd { 16 u8 revision; 17 u8 reserved[3]; 18 void *nvs_buffer_ptr; 19 void *stack_base; 20 u32 stack_size; 21 u32 boot_loader_tolum_size; 22 u32 boot_mode; 23 u8 reserved1[8]; 24}; 25 26struct __packed fsp_ram_channel { 27 u8 rank_enable; 28 u8 device_width; 29 u8 dram_density; 30 u8 option; 31 u8 odt_config; 32 u8 tristate_clk1; 33 u8 mode2_n; 34 u8 odt_levels; 35}; 36 37/** 38 * struct fsp_m_config - FSP-M configuration 39 * 40 * Note that headers precede this and are 64 bytes long. The hex offsets 41 * mentioned in this file are relative to the start of the header, the same 42 * convention used in Intel's APL FSP header file. 43 */ 44struct __packed fsp_m_config { 45 /* 0x40 */ 46 u32 serial_debug_port_address; 47 u8 serial_debug_port_type; 48 u8 serial_debug_port_device; 49 u8 serial_debug_port_stride_size; 50 u8 mrc_fast_boot; 51 u8 igd; 52 u8 igd_dvmt50_pre_alloc; 53 u8 igd_aperture_size; 54 u8 gtt_size; 55 u8 primary_video_adaptor; 56 u8 package; 57 u8 profile; 58 u8 memory_down; 59 60 /* 0x50 */ 61 u8 ddr3_l_page_size; 62 u8 ddr3_lasr; 63 u8 scrambler_support; 64 u8 interleaved_mode; 65 u16 channel_hash_mask; 66 u16 slice_hash_mask; 67 u8 channels_slices_enable; 68 u8 min_ref_rate2x_enable; 69 u8 dual_rank_support_enable; 70 u8 rmt_mode; 71 u16 memory_size_limit; 72 u16 low_memory_max_value; 73 74 /* 0x60 */ 75 u16 high_memory_max_value; 76 u8 disable_fast_boot; 77 u8 dimm0_spd_address; 78 u8 dimm1_spd_address; 79 struct fsp_ram_channel chan[FSP_DRAM_CHANNELS]; 80 u8 rmt_check_run; 81 u16 rmt_margin_check_scale_high_threshold; 82 u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32]; 83 u32 msg_level_mask; 84 u8 unused_upd_space0[4]; 85 86 /* 0x110 */ 87 u8 pre_mem_gpio_table_pin_num[4]; 88 u32 pre_mem_gpio_table_ptr; 89 u8 pre_mem_gpio_table_entry_num; 90 u8 enhance_port8xh_decoding; 91 u8 spd_write_enable; 92 u8 mrc_data_saving; 93 u32 oem_loading_base; 94 95 /* 0x120 */ 96 u8 oem_file_name[16]; 97 98 /* 0x130 */ 99 void *mrc_boot_data_ptr; 100 u8 e_mmc_trace_len; 101 u8 skip_cse_rbp; 102 u8 npk_en; 103 u8 fw_trace_en; 104 u8 fw_trace_destination; 105 u8 recover_dump; 106 u8 msc0_wrap; 107 u8 msc1_wrap; 108 u32 msc0_size; 109 110 /* 0x140 */ 111 u32 msc1_size; 112 u8 pti_mode; 113 u8 pti_training; 114 u8 pti_speed; 115 u8 punit_mlvl; 116 u8 pmc_mlvl; 117 u8 sw_trace_en; 118 u8 periodic_retraining_disable; 119 u8 enable_reset_system; 120 u8 enable_s3_heci2; 121 u8 unused_upd_space1[3]; 122 123 /* 0x150 */ 124 void *variable_nvs_buffer_ptr; 125 u64 start_timer_ticker_of_pfet_assert; 126 u8 rt_en; 127 u8 skip_pcie_power_sequence; 128 u8 reserved_fspm_upd[2]; 129}; 130 131/** FSP-M UPD Configuration */ 132struct __packed fspm_upd { 133 struct fsp_upd_header header; 134 struct fspm_arch_upd arch; 135 struct fsp_m_config config; 136 u8 unused_upd_space2[158]; 137 u16 upd_terminator; 138}; 139#endif 140 141#define SERIAL_DEBUG_PORT_TYPE_NONE 0 142#define SERIAL_DEBUG_PORT_TYPE_IO 1 143#define SERIAL_DEBUG_PORT_TYPE_MMIO 2 144 145#define SERIAL_DEBUG_PORT_DEVICE_UART0 0 146#define SERIAL_DEBUG_PORT_DEVICE_UART1 1 147#define SERIAL_DEBUG_PORT_DEVICE_UART2 2 148#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3 149 150#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0 151#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2 152 153#define IGD_DVMT_50_PRE_ALLOC_64M 0x02 154#define IGD_DVMT_50_PRE_ALLOC_96M 0x03 155#define IGD_DVMT_50_PRE_ALLOC_128M 0x04 156#define IGD_DVMT_50_PRE_ALLOC_160M 0x05 157#define IGD_DVMT_50_PRE_ALLOC_192M 0x06 158#define IGD_DVMT_50_PRE_ALLOC_224M 0x07 159#define IGD_DVMT_50_PRE_ALLOC_256M 0x08 160#define IGD_DVMT_50_PRE_ALLOC_288M 0x09 161#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a 162#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b 163#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c 164#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d 165#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e 166#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f 167#define IGD_DVMT_50_PRE_ALLOC_512M 0x10 168 169#define IGD_APERTURE_SIZE_128M 0x1 170#define IGD_APERTURE_SIZE_256M 0x2 171#define IGD_APERTURE_SIZE_512M 0x3 172 173#define GTT_SIZE_2M 1 174#define GTT_SIZE_4M 2 175#define GTT_SIZE_8M 3 176 177#define PRIMARY_VIDEO_ADAPTER_AUTO 0 178#define PRIMARY_VIDEO_ADAPTER_IGD 2 179#define PRIMARY_VIDEO_ADAPTER_PCI 3 180 181#define PACKAGE_SODIMM 0 182#define PACKAGE_BGA 1 183#define PACKAGE_BGA_MIRRORED 2 184#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3 185 186#define PROFILE_WIO2_800_7_8_8 0x1 187#define PROFILE_WIO2_1066_9_10_10 0x2 188#define PROFILE_LPDDR3_1066_8_10_10 0x3 189#define PROFILE_LPDDR3_1333_10_12_12 0x4 190#define PROFILE_LPDDR3_1600_12_15_15 0x5 191#define PROFILE_LPDDR3_1866_14_17_17 0x6 192#define PROFILE_LPDDR3_2133_16_20_20 0x7 193#define PROFILE_LPDDR4_1066_10_10_10 0x8 194#define PROFILE_LPDDR4_1600_14_15_15 0x9 195#define PROFILE_LPDDR4_2133_20_20_20 0xa 196#define PROFILE_LPDDR4_2400_24_22_22 0xb 197#define PROFILE_LPDDR4_2666_24_24_24 0xc 198#define PROFILE_LPDDR4_2933_28_27_27 0xd 199#define PROFILE_LPDDR4_3200_28_29_29 0xe 200#define PROFILE_DDR3_1066_6_6_6 0xf 201#define PROFILE_DDR3_1066_7_7_7 0x10 202#define PROFILE_DDR3_1066_8_8_8 0x11 203#define PROFILE_DDR3_1333_7_7_7 0x12 204#define PROFILE_DDR3_1333_8_8_8 0x13 205#define PROFILE_DDR3_1333_9_9_9 0x14 206#define PROFILE_DDR3_1333_10_10_10 0x15 207#define PROFILE_DDR3_1600_8_8_8 0x16 208#define PROFILE_DDR3_1600_9_9_9 0x17 209#define PROFILE_DDR3_1600_10_10_10 0x18 210#define PROFILE_DDR3_1600_11_11_11 0x19 211#define PROFILE_DDR3_1866_10_10_10 0x1a 212#define PROFILE_DDR3_1866_11_11_11 0x1b 213#define PROFILE_DDR3_1866_12_12_12 0x1c 214#define PROFILE_DDR3_1866_13_13_13 0x1d 215#define PROFILE_DDR3_2133_11_11_11 0x1e 216#define PROFILE_DDR3_2133_12_12_12 0x1f 217#define PROFILE_DDR3_2133_13_13_13 0x20 218#define PROFILE_DDR3_2133_14_14_14 0x21 219#define PROFILE_DDR4_1333_10_10_10 0x22 220#define PROFILE_DDR4_1600_10_10_10 0x23 221#define PROFILE_DDR4_1600_11_11_11 0x24 222#define PROFILE_DDR4_1600_12_12_12 0x25 223#define PROFILE_DDR4_1866_12_12_12 0x26 224#define PROFILE_DDR4_1866_13_13_13 0x27 225#define PROFILE_DDR4_1866_14_14_14 0x28 226#define PROFILE_DDR4_2133_14_14_14 0x29 227#define PROFILE_DDR4_2133_15_15_15 0x2a 228#define PROFILE_DDR4_2133_16_16_16 0x2b 229#define PROFILE_DDR4_2400_15_15_15 0x2c 230#define PROFILE_DDR4_2400_16_16_16 0x2d 231#define PROFILE_DDR4_2400_17_17_17 0x2e 232#define PROFILE_DDR4_2400_18_18_18 0x2f 233 234#define MEMORY_DOWN_NO 0 235#define MEMORY_DOWN_YES 1 236#define MEMORY_DOWN_MD_SODIMM 2 237#define MEMORY_DOWN_LPDDR4 3 238 239#define DDR3L_PAGE_SIZE_1KB 1 240#define DDR3L_PAGE_SIZE_2KB 2 241 242#define INTERLEAVED_MODE_DISABLE 0 243#define INTERLEAVED_MODE_ENABLE 2 244 245#define RMT_MODE_DISABLE 0 246#define RMT_MODE_ENABLE 3 247 248#define CHX_DEVICE_WIDTH_X8 0 249#define CHX_DEVICE_WIDTH_X16 1 250#define CHX_DEVICE_WIDTH_X32 2 251#define CHX_DEVICE_WIDTH_X64 3 252 253#define CHX_DEVICE_DENSITY_4GB 0 254#define CHX_DEVICE_DENSITY_6GB 1 255#define CHX_DEVICE_DENSITY_8GB 2 256#define CHX_DEVICE_DENSITY_12GB 3 257#define CHX_DEVICE_DENSITY_16GB 4 258#define CHX_DEVICE_DENSITY_2GB 5 259 260#define CHX_OPTION_RANK_INTERLEAVING 0x1 261#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2 262#define CHX_OPTION_CH1_CLK_DISABLE 0x4 263#define CHX_OPTION_ADDRESS_MAP_2KB 0x10 264 265#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1 266#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2 267#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10 268 269#define CHX_MODE2N_AUTO 0 270#define CHX_MODE2N_FORCE 1 271 272#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0 273#define CHX_ODT_LEVELS_HELD_HIGH 0x1 274 275#define NPK_EN_DISABLE 0 276#define NPK_EN_ENABLE 1 277#define NPK_EN_DEBUGGER 2 278#define NPK_EN_AUTO 3 279 280#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1 281#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2 282#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3 283#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4 284 285#define MSC_X_WRAP_0 0 286#define MSC_X_WRAP_1 1 287 288#define MSC_X_SIZE_0M 0 289#define MSC_X_SIZE_1M 1 290#define MSC_X_SIZE_8M 2 291#define MSC_X_SIZE_64M 3 292#define MSC_X_SIZE_128M 4 293#define MSC_X_SIZE_256M 5 294#define MSC_X_SIZE_512M 6 295#define MSC_X_SIZE_1GB 7 296 297#define PTI_MODE_0 0 298#define PTI_MODE_x4 1 299#define PTI_MODE_x8 2 300#define PTI_MODE_x12 3 301#define PTI_MODE_x16 4 302 303#define PTI_SPEED_FULL 0 304#define PTI_SPEED_HALF 1 305#define PTI_SPEED_QUARTER 2 306 307#endif 308