1/* SPDX-License-Identifier: Intel */ 2/* 3 * Copyright (C) 2015, Intel Corporation 4 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 5 */ 6 7#ifndef __FSP_VPD_H__ 8#define __FSP_VPD_H__ 9 10#include <stddef.h> 11 12struct __packed memory_upd { 13 u64 signature; /* Offset 0x0020 */ 14 u8 revision; /* Offset 0x0028 */ 15 u8 unused2[7]; /* Offset 0x0029 */ 16 u16 mrc_init_tseg_size; /* Offset 0x0030 */ 17 u16 mrc_init_mmio_size; /* Offset 0x0032 */ 18 u8 mrc_init_spd_addr1; /* Offset 0x0034 */ 19 u8 mrc_init_spd_addr2; /* Offset 0x0035 */ 20 u8 mem_ch0_config; /* Offset 0x0036 */ 21 u8 mem_ch1_config; /* Offset 0x0037 */ 22 u32 memory_spd_ptr; /* Offset 0x0038 */ 23 u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */ 24 u8 aperture_size; /* Offset 0x003d */ 25 u8 gtt_size; /* Offset 0x003e */ 26 u8 legacy_seg_decode; /* Offset 0x003f */ 27 u8 enable_dvfs; /* Offset 0x0040 */ 28 u8 memory_type; /* Offset 0x0041 */ 29 u8 enable_ca_mirror; /* Offset 0x0042 */ 30 u8 reserved[189]; /* Offset 0x0043 */ 31}; 32 33struct gpio_family { 34 u32 confg; 35 u32 confg_changes; 36 u32 misc; 37 u32 mmio_addr; 38 wchar_t *name; 39}; 40 41struct gpio_pad { 42 u32 confg0; 43 u32 confg0_changes; 44 u32 confg1; 45 u32 confg1_changes; 46 u32 community; 47 u32 mmio_addr; 48 wchar_t *name; 49 u32 misc; 50}; 51 52struct __packed silicon_upd { 53 u64 signature; /* Offset 0x0100 */ 54 u8 revision; /* Offset 0x0108 */ 55 u8 unused3[7]; /* Offset 0x0109 */ 56 u8 sdcard_mode; /* Offset 0x0110 */ 57 u8 enable_hsuart0; /* Offset 0x0111 */ 58 u8 enable_hsuart1; /* Offset 0x0112 */ 59 u8 enable_azalia; /* Offset 0x0113 */ 60 struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */ 61 u8 enable_sata; /* Offset 0x0118 */ 62 u8 enable_xhci; /* Offset 0x0119 */ 63 u8 lpe_mode; /* Offset 0x011a */ 64 u8 enable_dma0; /* Offset 0x011b */ 65 u8 enable_dma1; /* Offset 0x011c */ 66 u8 enable_i2c0; /* Offset 0x011d */ 67 u8 enable_i2c1; /* Offset 0x011e */ 68 u8 enable_i2c2; /* Offset 0x011f */ 69 u8 enable_i2c3; /* Offset 0x0120 */ 70 u8 enable_i2c4; /* Offset 0x0121 */ 71 u8 enable_i2c5; /* Offset 0x0122 */ 72 u8 enable_i2c6; /* Offset 0x0123 */ 73 u32 graphics_config_ptr; /* Offset 0x0124 */ 74 struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */ 75 struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */ 76 u8 disable_punit_pwr_config; /* Offset 0x0130 */ 77 u8 chv_svid_config; /* Offset 0x0131 */ 78 u8 disable_dptf; /* Offset 0x0132 */ 79 u8 emmc_mode; /* Offset 0x0133 */ 80 u8 usb3_clk_ssc; /* Offset 0x0134 */ 81 u8 disp_clk_ssc; /* Offset 0x0135 */ 82 u8 sata_clk_ssc; /* Offset 0x0136 */ 83 u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */ 84 u8 usb2_port0_txi_set; /* Offset 0x0138 */ 85 u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */ 86 u8 usb2_port0_tx_pe_half; /* Offset 0x013a */ 87 u8 usb2_port1_pe_txi_set; /* Offset 0x013b */ 88 u8 usb2_port1_txi_set; /* Offset 0x013c */ 89 u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */ 90 u8 usb2_port1_tx_pe_half; /* Offset 0x013e */ 91 u8 usb2_port2_pe_txi_set; /* Offset 0x013f */ 92 u8 usb2_port2_txi_set; /* Offset 0x0140 */ 93 u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */ 94 u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */ 95 u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */ 96 u8 usb2_port3_txi_set; /* Offset 0x0144 */ 97 u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */ 98 u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */ 99 u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */ 100 u8 usb2_port4_txi_set; /* Offset 0x0148 */ 101 u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */ 102 u8 usb2_port4_tx_pe_half; /* Offset 0x014a */ 103 u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */ 104 u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */ 105 u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */ 106 u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */ 107 u8 sata_speed; /* Offset 0x014f */ 108 u8 usb_ssic_port; /* Offset 0x0150 */ 109 u8 usb_hsic_port; /* Offset 0x0151 */ 110 u8 pcie_rootport_speed; /* Offset 0x0152 */ 111 u8 enable_ssic; /* Offset 0x0153 */ 112 u32 logo_ptr; /* Offset 0x0154 */ 113 u32 logo_size; /* Offset 0x0158 */ 114 u8 rtc_lock; /* Offset 0x015c */ 115 u8 pmic_i2c_bus; /* Offset 0x015d */ 116 u8 enable_isp; /* Offset 0x015e */ 117 u8 isp_pci_dev_config; /* Offset 0x015f */ 118 u8 turbo_mode; /* Offset 0x0160 */ 119 u8 pnp_settings; /* Offset 0x0161 */ 120 u8 sd_detect_chk; /* Offset 0x0162 */ 121 u8 reserved[411]; /* Offset 0x0163 */ 122}; 123 124#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */ 125#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */ 126 127struct __packed upd_region { 128 u64 signature; /* Offset 0x0000 */ 129 u8 revision; /* Offset 0x0008 */ 130 u8 unused0[7]; /* Offset 0x0009 */ 131 u32 memory_upd_offset; /* Offset 0x0010 */ 132 u32 silicon_upd_offset; /* Offset 0x0014 */ 133 u64 unused1; /* Offset 0x0018 */ 134 struct memory_upd memory_upd; /* Offset 0x0020 */ 135 struct silicon_upd silicon_upd; /* Offset 0x0100 */ 136 u16 terminator; /* Offset 0x02fe */ 137}; 138 139#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ 140 141struct __packed vpd_region { 142 u64 sign; /* Offset 0x0000 */ 143 u32 img_rev; /* Offset 0x0008 */ 144 u32 upd_offset; /* Offset 0x000c */ 145}; 146 147#endif /* __FSP_VPD_H__ */ 148