1/* SPDX-License-Identifier: Intel */ 2/* 3 * Copyright (C) 2013, Intel Corporation 4 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 5 * 6 * Ported from Intel released Quark UEFI BIOS 7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 8 */ 9 10#ifndef _MRC_H_ 11#define _MRC_H_ 12 13#define MRC_VERSION 0x0111 14 15/* architectural definitions */ 16#define NUM_CHANNELS 1 /* number of channels */ 17#define NUM_RANKS 2 /* number of ranks per channel */ 18#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */ 19 20/* software limitations */ 21#define MAX_CHANNELS 1 22#define MAX_RANKS 2 23#define MAX_BYTE_LANES 4 24 25#define MAX_SOCKETS 1 26#define MAX_SIDES 1 27#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS) 28 29/* Specify DRAM and channel width */ 30enum { 31 X8, /* DRAM width */ 32 X16, /* DRAM width & Channel Width */ 33 X32 /* Channel Width */ 34}; 35 36/* Specify DRAM speed */ 37enum { 38 DDRFREQ_800, 39 DDRFREQ_1066 40}; 41 42/* Specify DRAM type */ 43enum { 44 DDR3, 45 DDR3L 46}; 47 48/* 49 * density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb 50 * cl: DRAM CAS Latency in clocks 51 * ras: ACT to PRE command period 52 * wtr: Delay from start of internal write transaction to internal read command 53 * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K) 54 * faw: Four activate window (JESD79 specific to page size 1K/2K) 55 * 56 * ras/wtr/rrd/faw timings are in picoseconds 57 * 58 * Refer to JEDEC spec (or DRAM datasheet) when changing these values. 59 */ 60struct dram_params { 61 uint8_t density; 62 uint8_t cl; 63 uint32_t ras; 64 uint32_t wtr; 65 uint32_t rrd; 66 uint32_t faw; 67}; 68 69/* 70 * Delay configuration for individual signals 71 * Vref setting 72 * Scrambler seed 73 */ 74struct mrc_timings { 75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES]; 80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS]; 81 uint32_t wcmd[NUM_CHANNELS]; 82 uint32_t scrambler_seed; 83 /* need to save for the case of frequency change */ 84 uint8_t ddr_speed; 85}; 86 87/* Boot mode defined as bit mask (1<<n) */ 88enum { 89 BM_UNKNOWN, 90 BM_COLD = 1, /* full training */ 91 BM_FAST = 2, /* restore timing parameters */ 92 BM_S3 = 4, /* resume from S3 */ 93 BM_WARM = 8 94}; 95 96/* MRC execution status */ 97#define MRC_SUCCESS 0 /* initialization ok */ 98#define MRC_E_MEMTEST 1 /* memtest failed */ 99 100/* 101 * Memory Reference Code parameters 102 * 103 * It includes 3 parts: 104 * - input parameters like boot mode and DRAM parameters 105 * - context parameters for MRC internal state 106 * - output parameters like initialization result and memory size 107 */ 108struct mrc_params { 109 /* Input parameters */ 110 uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */ 111 /* DRAM parameters */ 112 uint8_t dram_width; /* x8, x16 */ 113 uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */ 114 uint8_t ddr_type; /* DDR3, DDR3L */ 115 uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */ 116 uint8_t scrambling_enables; /* 0, 1 */ 117 /* 1, 3 (1'st rank has to be populated if 2'nd rank present) */ 118 uint32_t rank_enables; 119 uint32_t channel_enables; /* 1 only */ 120 uint32_t channel_width; /* x16 only */ 121 /* 0, 1, 2 (mode 2 forced if ecc enabled) */ 122 uint32_t address_mode; 123 /* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */ 124 uint8_t refresh_rate; 125 /* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */ 126 uint8_t sr_temp_range; 127 /* 128 * RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED 129 * (select MRS1.DIC driver impedance control) 130 */ 131 uint8_t ron_value; 132 /* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ 133 uint8_t rtt_nom_value; 134 /* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ 135 uint8_t rd_odt_value; 136 struct dram_params params; 137 /* Internally used context parameters */ 138 uint32_t board_id; /* board layout (use x8 or x16 memory) */ 139 uint32_t hte_setup; /* when set hte reconfiguration requested */ 140 uint32_t menu_after_mrc; 141 uint32_t power_down_disable; 142 uint32_t tune_rcvn; 143 uint32_t channel_size[NUM_CHANNELS]; 144 uint32_t column_bits[NUM_CHANNELS]; 145 uint32_t row_bits[NUM_CHANNELS]; 146 uint32_t mrs1; /* register content saved during training */ 147 uint8_t first_run; 148 /* Output parameters */ 149 /* initialization result (non zero specifies error code) */ 150 uint32_t status; 151 /* total memory size in bytes (excludes ECC banks) */ 152 uint32_t mem_size; 153 /* training results (also used on input) */ 154 struct mrc_timings timings; 155}; 156 157/* 158 * MRC memory initialization structure 159 * 160 * post_code: a 16-bit post code of a specific initialization routine 161 * boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3 162 * init_fn: real memory initialization routine 163 */ 164struct mem_init { 165 uint16_t post_code; 166 uint16_t boot_path; 167 void (*init_fn)(struct mrc_params *mrc_params); 168}; 169 170/* MRC platform data flags */ 171#define MRC_FLAG_ECC_EN 0x00000001 172#define MRC_FLAG_SCRAMBLE_EN 0x00000002 173#define MRC_FLAG_MEMTEST_EN 0x00000004 174/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ 175#define MRC_FLAG_TOP_TREE_EN 0x00000008 176/* If set ODR signal is asserted to DRAM devices on writes */ 177#define MRC_FLAG_WR_ODT_EN 0x00000010 178 179/** 180 * mrc_init - Memory Reference Code initialization entry routine 181 * 182 * @mrc_params: parameters for MRC 183 */ 184void mrc_init(struct mrc_params *mrc_params); 185 186#endif /* _MRC_H_ */ 187