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11#include <common.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/arch/hardware.h>
14#include <asm/arch/mux.h>
15#include <asm/io.h>
16#include <i2c.h>
17
18static struct module_pin_mux spi0_pin_mux[] = {
19
20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
21
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
23
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
25
26 {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
27
28 {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
29 {-1},
30};
31
32static struct module_pin_mux dcan0_pin_mux[] = {
33
34 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
35
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
37 {-1},
38};
39
40static struct module_pin_mux dcan1_pin_mux[] = {
41
42 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
43
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
45 {-1},
46};
47
48static struct module_pin_mux gpios[] = {
49
50 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
51
52 {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
53
54 {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
55
56 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
57
58 {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
59
60 {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
61
62 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
63
64 {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
65
66 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
67
68 {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
69
70 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
71
72 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
73
74 {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
75
76 {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
77
78 {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
79
80 {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
81
82 {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
83 {-1},
84};
85
86static struct module_pin_mux uart0_pin_mux[] = {
87
88 {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
89
90 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
91
92 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
93 {-1},
94};
95
96static struct module_pin_mux i2c0_pin_mux[] = {
97
98 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
99
100 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
101 {-1},
102};
103
104static struct module_pin_mux mii1_pin_mux[] = {
105 {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
106 {OFFSET(mii1_col), MODE(0) | RXACTIVE},
107 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
108 {OFFSET(mii1_txen), MODE(0)},
109 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
110 {OFFSET(mii1_txd3), MODE(0)},
111 {OFFSET(mii1_txd2), MODE(0)},
112 {OFFSET(mii1_txd1), MODE(0)},
113 {OFFSET(mii1_txd0), MODE(0)},
114 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
115 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
116 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
117 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
118 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
119 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
120 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
121 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
122 {-1},
123};
124
125static struct module_pin_mux mmc1_pin_mux[] = {
126 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},
127 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},
128 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},
129 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},
130 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},
131 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},
132 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},
133 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},
134 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},
135 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},
136 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},
137 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},
138
139 {-1},
140};
141
142static struct module_pin_mux lcd_pin_mux[] = {
143 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
144 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
145 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
146 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
147 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
148 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
149 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
150 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
151 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
152 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
153 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
154 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
155 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
156 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
157 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
158 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
159
160 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},
161 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},
162 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},
163 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},
164 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},
165 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},
166 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},
167 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},
168
169 {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},
170 {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},
171 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},
172 {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},
173
174 {-1},
175};
176
177void enable_uart0_pin_mux(void)
178{
179 configure_module_pin_mux(uart0_pin_mux);
180}
181
182void enable_i2c_pin_mux(void)
183{
184 configure_module_pin_mux(i2c0_pin_mux);
185}
186
187void enable_board_pin_mux(void)
188{
189 configure_module_pin_mux(i2c0_pin_mux);
190 configure_module_pin_mux(mii1_pin_mux);
191 configure_module_pin_mux(spi0_pin_mux);
192 configure_module_pin_mux(dcan0_pin_mux);
193 configure_module_pin_mux(dcan1_pin_mux);
194 configure_module_pin_mux(mmc1_pin_mux);
195 configure_module_pin_mux(lcd_pin_mux);
196 configure_module_pin_mux(gpios);
197}
198