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10#include <common.h>
11#include <cpu_func.h>
12#include <init.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/iomux-mx53.h>
16#include <asm/global_data.h>
17#include <asm/mach-imx/mx5_video.h>
18#include <ACEX1K.h>
19#include <asm/gpio.h>
20#include <linux/delay.h>
21
22enum LED_GPIOS {
23 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
24 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
25 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
26 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
27 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
28 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
29 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
30 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
31 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
32 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
33 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
34 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
35 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
36 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
37 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
38};
39
40#define CCAT_BASE_ADDR ((void *)0xf0000000)
41#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
42#define CCAT_SIZE 1191788
43#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
44static const char CCAT_SIGNATURE[] = "CCAT";
45
46static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
47static const u32 CCAT_MODE_RUN = 0x0033DC8F;
48
49DECLARE_GLOBAL_DATA_PTR;
50
51#ifdef CONFIG_REVISION_TAG
52u32 get_board_rev(void)
53{
54 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
55 struct fuse_bank *bank = &iim->bank[0];
56 struct fuse_bank0_regs *fuse =
57 (struct fuse_bank0_regs *)bank->fuse_regs;
58
59 int rev = readl(&fuse->gp[6]);
60
61 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
62}
63#endif
64
65
66
67
68
69void weim_cs0_settings(u32 mode)
70{
71 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
72
73 writel(0x0, &weim_regs->cs0gcr1);
74 writel(mode, &weim_regs->cs0gcr1);
75 writel(0x00001002, &weim_regs->cs0gcr2);
76
77 writel(0x04000000, &weim_regs->cs0rcr1);
78 writel(0x00000000, &weim_regs->cs0rcr2);
79
80 writel(0x04000000, &weim_regs->cs0wcr1);
81 writel(0x00000000, &weim_regs->cs0wcr2);
82}
83
84static void setup_gpio_eim(void)
85{
86 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
87 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
88 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
89 gpio_direction_input(GPIO_C3_STATUS);
90 gpio_direction_input(GPIO_C3_DONE);
91 gpio_direction_output(GPIO_C3_CONFIG, 1);
92
93 weim_cs0_settings(CCAT_MODE_RUN);
94}
95
96static void setup_gpio_sups(void)
97{
98 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
99 gpio_direction_input(GPIO_SUPS_INT);
100
101 static const int BLINK_INTERVALL = 50000;
102 int status = 1;
103 while (gpio_get_value(GPIO_SUPS_INT)) {
104
105 gpio_set_value(GPIO_LED_PWR_R,
106 (++status / BLINK_INTERVALL) % 2);
107 }
108
109
110 gpio_set_value(GPIO_LED_PWR_R, 1);
111}
112
113static void setup_gpio_leds(void)
114{
115 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
116 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
117 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
118 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
119 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
120 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
121 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
122 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
123 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
124
125 gpio_direction_output(GPIO_LED_SD2_R, 0);
126 gpio_direction_output(GPIO_LED_SD2_B, 0);
127 gpio_direction_output(GPIO_LED_SD2_G, 0);
128 gpio_direction_output(GPIO_LED_SD1_R, 0);
129 gpio_direction_output(GPIO_LED_SD1_B, 0);
130 gpio_direction_output(GPIO_LED_SD1_G, 0);
131 gpio_direction_output(GPIO_LED_PWR_R, 0);
132 gpio_direction_output(GPIO_LED_PWR_B, 0);
133 gpio_direction_output(GPIO_LED_PWR_G, 0);
134}
135
136static int power_init(void)
137{
138
139 return 0;
140}
141
142static void clock_1GHz(void)
143{
144 int ret;
145 u32 ref_clk = MXC_HCLK;
146
147
148
149
150 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
151 if (ret)
152 printf("CPU: Switch CPU clock to 1GHZ failed\n");
153
154 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
155 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
156 if (ret)
157 printf("CPU: Switch DDR clock to 400MHz failed\n");
158}
159
160int board_early_init_f(void)
161{
162
163 return 0;
164}
165
166int board_init(void)
167{
168 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
169
170 mxc_set_sata_internal_clock();
171
172 setup_gpio_leds();
173 setup_gpio_sups();
174 setup_gpio_eim();
175 setup_iomux_lcd();
176
177 return 0;
178}
179
180int checkboard(void)
181{
182 puts("Board: Beckhoff CX9020\n");
183
184 return 0;
185}
186
187static int ccat_config_fn(int assert_config, int flush, int cookie)
188{
189
190 weim_cs0_settings(CCAT_MODE_CONFIG);
191 gpio_set_value(GPIO_C3_CONFIG, 0);
192 udelay(1);
193 gpio_set_value(GPIO_C3_CONFIG, 1);
194 udelay(230);
195
196 return FPGA_SUCCESS;
197}
198
199static int ccat_status_fn(int cookie)
200{
201 return FPGA_FAIL;
202}
203
204static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
205{
206 const uint8_t *const buffer = buf;
207
208
209 int i;
210 for (i = 0; i < buf_len; ++i)
211 writeb(buffer[i], CCAT_BASE_ADDR);
212
213 writeb(0xff, CCAT_BASE_ADDR);
214 writeb(0xff, CCAT_BASE_ADDR);
215
216 return FPGA_SUCCESS;
217}
218
219static int ccat_done_fn(int cookie)
220{
221
222 return gpio_get_value(GPIO_C3_DONE);
223}
224
225static int ccat_post_fn(int cookie)
226{
227
228 weim_cs0_settings(CCAT_MODE_RUN);
229 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
230
231 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
232 printf("Verifing CCAT firmware failed, signature not found\n");
233 return FPGA_FAIL;
234 }
235
236
237 gpio_set_value(GPIO_LED_PWR_R, 1);
238 gpio_set_value(GPIO_LED_PWR_G, 1);
239 gpio_set_value(GPIO_LED_PWR_B, 0);
240 return FPGA_SUCCESS;
241}
242
243static Altera_CYC2_Passive_Serial_fns ccat_fns = {
244 .config = ccat_config_fn,
245 .status = ccat_status_fn,
246 .done = ccat_done_fn,
247 .write = ccat_write_fn,
248 .abort = ccat_post_fn,
249 .post = ccat_post_fn,
250};
251
252static Altera_desc ccat_fpga = {
253 .family = Altera_CYC2,
254 .iface = passive_serial,
255 .size = CCAT_SIZE,
256 .iface_fns = &ccat_fns,
257 .base = CCAT_BASE_ADDR,
258};
259
260int board_late_init(void)
261{
262 if (!power_init())
263 clock_1GHz();
264
265 fpga_init();
266 fpga_add(fpga_altera, &ccat_fpga);
267
268 return 0;
269}
270
