LXR uboot/board/compulab/cm_t43/cm

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015 Compulab, Ltd.
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <miiphy.h>
   9#include <cpsw.h>
  10#include <net.h>
  11#include <asm/global_data.h>
  12#include <asm/gpio.h>
  13#include <asm/arch/sys_proto.h>
  14#include <asm/emif.h>
  15#include <linux/delay.h>
  16#include <power/pmic.h>
  17#include <power/tps65218.h>
  18#include "board.h"
  19#include <usb.h>
  20#include <asm/omap_common.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  25
  26/* setup board specific PMIC */
  27int power_init_board(void)
  28{
  29        struct pmic *p;
  30        uchar tps_status = 0;
  31
  32        power_tps65218_init(I2C_PMIC);
  33        p = pmic_get("TPS65218_PMIC");
  34        if (p && !pmic_probe(p)) {
  35                puts("PMIC:  TPS65218\n");
  36                /* We don't care if fseal is locked, but we do need it set */
  37                tps65218_lock_fseal();
  38                tps65218_reg_read(TPS65218_STATUS, &tps_status);
  39                if (!(tps_status & TPS65218_FSEAL))
  40                        printf("WARNING: RTC not backed by battery!\n");
  41        }
  42
  43        return 0;
  44}
  45
  46int board_init(void)
  47{
  48        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  49        gpmc_init();
  50        set_i2c_pin_mux();
  51        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  52        i2c_probe(TPS65218_CHIP_PM);
  53
  54        return 0;
  55}
  56
  57int board_usb_init(int index, enum usb_init_type init)
  58{
  59        enable_usb_clocks(index);
  60        return 0;
  61}
  62
  63int board_usb_cleanup(int index, enum usb_init_type init)
  64{
  65        disable_usb_clocks(index);
  66        return 0;
  67}
  68
  69#ifdef CONFIG_DRIVER_TI_CPSW
  70
  71static void cpsw_control(int enabled)
  72{
  73        return;
  74}
  75
  76static struct cpsw_slave_data cpsw_slaves[] = {
  77        {
  78                .slave_reg_ofs  = 0x208,
  79                .sliver_reg_ofs = 0xd80,
  80                .phy_addr       = 0,
  81                .phy_if         = PHY_INTERFACE_MODE_RGMII,
  82        },
  83        {
  84                .slave_reg_ofs  = 0x308,
  85                .sliver_reg_ofs = 0xdc0,
  86                .phy_addr       = 1,
  87                .phy_if         = PHY_INTERFACE_MODE_RGMII,
  88        },
  89};
  90
  91static struct cpsw_platform_data cpsw_data = {
  92        .mdio_base              = CPSW_MDIO_BASE,
  93        .cpsw_base              = CPSW_BASE,
  94        .mdio_div               = 0xff,
  95        .channels               = 8,
  96        .cpdma_reg_ofs          = 0x800,
  97        .slaves                 = 2,
  98        .slave_data             = cpsw_slaves,
  99        .ale_reg_ofs            = 0xd00,
 100        .ale_entries            = 1024,
 101        .host_port_reg_ofs      = 0x108,
 102        .hw_stats_reg_ofs       = 0x900,
 103        .bd_ram_ofs             = 0x2000,
 104        .mac_control            = (1 << 5),
 105        .control                = cpsw_control,
 106        .host_port_num          = 0,
 107        .version                = CPSW_CTRL_VERSION_2,
 108};
 109
 110#define GPIO_PHY1_RST           170
 111#define GPIO_PHY2_RST           168
 112
 113int board_phy_config(struct phy_device *phydev)
 114{
 115        unsigned short val;
 116
 117        /* introduce tx clock delay */
 118        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 119        val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 120        val |= 0x0100;
 121        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 122
 123        if (phydev->drv->config)
 124                return phydev->drv->config(phydev);
 125
 126        return 0;
 127}
 128
 129static void board_phy_init(void)
 130{
 131        set_mdio_pin_mux();
 132        writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
 133        writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
 134        writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
 135
 136        /* For revision A */
 137        writel(0x2000009, 0x44df2e6c);
 138        writel(0x38a, 0x44df2e70);
 139
 140        mdelay(10);
 141
 142        gpio_request(GPIO_PHY1_RST, "phy1_rst");
 143        gpio_request(GPIO_PHY2_RST, "phy2_rst");
 144        gpio_direction_output(GPIO_PHY1_RST, 0);
 145        gpio_direction_output(GPIO_PHY2_RST, 0);
 146        mdelay(2);
 147
 148        gpio_set_value(GPIO_PHY1_RST, 1);
 149        gpio_set_value(GPIO_PHY2_RST, 1);
 150        mdelay(2);
 151}
 152
 153int board_eth_init(struct bd_info *bis)
 154{
 155        int rv;
 156
 157        set_rgmii_pin_mux();
 158        writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 159        board_phy_init();
 160
 161        rv = cpsw_register(&cpsw_data);
 162        if (rv < 0)
 163                printf("Error %d registering CPSW switch\n", rv);
 164
 165        return rv;
 166}
 167#endif
 168