LXR uboot/board/cssi/MCR3000/MCR3000.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010-2017 CS Systemes d'Information
   4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5 * Christophe Leroy <christophe.leroy@c-s.fr>
   6 *
   7 * Board specific routines for the MCR3000 board
   8 */
   9
  10#include <common.h>
  11#include <env.h>
  12#include <hwconfig.h>
  13#include <init.h>
  14#include <mpc8xx.h>
  15#include <fdt_support.h>
  16#include <serial.h>
  17#include <asm/global_data.h>
  18#include <asm/io.h>
  19#include <dm/uclass.h>
  20#include <wdt.h>
  21#include <linux/delay.h>
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25#define SDRAM_MAX_SIZE                  (32 * 1024 * 1024)
  26
  27static const uint cs1_dram_table_66[] = {
  28        /* DRAM - single read. (offset 0 in upm RAM) */
  29        0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  30        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  31
  32        /* DRAM - burst read. (offset 8 in upm RAM) */
  33        0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  34        0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  35        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  36        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  37
  38        /* DRAM - single write. (offset 18 in upm RAM) */
  39        0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  40        0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  41
  42        /* DRAM - burst write. (offset 20 in upm RAM) */
  43        0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  44        0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  45        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  46        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  47
  48        /* refresh  (offset 30 in upm RAM) */
  49        0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  50        0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  51
  52        /* init */
  53        0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  54
  55        /* exception. (offset 3c in upm RAM) */
  56        0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  57};
  58
  59int ft_board_setup(void *blob, struct bd_info *bd)
  60{
  61        const char *sync = "receive";
  62
  63        ft_cpu_setup(blob, bd);
  64
  65        /* BRG */
  66        do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  67                             bd->bi_busfreq, 1);
  68
  69        /* MAC addr */
  70        fdt_fixup_ethernet(blob);
  71
  72        /* Bus Frequency for CPM */
  73        do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  74
  75        /* E1 interface - Set data rate */
  76        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  77
  78        /* E1 interface - Set channel phase to 0 */
  79        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  80
  81        /* E1 interface - rising edge sync pulse transmit */
  82        do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  83                         sync, strlen(sync), 1);
  84
  85        return 0;
  86}
  87
  88int checkboard(void)
  89{
  90        serial_puts("BOARD: MCR3000 CSSI\n");
  91
  92        return 0;
  93}
  94
  95int dram_init(void)
  96{
  97        immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  98        memctl8xx_t __iomem *memctl = &immap->im_memctl;
  99
 100        printf("UPMA init for SDRAM (CAS latency 2), ");
 101        printf("init address 0x%08x, size ", (int)dram_init);
 102        /* Configure UPMA for cs1 */
 103        upmconfig(UPMA, (uint *)cs1_dram_table_66,
 104                  sizeof(cs1_dram_table_66) / sizeof(uint));
 105        udelay(10);
 106        out_be16(&memctl->memc_mptpr, 0x0200);
 107        out_be32(&memctl->memc_mamr, 0x14904000);
 108        udelay(10);
 109        out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 110        out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 111        udelay(10);
 112        out_be32(&memctl->memc_mcr, 0x80002830);
 113        out_be32(&memctl->memc_mar, 0x00000088);
 114        out_be32(&memctl->memc_mcr, 0x80002038);
 115        udelay(200);
 116
 117        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 118                                    SDRAM_MAX_SIZE);
 119
 120        return 0;
 121}
 122
 123int misc_init_r(void)
 124{
 125        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 126        iop8xx_t __iomem *iop = &immr->im_ioport;
 127
 128        /* Set port C13 as GPIO (BTN_ACQ_AL) */
 129        clrbits_be16(&iop->iop_pcpar, 0x4);
 130        clrbits_be16(&iop->iop_pcdir, 0x4);
 131
 132        /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 133        if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 134                env_set("bootdelay", "60");
 135
 136        return 0;
 137}
 138
 139int board_early_init_f(void)
 140{
 141        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 142
 143        /*
 144         * Erase FPGA(s) for reboot
 145         */
 146        clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 147        setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 148        udelay(1);                              /* Wait more than 300ns */
 149        setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 150
 151        return 0;
 152}
 153
 154int board_early_init_r(void)
 155{
 156        struct udevice *watchdog_dev = NULL;
 157
 158        if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 159                puts("Cannot find watchdog!\n");
 160        } else {
 161                puts("Enabling watchdog.\n");
 162                wdt_start(watchdog_dev, 0xffff, 0);
 163        }
 164
 165        return 0;
 166}
 167